CN219107415U - Comparator - Google Patents

Abstract

The utility model discloses a comparator, which relates to the field of circuits and comprises a first input module, a first control module, a first acceleration module, a first output switch, a first regulation switch, a second output switch, a second regulation switch, a first voltage dividing module, a second voltage dividing module and an inverter, wherein when the first voltage of a first normal phase input end of the comparator is smaller than the second voltage of a first reverse phase input end of the comparator, the first acceleration module can further control the current reduction of the second output end of the first control module and the voltage increase of the first output end so as to improve the conversion speed of the first output switch and the second output switch, so that the voltage conversion of an output signal of the comparator from a low level to a high level is faster, the delay is shorter, the signal conversion speed is greatly improved, the processing speed of the comparator is improved, the transmission delay is reduced, the improvement of the processing speed of the whole comparator is realized, and the application range of the comparator is expanded under the condition of low power consumption.

Description

Comparator

Technical Field

The present utility model relates to the field of circuits, and in particular, to a comparator.

Background

With the improvement of the performance and the wide application of the information processing system, the performance requirements of users on each module in the system are also higher and higher, especially, the comparator, which is an indispensable part of the system, has a great influence on the processing speed of the whole information processing system. The existing comparator generally has certain delay in the processing process, particularly when the difference value of input signals is smaller, larger delay is generated, and the requirement of high-speed processing under the condition of small signal input cannot be well met, so that how to improve the processing speed of the comparator plays an important role in the development of an information processing system.

In the prior art, in order to increase the processing speed of the comparator, the working current of the comparator is generally increased to increase the processing speed of the comparator, but this way causes high power consumption, causes extra resource waste, and is not beneficial to the application of the whole information processing system.

Disclosure of Invention

The utility model aims to provide a comparator, which can enable the voltage conversion of an output signal of the comparator from a low level to a high level to be faster, delay to be shorter, greatly improve the signal conversion speed, improve the processing speed of the comparator, reduce transmission delay, particularly reduce the transmission delay when the voltage difference of an input signal of the comparator is smaller, realize the improvement of the processing speed of the whole comparator under the condition of low power consumption, and expand the application range of the comparator.

In order to solve the technical problems, the utility model provides a comparator, which comprises a first input module, a first control module, a first acceleration module, a first output switch, a first adjustment switch, a second output switch, a second adjustment switch, a first voltage division module, a second voltage division module and an inverter; the first input end of the first input module is used as a first non-inverting input end of the comparator, the second input end of the first input module is used as a first inverting input end of the comparator, and the output end of the inverter is used as an output end of the comparator;

The first end of the first output switch is respectively connected with the first end of the first adjusting switch, the control end of the first output switch is connected with the first end of the second output switch, the second end of the first output switch is grounded, the control end of the first adjusting switch is connected with a first fixed bias voltage, the second end of the first adjusting switch is connected with the first end of the first voltage dividing module, the first end of the second voltage dividing module is respectively connected with the second end of the first voltage dividing module and the input end of the inverter, the second end of the second voltage dividing module is connected with the second end of the second adjusting switch, the control end of the second adjusting switch is connected with a second fixed bias voltage, the first end of the second adjusting switch is connected with the first end and the control end of the second output switch, and the second end of the second output switch is connected with a power supply; the first adjusting switch and the second adjusting switch are in a normally-on state;

the input end of the first control module is connected with the output end of the first input module, the first output end of the first control module is connected with the control end of the first output switch, the second output end of the first control module is connected with the second end of the second regulation switch, and the first control module is used for regulating the voltage of the first output end to enable the first output switch to be conducted and regulating the current of the second output end to enable the second output switch to be turned off based on the control of the first input module when the first voltage of the first non-inverting input end of the comparator is larger than the second voltage of the first inverting input end of the comparator; when the first voltage is smaller than the second voltage, adjusting the voltage of a first output end based on the control of the first input module to enable the first output switch to be turned off, and adjusting the current of a second output end to enable the second output switch to be turned on;

The first acceleration module is respectively connected with the first input module and the first control module, and is used for controlling the current of the second output end of the first control module to be reduced so as to increase the voltage of the control end of the second output switch and controlling the voltage of the first output end of the first control module to be increased when the first voltage is smaller than the second voltage.

Preferably, the first acceleration module comprises a start switch and a common gate amplifier; the first end of the starting switch is connected with the first input module, and the second end of the starting switch is connected with the first input module and the first control module respectively;

the input end of the common gate amplifier is respectively connected with the first input module and the first control module, the output end of the common gate amplifier is connected with the control end of the starting switch, and the common gate amplifier is used for controlling the starting switch to be conducted when the first voltage is smaller than the second voltage so as to control the current of the second output end of the first control module to be reduced so as to enable the voltage of the control end of the second output switch to be increased, and controlling the voltage of the first output end of the first control module to be increased.

Preferably, the common gate amplifier includes a first current source, a second current source, a first switch, a second switch, a third switch, a fourth switch, and a third voltage dividing module;

The first switch is connected with the control end of the second switch and is connected with a third fixed bias voltage, the third switch is connected with the control end of the fourth switch, the first end of the first switch is connected with the output end of the first current source, the first end of the second switch is connected with the output end of the second current source, the input end of the first current source and the input end of the second current source are respectively connected with a power supply, the second end of the first switch is respectively connected with the second end of the third switch and the control end of the third switch, the second end of the second switch is respectively connected with the second end of the fourth switch and the control end of the starting switch, the first end of the third switch is connected with the first end of the third voltage dividing module, the second end of the third voltage dividing module is respectively connected with the first input module and the first control module, the third end of the third voltage dividing module is respectively connected with the first end of the first voltage dividing module and the first end of the fourth switch is respectively connected with the first input module and the first end of the fourth voltage dividing module.

Preferably, the first input module includes a third current source, a fifth switch and a sixth switch;

The input end of the third current source is connected with a power supply, the first ends of the fifth switch and the sixth switch are respectively connected with the output end of the third current source, the output end of the third current source is also connected with the first acceleration module, the control end of the fifth switch is used as a first normal phase input end of the comparator, the control end of the sixth switch is used as a first reverse phase input end of the comparator, the second ends of the fifth switch and the sixth switch are respectively connected with the input end of the first control module, and the second ends of the fifth switch and the sixth switch are respectively connected with the first acceleration module.

Preferably, the first control module includes a fourth current source, a first load switch, a second load switch, a third load switch, a fourth load switch, and a fifth load switch;

the first end of the first load switch is respectively connected with the output end of the first input module and the first end of the third load switch, the second end of the first load switch is grounded, the control end of the first load switch is respectively connected with the control end of the fourth load switch, the second end of the third load switch is connected with the output end of the fourth current source, the input end of the fourth current source is connected with a power supply, the first end of the second load switch is respectively connected with the output end of the first input module, the first end of the fourth load switch is connected with the first end of the fifth load switch, the second end of the fourth load switch is grounded, the control end of the third load switch is respectively connected with the control end of the fourth load switch, the control end of the fifth load switch is connected with the fourth fixed bias voltage, the second end of the fourth load switch is connected with the control end of the first output switch, and the second end of the fifth load switch is connected with the second end of the second adjustment switch.

Preferably, the inverter includes a first inverting switch and a second inverting switch;

the first end of the first inverting switch is connected with a power supply, the second end of the first inverting switch is used as the output end of the comparator and is connected with the second end of the second inverting switch, the first end of the second inverting switch is grounded, and the control end of the first inverting switch is respectively connected with the control end of the second inverting switch and the first end of the second voltage dividing module.

Preferably, the system further comprises a first control switch, a second control switch, a first quiescent current module and a second quiescent current module;

the first end of the first control switch is respectively connected with the first output end of the first control module, the control end of the first output switch is connected with the second end of the second control switch, the second end of the first control switch is respectively connected with the control end of the second output switch and the first end of the second control switch, the control end of the first control switch is connected with the first static current module, and the control end of the second control switch is connected with the second static current module; the first end of the first static current module is connected with the power supply, the second end of the first static current module is grounded, the first end of the second static current module is connected with the power supply, and the second end of the second static current module is grounded;

The first quiescent current module is used for providing a bias quiescent current for the first control switch, and the second quiescent current module is used for providing a bias quiescent current for the second control switch.

Preferably, the first quiescent current module includes a fifth current source, a first current switch and a second current switch;

the first end of the fifth current source is connected with the power supply, the second end of the fifth current source is respectively connected with the control end of the first control switch, the control end of the first current switch is connected with the first end of the first current switch, the second end of the first current switch is respectively connected with the control end of the second current switch and the first end of the second current switch, and the second end of the second current switch is grounded.

Preferably, the second quiescent current module includes a sixth current source, a third current switch and a fourth current switch;

the first end of the sixth current source is grounded, the second end of the sixth current source is respectively connected with the control end of the second control switch, the control end of the third current switch is connected with the first end of the third current switch, the second end of the third current switch is respectively connected with the control end of the fourth current switch and the first end of the fourth current switch, and the second end of the fourth current switch is connected with the power supply.

Preferably, the system further comprises a second input module, a second control module and a second acceleration module; the first input end of the second input module is used as a second non-inverting input end of the comparator, and the second input end of the second input module is used as a second inverting input end of the comparator;

the input end of the second control module is connected with the output end of the second input module, the first output end of the second control module is connected with the control end of the second output switch, the second output end of the second control module is connected with the second end of the first adjusting switch, and the second control module is used for adjusting the voltage of the first output end based on the control of the second input module to enable the second output switch to be turned off and adjusting the current of the second output end to enable the first output switch to be turned on when the third voltage of the second non-inverting input end of the comparator is larger than the fourth voltage of the second inverting input end of the comparator; when the third voltage is smaller than the fourth voltage, adjusting the voltage of the first output end based on the control of the second input module to enable the second output switch to be on, and adjusting the current of the second output end to enable the first output switch to be off;

the second acceleration module is respectively connected with the second input module and the second control module, and is used for controlling the current of the second output end of the second control module to be reduced so as to increase the voltage of the control end of the first output switch and controlling the voltage of the first output end of the second control module to be increased when the third voltage is smaller than the fourth voltage.

The utility model provides a comparator, which comprises a first input module, a first control module, a first acceleration module, a first output switch, a first regulation switch, a second output switch, a second regulation switch, a first voltage division module, a second voltage division module and an inverter, wherein the first control module regulates output signals based on the control of the first input module, controls the on and off of the first output switch through the voltage of the first output end, controls the on and off of the second output switch through the current of the second output end, so that the comparator outputs different values, when the first voltage of a first positive input end of the comparator is smaller than the second voltage of a first negative input end of the comparator, the first acceleration module can further control the current of the second output end of the first control module to be reduced and the voltage of the first output end to be increased, so that the conversion speed of the first output switch and the second output switch is increased, the output signals of the comparator are enabled to be converted from low level to high level to be faster, the time delay is shorter, the conversion speed of the signals is enabled to be increased, the conversion speed of the comparator is enabled to be greatly prolonged, and the time delay of the comparator is enabled to be greatly increased, and the transmission speed of the comparator is enabled to be lower when the voltage difference is lower than the comparator is applied to the low-speed.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required in the prior art and the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a comparator according to the present utility model;

FIG. 2 is a schematic diagram of another comparator according to the present utility model;

FIG. 3 is a schematic diagram of a transconductance linear loop according to the present utility model;

fig. 4 is a timing diagram of a comparator according to the present utility model without and with an acceleration module.

Detailed Description

The utility model has the core that the utility model provides the comparator, the conversion speed of the first output switch and the second output switch can be improved, the voltage conversion of the output signal of the comparator from low level to high level is faster, the delay is shorter, the signal conversion speed is greatly improved, the processing speed of the comparator is improved, the transmission delay is reduced, particularly the transmission delay when the voltage difference of the input signal of the comparator is smaller is reduced, the improvement of the processing speed of the whole comparator is realized under the condition of low power consumption, and the application range of the comparator is expanded.

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are some embodiments of the present utility model, but not all embodiments of the present utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

The comparator provided by the utility model can reduce the transmission delay, and as the input signal of the comparator is changed from a positive input end smaller than an opposite input end to a positive input end larger than the opposite input end, the output signal of the comparator is changed from a low level to a high level, and the delay from the change of the input signal to the middle of the change of the output signal is called the transmission delay. Detailed description of the embodiments are described below.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a comparator according to the present utility model; VDD in the figure represents a power supply;

in order to solve the above technical problems, the present utility model provides a comparator, which includes a first input module 1, a first control module 2, a first acceleration module 3, a first output switch M33, a first adjustment switch M35, a second output switch M40, a second adjustment switch M38, a first voltage division module M36, a second voltage division module M37 and an inverter 4; the first input end of the first input module 1 is used as a first normal phase input end of the comparator, the second input end is used as a first reverse phase input end of the comparator, and the output end of the inverter 4 is used as an output end of the comparator;

The first end of the first output switch M33 is respectively connected with the first end of the first adjusting switch M35, the control end of the first output switch M33 is connected with the first end of the second output switch M40, the second end of the first adjusting switch M35 is grounded, the control end of the first adjusting switch M35 is connected with a first fixed bias voltage, the second end of the first adjusting switch M35 is connected with the first end of the first voltage dividing module M36, the first end of the second voltage dividing module M37 is respectively connected with the second end of the first voltage dividing module M36 and the input end of the inverter 4, the second end of the second voltage dividing module M37 is connected with the second end of the second adjusting switch M38, the control end of the second adjusting switch M38 is connected with a second fixed bias voltage, the first end of the second output switch M40 is connected with the first end and the control end of the second output switch M40, and the second end of the second output switch M40 is connected with a power supply; the first adjusting switch M35 and the second adjusting switch M38 are in a normally-on state;

the input end of the first control module 2 is connected with the output end of the first input module 1, the first output end is connected with the control end of the first output switch M33, the second output end is connected with the second end of the second adjusting switch M38, and the first control module is used for adjusting the voltage of the first output end to enable the first output switch M33 to be conducted and adjusting the current of the second output end to enable the second output switch M40 to be turned off based on the control of the first input module 1 when the first voltage of the first non-inverting input end of the comparator is larger than the second voltage of the first inverting input end of the comparator; when the first voltage is smaller than the second voltage, the voltage of the first output end is adjusted based on the control of the first input module 1 to enable the first output switch M33 to be turned off, and the current of the second output end is adjusted to enable the second output switch M40 to be turned on;

The first acceleration module 3 is connected to the first input module 1 and the first control module 2, and is configured to control the current at the second output terminal of the first control module 2 to decrease so as to increase the voltage at the control terminal of the second output switch M40 and control the voltage at the first output terminal of the first control module 2 to increase when the first voltage is less than the second voltage.

Specifically, the comparator provided by the utility model mainly comprises a comparator main body and a first acceleration module 3, wherein the comparator main body comprises an input stage, a load stage and an output stage, and can be regarded as a single-ended output amplifier, the input stage and the load stage play a role in amplifying the difference value of input signals, the amplified signals are input into the output stage, and the signals output by the output stage are finally inverted by an inverter 4 and then output as final output signals. Correspondingly, the first input module 1 corresponds to an input stage, the first control module 2 corresponds to a load stage, the first output switch M33, the first adjusting switch M35, the second output switch M40, the second adjusting switch M38, the first voltage dividing module M36 and the second voltage dividing module M37 together form an output stage.

When the first acceleration module 3 does not operate, when the first voltage is smaller than the second voltage, compared with the case that the first voltage is equal to the second voltage, the first voltage is reduced to cause the current of the second output end of the first control module 2 to be increased, the current of the second end and the first end of the second adjusting switch M38 connected with the first voltage is increased, the voltage of the first end of the second adjusting switch M38 is reduced because the control end of the second adjusting switch M38 is connected with the second fixed bias voltage, the voltage of the control end of the second adjusting switch M40 is reduced, the voltage of the control end of the second output switch M40 connected with the second adjusting switch M40 is reduced, the second output switch M40 is turned on, and meanwhile, the voltage of the control end of the first output switch M33 connected with the first adjusting switch M is reduced because the first voltage is reduced, the first output switch M33 is turned off, at this time, the second output switch M40 is turned on to be high, and after the inverter 4 is turned on, the output signal of the comparator is low; similarly, when the first voltage is greater than the second voltage, the first output switch M33 is turned on, the second output switch M40 is turned off, and the output signal of the comparator is at a high level.

Meanwhile, when the first voltage is smaller than the second voltage, the first acceleration module 3 starts to operate, the starting of the first acceleration module 3 reduces the current of the second output end of the first control module 2 and increases the voltage of the first output end of the first control module 2, so that the voltages of the control ends of the first output switch M33 and the second output switch M40 are higher than the voltage when the first acceleration module 3 does not operate, the on speed of the first output switch M33 is faster, and the off speed of the second output switch M40 is faster, so that when the first voltage is converted from smaller than the second voltage to larger than the second voltage, the first output switch M33 can be turned off faster, the second output switch M40 can be turned on faster, the speed of the comparator from low level to high level is accelerated, and the transmission delay is reduced.

It can be understood that the first acceleration module 3 is controlled to be turned on or off based on signals of two input terminals of the comparator, and the first acceleration module 3 is turned on only when the first voltage of the input signal of the comparator is smaller than the second voltage, so as to achieve the improvement of the speed of the comparator from the low level to the high level.

Specifically, the specific types and implementation manners of each module and each device in the comparator are not particularly limited herein, and may be adjusted according to actual application requirements and application environments. The first output switch M33 may be an NMOS (N-Metal-Oxide-Semiconductor) tube, the corresponding first adjustment switch M35 is a PMOS (P-Metal-Oxide-Semiconductor) tube, the corresponding second output switch M40 is a PMOS tube, the second adjustment switch M38 is an NMOS tube, the first voltage dividing module M36 and the second voltage dividing module M37 may select fixed resistors, or may use similar NMOS tubes and PMOS tubes as above; the specific structure of the inverter 4 may be selected from various ones, and is not particularly limited herein. It will be appreciated that the fixed bias voltage may be a fixed external power source, and the specific implementation may have various options, which are not particularly limited herein.

The utility model provides a comparator, which comprises a first input module 1, a first control module 2, a first acceleration module 3, a first output switch M33, a first adjusting switch M35, a second output switch M40, a second adjusting switch M38, a first voltage dividing module M36, a second voltage dividing module M37 and an inverter 4, wherein the first control module 2 adjusts output signals based on the control of the first input module 1, controls the on and off of the first output switch M33 through the voltage of a first output end, controls the on and off of the second output switch M40 through the current of a second output end, so that the comparator outputs different values, and when the first voltage of a first normal phase input end of the comparator is smaller than the second voltage of a first reverse phase input end of the comparator, the first acceleration module 3 further controls the current decrease at the second output end and the voltage increase at the first output end of the first control module 2, so that the voltages at the control ends of the first output switch M33 and the second output switch M40 are increased to increase the conversion speed of the first output switch M33 and the second output switch M40, the voltage conversion of the output signal of the comparator from the low level to the high level is faster, the delay is shorter, the signal conversion speed is greatly increased, the processing speed of the comparator is increased, the transmission delay is reduced, particularly, the transmission delay when the voltage difference of the input signal of the comparator is smaller is reduced, the increase of the processing speed of the whole comparator is realized under the condition of low power consumption, and the application range of the comparator is expanded.

On the basis of the above-described embodiments,

referring to fig. 2, fig. 2 is a schematic diagram of another comparator according to the present utility model; VB1, VB2, VB3, VB4, VB5 and VB6 in the figure represent fixed bias voltages and are fixed external power supplies; m34 and M39 are appropriately added voltage dividing modules as buffers between the output switch and the regulation switch;

as a preferred embodiment, the first acceleration module 3 comprises a start-up switch M6 and a common-gate amplifier; the first end of the starting switch M6 is connected with the first input module 1, and the second end of the starting switch M is connected with the first input module 1 and the first control module 2 respectively;

the input end of the common gate amplifier is respectively connected with the first input module 1 and the first control module 2, the output end of the common gate amplifier is connected with the control end of the starting switch M6, and the common gate amplifier is used for controlling the starting switch M6 to be conducted when the first voltage is smaller than the second voltage so as to control the current of the second output end of the first control module 2 to be reduced so as to enable the voltage of the control end of the second output switch M40 to be increased, and controlling the voltage of the first output end of the first control module 2 to be increased.

The present embodiment is a specific implementation of the first accelerating module 3, and is implemented by a start switch M6 and a common gate amplifier, where the control on whether the first accelerating module 3 operates is implemented by turning on and off the start switch M6, and the common gate amplifier is used to ensure the normal operating state of the first accelerating module 3 when the first voltage is less than the second voltage, and the non-operating state under other conditions.

Specifically, the start switch M6 may be an NMOS transistor, or may be implemented by using other switch types, and the type and specific implementation of the start switch M6 are not limited herein; there are also various options for the specific structure and implementation of the common gate amplifier, and the present application is not particularly limited herein.

The first acceleration module 3 is realized through the starting switch M6 and the common gate amplifier, the first acceleration module 3 is realized through the starting switch M6 and is not operated, the detection of two input voltages of the comparator is realized through the common gate amplifier, the circuit structure is simple, the implementation is easy, the application is convenient, the first acceleration module 3 can be effectively realized, the normal operation of the first acceleration module 3 is convenient, the improvement of the conversion speed of the subsequent comparator is ensured, and the transmission delay is reduced.

As a preferred embodiment, the common gate amplifier includes a first current source I1, a second current source I2, a first switch M4, a second switch M5, a third switch M2, a fourth switch M3, and a third voltage dividing module;

the first switch M4 is connected with the control end of the second switch M5 and is connected with a third fixed bias voltage, the third switch M2 is connected with the control end of the fourth switch M3, the first end of the first switch M4 is connected with the output end of the first current source I1, the first end of the second switch M5 is connected with the output end of the second current source I2, the input end of the first current source I1 and the input end of the second current source I2 are respectively connected with a power supply, the second end of the first switch M4 is respectively connected with the second end of the third switch M2 and the control end of the third switch M2, the second end of the second switch M5 is respectively connected with the second end of the fourth switch M3 and the control end of the starting switch M6, the first end of the third switch M2 is connected with the first end of the third voltage dividing module, the second end of the third voltage dividing module is respectively connected with the first input module 1 and the first control module 2, and the third end of the fourth switch M3 is respectively connected with the first input module 1 and the first control module 2.

The common gate amplifier is realized by four switches, and a third voltage dividing module is added at the same time, so that when the first voltage of the comparator is equal to the second voltage, the first acceleration module 3 is not put into operation. The first end of the third switch M2 is used as the first input end of the common-gate amplifier, the first end of the fourth switch M3 is used as the second input end of the common-gate amplifier, the second end of the second switch M5 is used as the output end of the common-gate amplifier, the first end of the third switch M2 is connected with the output signal of the corresponding first voltage in the first input module 1, the first end of the fourth switch M3 is connected with the output signal of the corresponding second voltage in the first input module 1, when the voltage of the first input end of the common-gate amplifier is smaller than the voltage of the second input end, the first voltage is smaller than the second voltage, and the first acceleration module 3 can be started; after the third voltage dividing module is added, when the first voltage is equal to the second voltage, the voltage of the first input end of the common gate amplifier is kept smaller than the voltage of the second input end, so that misoperation of the first acceleration module 3 can be prevented, and in fig. 2, the third voltage dividing module is realized by connecting R1 and M1 in series.

It is to be understood that the detection manner of the first voltage and the second voltage by the common gate amplifier may be other manners, which are not limited to the above implementation manner, and the application is not particularly limited herein. Specifically, the first switch M4 and the second switch M5 may be PMOS transistors, the third switch M2 and the fourth switch M3 may be NMOS transistors, the third voltage dividing module may be a fixed resistor and/or an NMOS transistor, and for each switching device, the types and specific implementation manners of the third voltage dividing module, the two current sources, and the like are not limited herein, and may be adjusted according to actual needs and actual applications.

The common-gate amplifier is realized through the four switches and the third voltage division module, so that the correct control of the common-gate amplifier to the starting switch M6 is effectively realized, the circuit structure is simple, the implementation is easy, the application is convenient, the common-gate amplifier can be effectively realized, the normal operation of the first acceleration module 3 is convenient, the improvement of the conversion speed of a subsequent comparator is ensured, and the transmission delay is reduced.

As a preferred embodiment, the first input module 1 comprises a third current source I6, a fifth switch M7 and a sixth switch M8;

the input end of the third current source I6 is connected with a power supply, the first ends of the fifth switch M7 and the sixth switch M8 are respectively connected with the output end of the third current source I6, the output end of the third current source I6 is also connected with the first acceleration module 3, the control end of the fifth switch M7 is used as a first normal phase input end of a comparator, the control end of the sixth switch M8 is used as a first reverse phase input end of the comparator, the second end of the fifth switch M7 and the second end of the sixth switch M8 are respectively connected with the input end of the first control module 2, and the second end of the fifth switch M7 and the second end of the sixth switch M8 are respectively connected with the first acceleration module 3.

The present embodiment is a specific implementation manner of the first input module 1, and the detection and conversion of the two input voltages of the comparator are implemented through the fifth switch M7 and the sixth switch M8, so that the voltage signals of the two inputs are converted into current signals, so that the corresponding control operations of the first control module 2 and the first acceleration module 3 can be performed subsequently.

Specifically, the fifth switch M7 and the sixth switch M8 may be PMOS transistors, and correspondingly, the second end of the fifth switch M7 may be connected to the first end of the fourth switch M3, the second end of the sixth switch M8 may be connected to the first end of the third switch M2, the first end of the start switch M6 may be connected to the output end of the third current source I6, and the second end may be connected to the second end of the fifth switch M7 or the second end of the sixth switch M8. The type and implementation of the fifth switch M7, the sixth switch M8, and the third current source I6 are not particularly limited herein.

The embodiment is a specific implementation manner of the first input module 1, has a simple circuit structure, is easy to implement, is convenient to apply, and can effectively implement the first input module 1 so as to facilitate the control work of the subsequent first control module 2 and the first acceleration module 3, ensure the improvement of the conversion speed of the subsequent comparator and reduce the transmission delay.

As a preferred embodiment, the first control module 2 comprises a fourth current source I7, a first load switch M17, a second load switch M18, a third load switch M19, a fourth load switch M20 and a fifth load switch M27;

the first end of the first load switch M17 is connected to the output end of the first input module 1 and the first end of the third load switch M19 respectively, the second end is grounded, the control end is connected to the control end of the second load switch M18 respectively, the second end of the third load switch M19 and the output end of the fourth current source I7 are connected, the input end of the fourth current source I7 is connected to the power supply, the first end of the second load switch M18 is connected to the output end of the first input module 1 respectively, the first end of the fourth load switch M20 and the first end of the fifth load switch M27 are connected to the ground, the control end of the third load switch M19 is connected to the control end of the fourth load switch M20 respectively, the control end of the fifth load switch M27 and the fourth fixed bias voltage are connected, the second end of the fourth load switch M20 is connected to the control end of the first output switch M33, and the second end of the fifth load switch M27 is connected to the second end of the second adjustment switch M38.

The embodiment is a specific implementation manner of the first control module 2, where the second end of the fourth load switch M20 is used as the first output end of the first control module 2, the second end of the fifth load switch M27 is used as the second output end of the first control module 2, and regulation and control on the second end of the fourth load switch M20 and the second end of the fifth load switch M27 are implemented based on control of the first input module 1, so as to implement control on the first output switch M33 and the second output switch M40.

Specifically, the first load switch M17, the second load switch M18, the third load switch M19, the fourth load switch M20, and the fifth load switch M27 may be NMOS transistors, and the types and specific implementation manners of the switching devices, the fourth current source I7, and the like are not particularly limited herein.

The embodiment is a specific implementation manner of the first control module 2, has a simple circuit structure, is easy to implement, is convenient to apply, and can effectively implement the first control module 2, so that the first control module 2 can implement subsequent control based on the first input module 1, thereby ensuring the improvement of the conversion speed of a subsequent comparator and reducing the transmission delay.

As a preferred embodiment, the inverter 4 includes a first inverting switch M42 and a second inverting switch M41;

The first end of the first inverting switch M42 is connected with a power supply, the second end is used as the output end of the comparator and is connected with the second end of the second inverting switch M41, the first end of the second inverting switch M41 is grounded, and the control end of the first inverting switch M42 is respectively connected with the control end of the second inverting switch M41 and the first end of the second voltage dividing module M37.

The embodiment is a specific implementation manner of the inverter 4, corresponding to the connection manner, the first inverting switch M42 may be a PMOS tube, the second inverting switch M41 may be an NMOS tube, the control end of the first inverting switch M42 and the control end of the second inverting switch M41 may be connected and then used as the input end of the inverter 4, when the first voltage is smaller than the second voltage, the second output switch M40 is turned on, the signal of the input end of the inverter 4 is at a high level, the voltages of the control end of the first inverting switch M42 and the control end of the second inverting switch M41 are higher, at this time, the second inverting switch M41 is turned on, and the output end of the comparator outputs a low level; when the first voltage is greater than the second voltage, the first output switch M33 is turned on, the signal at the input terminal of the inverter 4 is at a low level, the voltages at the control terminal of the first inverting switch M42 and the control terminal of the second inverting switch M41 are lower, at this time, the first inverting switch M42 is turned on, and the output terminal of the comparator outputs a high level.

The inverter 4 is realized through the simple two switches, the circuit structure is simple, the implementation is easy, the application is convenient, the inverter 4 can be effectively realized, the output signal of the comparator is ensured, the accuracy of the output result of the comparator is improved, and the reliability and the safety of the comparator are ensured.

As a preferred embodiment, the device further comprises a first control switch M25, a second control switch M26, a first quiescent current module and a second quiescent current module;

the first end of the first control switch M25 is respectively connected with the first output end of the first control module 2, the control end of the first output switch M33 and the second end of the second control switch M26, the second end is respectively connected with the control end of the second output switch M40 and the first end of the second control switch M26, the control end is connected with the first static current module, and the control end of the second control switch M26 is connected with the second static current module; the first end of the first static current module is connected with a power supply, the second end of the first static current module is grounded, and the first end of the second static current module is connected with the power supply;

the first quiescent current module is used for providing a bias quiescent current for the first control switch M25, and the second quiescent current module is used for providing a bias quiescent current for the second control switch M26.

Considering that the conduction condition and output capability of the first output switch M33 and the second output switch M40 are affected by the power supply voltage under different power supply voltages, the first control switch M25, the second control switch M26, the first quiescent current module and the second quiescent current module are additionally provided. The first control switch M25, the first static current module and the first output switch M33 are in one group, the second control switch M26, the second static current module and the second output switch M40 are in one group, and two groups of transconductance linear rings are respectively formed.

Specifically, the first control switch M25 may be an NMOS tube, the second control switch M26 may be a PMOS tube, and the types and specific implementation manners of the first control switch M25, the second control switch M26, the first quiescent current module and the second quiescent current module are not particularly limited herein. It is understood that the first control switch M25 and the second control switch M26 are in a normally-on state.

Considering that the conduction condition and output capability of the first output switch M33 and the second output switch M40 are affected by the power supply voltage under different power supply voltages, the first control switch M25, the second control switch M26, the first quiescent current module and the second quiescent current module are additionally provided. Through the structure of forming the transconductance linear loop, the static current output to the two output switches is ensured to be irrelevant to the power supply voltage, the output capacities of the first output switch M33 and the second output switch M40 are still ensured under the condition of different power supply voltages, the normal operation of the first output switch M33 and the second output switch M40 is further ensured, the accuracy of the output result of the comparator is ensured, and the reliability and the safety of the comparator are improved.

As a preferred embodiment, the first quiescent current module comprises a fifth current source I8, a first current switch M30 and a second current switch M29;

the first end of the fifth current source I8 is connected to the power supply, the second end is connected to the control end of the first control switch M25, the control end of the first current switch M30 is connected to the first end of the first current switch M30, the second end of the first current switch M30 is connected to the control end of the second current switch M29 and the first end of the second current switch M29, and the second end of the second current switch M29 is grounded.

The embodiment is a specific implementation manner of the first quiescent current module, the first quiescent current module is implemented through two current switches and a fifth current source I8, and provides a conducting quiescent current for the first control switch M25, and meanwhile, the first current switch M30 and the second current switch M29 ensure the implementation of a transconductance linear loop structure so as to ensure the normal operation of the first output switch M33.

Specifically, the first current switch M30 and the second current switch M29 may be NMOS transistors, and the types and specific implementations of the first current switch M30, the second current switch M29, and the fifth current source I8 are not particularly limited herein.

The embodiment is a specific implementation manner of the first quiescent current module, the first quiescent current module is realized through the two current switches and the fifth current source I8, the circuit structure is simple, the implementation is easy, the application is convenient, the first quiescent current module can be effectively realized, so that the normal operation of the first control switch M25 and the first output switch M33 is facilitated, the improvement of the conversion speed of a subsequent comparator is ensured, the transmission delay is reduced, the accuracy of the output result of the comparator is ensured, and the reliability and the safety of the comparator are improved.

As a preferred embodiment, the second quiescent current module comprises a sixth current source I9, a third current switch M31 and a fourth current switch M32;

the first end of the sixth current source I9 is grounded, the second end is connected to the control end of the second control switch M26, the control end of the third current switch M31 is connected to the first end of the third current switch M31, the second end of the third current switch M31 is connected to the control end of the fourth current switch M32 and the first end of the fourth current switch M32, and the second end of the fourth current switch M32 is connected to the power supply.

The embodiment is a specific implementation manner of the second quiescent current module, the second quiescent current module is implemented through two current switches and a sixth current source I9, the on quiescent current is provided for the second control switch M26, and meanwhile, the third current switch M31 and the fourth current switch M32 ensure the implementation of the transconductance linear loop structure so as to ensure the normal operation of the second output switch M40.

Specifically, the third current switch M31 and the fourth current switch M32 may be PMOS transistors, and the types and specific implementation manners of the third current switch M31, the fourth current switch M32, and the sixth current source I9 are not particularly limited herein.

The embodiment is a specific implementation manner of the second quiescent current module, the second quiescent current module is realized through the two current switches and the sixth current source I9, the circuit structure is simple, the implementation is easy, the application is convenient, the second quiescent current module can be effectively realized, so that the normal operation of the second control switch M26 and the second output switch M40 is facilitated, the improvement of the conversion speed of a subsequent comparator is ensured, the transmission delay is reduced, the accuracy of the output result of the comparator is ensured, and the reliability and the safety of the comparator are improved.

Taking the second quiescent current module as an example, please refer to fig. 3, fig. 3 is a schematic structural diagram of a transconductance linear loop provided by the present utility model;

in the figure, M32, M31, M26 and M40 form a group of transconductance linear loops, it can be understood that V _GS40 +V _GS26 ＝V _GS31 +V _GS32 V in the formula _GS40 Representing the difference between the gate voltage and the source voltage of M40, V _GS26 Representing the difference between the gate voltage and the source voltage of M26, V _GS31 Representing the difference between the gate voltage and the source voltage of M31, V _GS32 Representing the difference between the gate voltage and the source voltage of M32, if the width-to-length ratio of M31 and M32 is equal

In the formula, I _DS40 Represents the current through M40, W/L ₄₀ Represents the width-to-length ratio of M40, corresponding to I _DS26 Represents the current through M26, W/L ₂₆ Represents the aspect ratio of M26, I _DS32 Represents the current through M32, W/L ₃₂ Referring to the aspect ratio of M32, it can be seen from this equation that the current flowing through M40 is determined by the aspect ratios of M31, M32 and M26, the current flowing through M31, M32 and M26, and the aspect ratio of M40. Similarly, the current flowing through M33 is determined by the aspect ratios of M29, M30 and M25, the current flowing through M29, M30 and M25, and the aspect ratio of M33.

As a preferred embodiment, the system further comprises a second input module, a second control module and a second acceleration module; the first input end of the second input module is used as a second non-inverting input end of the comparator, and the second input end is used as a second inverting input end of the comparator;

the input end of the second control module is connected with the output end of the second input module, the first output end is connected with the control end of the second output switch M40, the second output end is connected with the second end of the first adjusting switch M35, and the second control module is used for adjusting the voltage of the first output end based on the control of the second input module to enable the second output switch M40 to be turned off and adjusting the current of the second output end to enable the first output switch M33 to be turned on when the third voltage of the second non-inverting input end of the comparator is larger than the fourth voltage of the second inverting input end of the comparator; when the third voltage is smaller than the fourth voltage, the voltage of the first output end is adjusted based on the control of the second input module to enable the second output switch M40 to be conducted, and the current of the second output end is adjusted to enable the first output switch M33 to be turned off;

The second acceleration module is connected with the second input module and the second control module respectively, and is used for controlling the current of the second output end of the second control module to be reduced so as to increase the voltage of the control end of the first output switch M33 and controlling the voltage of the first output end of the second control module to be increased when the third voltage is smaller than the fourth voltage.

It can be understood that the comparator provided by the utility model can be a rail-to-rail input comparator, and when the input common mode level is higher, the second input module and the corresponding second control module work; when the input common mode level is lower, the first input module 1 and the corresponding first control module 2 and the first acceleration module 3 work; for the second input module and the corresponding second control module, the working process of the second acceleration module is similar to that of the first input module 1 and the corresponding first control module 2, the specific content is not described in detail herein, and the type and specific implementation mode of the second acceleration module are not limited in particular herein.

The second input module and the corresponding second control module and the second acceleration module are added to embody that the comparator provided by the utility model can be used for the comparator with rail-to-rail input, when the intervals of input signals are different, different input modules and corresponding control modules are selected, the acceleration module works, the accuracy of the output result of the comparator is further ensured, and the reliability and the safety of the comparator are improved.

Taking fig. 2 as an example, when the input common mode level is higher, the NMOS transistors M15 and M16 operate, the PMOS transistors M7 and M8 are turned off, and similarly, when the input common mode level is lower, the opposite is true. When the acceleration module is not added, assuming that the initial state input level is lower and vinp=vinn, the PMOS transistors M7 and M8 are operated, the NMOS transistors M15 and M16 are turned off, and when VINP starts to decrease, the drain current I of M7 _D7 Increase the drain current I of M8 _D8 Reduced, M17 and M18 are a pair of current mirrors and are equal in size, drain current I of M17 _D17 Drain current I of =m18 _D18 At this time I _D17 Following I _D7 Is increased by an increase of (1), and I _D17 ＝I _D7 +I _D19 And drain current I of M19 _D19 Unchanged, at the same time I _D18 Following I _D17 Is increased by an increase of (1), and I _D18 ＝I _D8 +I _D20 +I _D27 And since the sum of the M20 width-to-length ratio and the M27 width-to-length ratio is equal to the M19 width-to-length ratio, the drain current I of M20 _D20 Drain current I with M27 _D27 The drain current I of the corresponding M38 increases _D38 Increase, while the voltage of the M38 gate is fixed by the external bias voltage, so the drain voltage V of M38 _D38 Following I _D38 The increase and decrease of the pull-up PMOS tube M40 are conducted; and due to I _D20 Increase the drain voltage V of M20 _D20 With this decrease, pull-down NMOS transistor M33 is turned off, and after inverting by inverter 4 consisting of M41 and M42, VOUT is output low. Similarly, when VINP >At VINN, VOUT output is high.

When the acceleration module is added, assuming that the initial state input level is lower and vinp=vinn, the PMOS transistors M7 and M8 are operated, the NMOS transistors M15 and M16 are turned off, and the drain voltages of M7 and M8 are equal, i.e., the voltage V at the point a _A Voltage V at point =b _B Due to voltage V at point C _C ＝V _A +V _R1 ，V _R1 Refers to the voltage across resistor R1, thus V _C >V _B M2, M3, M4 and M5 form a common gate amplifier, where the gate voltage of M6 is low and M6 is off. When VINP becomes large, I _D17 Reduced, by current mirror replication, I _D18 Similarly reduce I _D20 And I _D27 Reduced, so V _A Increase due to I _D19 Unchanged, V _B Unchanged, thus V _C Still greater than V _B M6 is still in the off state. When VINP decreases, I _D17 Increase, by current mirror replication, I _D18 Similarly increase, then the corresponding V _A Reduced at this time V _A <V _B In this state, with V _A Continuing to decrease, V will occur _C <V _B At this time, M6 is turned on, and since M6 is small in size relative to the input tube, the conduction is very rapid, the current flowing from I6 into the input tubes M7 and M8 also flows into M6, and since VINP<Since VINN is a current greater than M8 through M7, the current split from M7 is relatively large. Thus when the acceleration module is active, I is compared to no acceleration module _D17 Reduction, I _D18 Corresponding decrease due to I _D18 ＝I _D6 +I _D8 +I _D20 +I _D27 With I _D6 Is increased by (I) _D20 And I _D27 Also decrease, thus I _D38 Reduced drain voltage V of M38 _D38 Following I _D38 Is increased by a decrease in M4Gate voltage V of 0 _G40 With a consequent rise, assuming that the gate voltage of M40 is V without the acceleration module _G40’ V is then _G40 >V _G40’ . When the input signal is from VINP<VINN change to VINP>After VINN, the acceleration module does not work, and the current in the comparator of the acceleration module is equal to the current in the comparator of the acceleration module, and the grid voltage of M40 is V _G40” V is then _G40” >V _G40 >V _G40’ I.e. V _G40” -V _G40 <V _G40” -V _G40’ When the current is equal and the acceleration module is provided, the charging is faster and the M40 is turned off faster due to smaller pressure difference. At the same time due to I _D20 Current reduction, drain voltage V of M20 _D20 Increase and V _D20 ＝V _G33 Therefore V _G33 Increase compared with the grid voltage V of the un-accelerated module _G33’ ，V _G33 >V _G33’ Similarly, when the input signal is from VINP<VINN change to VINP>VINN, gate voltage V of M33 at this time _G33 Rise, V _G33” >V _G33 >V _G33’ I.e. V _G33” -V _G33 <V _G33” -V _G33’ Therefore, with the acceleration module, the pressure difference is smaller, and because the currents are equal, the M33 is opened faster. The acceleration module can be turned on faster when the M40 is turned off and faster when the M33 is turned on, so that the output signal VOUT of the comparator is switched from low level to high level faster, and the transmission delay is shorter.

Referring to fig. 4, fig. 4 is a timing diagram of a comparator provided by the present utility model under the condition that the comparator does not include an acceleration module and includes an acceleration module.

VIN in the figure represents the input signal, and the solid lines are the gate voltages V of M40 without the acceleration module _G40 Gate voltage V of M33 _G33 The output voltage VOUT, dashed line is M40 gate voltage V including the acceleration module _G40 M33 gate voltage V _G33 The voltage difference between the grid voltages of M40 and M33 comprising the acceleration module is smaller, and the currents are equal, so that the M40 is closed and the M33 is conducted at a higher speed, the output voltage is turned over faster, and the transmission delay is reduced.

It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present utility model. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the utility model. Thus, the present utility model is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. The comparator is characterized by comprising a first input module, a first control module, a first acceleration module, a first output switch, a first adjustment switch, a second output switch, a second adjustment switch, a first voltage division module, a second voltage division module and an inverter; the first input end of the first input module is used as a first non-inverting input end of the comparator, the second input end of the first input module is used as a first inverting input end of the comparator, and the output end of the inverter is used as an output end of the comparator;

the first end of the first output switch is respectively connected with the first end of the first adjusting switch, the control end of the first output switch is connected with the first end of the second output switch, the second end of the first output switch is grounded, the control end of the first adjusting switch is connected with a first fixed bias voltage, the second end of the first adjusting switch is connected with the first end of the first voltage dividing module, the first end of the second voltage dividing module is respectively connected with the second end of the first voltage dividing module and the input end of the inverter, the second end of the second voltage dividing module is connected with the second end of the second adjusting switch, the control end of the second adjusting switch is connected with a second fixed bias voltage, the first end of the second adjusting switch is connected with the first end and the control end of the second output switch, and the second end of the second output switch is connected with a power supply; the first adjusting switch and the second adjusting switch are in a normally-on state;

The input end of the first control module is connected with the output end of the first input module, the first output end of the first control module is connected with the control end of the first output switch, the second output end of the first control module is connected with the second end of the second regulation switch, and the first control module is used for regulating the voltage of the first output end to enable the first output switch to be conducted and regulating the current of the second output end to enable the second output switch to be turned off based on the control of the first input module when the first voltage of the first non-inverting input end of the comparator is larger than the second voltage of the first inverting input end of the comparator; when the first voltage is smaller than the second voltage, adjusting the voltage of a first output end based on the control of the first input module to enable the first output switch to be turned off, and adjusting the current of a second output end to enable the second output switch to be turned on;

the first acceleration module is respectively connected with the first input module and the first control module, and is used for controlling the current of the second output end of the first control module to be reduced so as to increase the voltage of the control end of the second output switch and controlling the voltage of the first output end of the first control module to be increased when the first voltage is smaller than the second voltage.

2. The comparator of claim 1, wherein the first acceleration module comprises a start-up switch and a common-gate amplifier; the first end of the starting switch is connected with the first input module, and the second end of the starting switch is connected with the first input module and the first control module respectively;

the input end of the common gate amplifier is respectively connected with the first input module and the first control module, the output end of the common gate amplifier is connected with the control end of the starting switch, and the common gate amplifier is used for controlling the starting switch to be conducted when the first voltage is smaller than the second voltage so as to control the current of the second output end of the first control module to be reduced so as to enable the voltage of the control end of the second output switch to be increased, and controlling the voltage of the first output end of the first control module to be increased.

3. The comparator of claim 2, wherein the common-gate amplifier comprises a first current source, a second current source, a first switch, a second switch, a third switch, a fourth switch, and a third voltage division module;

the first switch is connected with the control end of the second switch and is connected with a third fixed bias voltage, the third switch is connected with the control end of the fourth switch, the first end of the first switch is connected with the output end of the first current source, the first end of the second switch is connected with the output end of the second current source, the input end of the first current source and the input end of the second current source are respectively connected with a power supply, the second end of the first switch is respectively connected with the second end of the third switch and the control end of the third switch, the second end of the second switch is respectively connected with the second end of the fourth switch and the control end of the starting switch, the first end of the third switch is connected with the first end of the third voltage dividing module, the second end of the third voltage dividing module is respectively connected with the first input module and the first control module, the third end of the third voltage dividing module is respectively connected with the first end of the first voltage dividing module and the first end of the fourth switch is respectively connected with the first input module and the first end of the fourth voltage dividing module.

4. The comparator of claim 1, wherein the first input module comprises a third current source, a fifth switch and a sixth switch;

the input end of the third current source is connected with a power supply, the first ends of the fifth switch and the sixth switch are respectively connected with the output end of the third current source, the output end of the third current source is also connected with the first acceleration module, the control end of the fifth switch is used as a first normal phase input end of the comparator, the control end of the sixth switch is used as a first reverse phase input end of the comparator, the second ends of the fifth switch and the sixth switch are respectively connected with the input end of the first control module, and the second ends of the fifth switch and the sixth switch are respectively connected with the first acceleration module.

5. The comparator of claim 1, wherein the first control module comprises a fourth current source, a first load switch, a second load switch, a third load switch, a fourth load switch, and a fifth load switch;

the first end of the first load switch is respectively connected with the output end of the first input module and the first end of the third load switch, the second end of the first load switch is grounded, the control end of the first load switch is respectively connected with the control end of the fourth load switch, the second end of the third load switch is connected with the output end of the fourth current source, the input end of the fourth current source is connected with a power supply, the first end of the second load switch is respectively connected with the output end of the first input module, the first end of the fourth load switch is connected with the first end of the fifth load switch, the second end of the fourth load switch is grounded, the control end of the third load switch is respectively connected with the control end of the fourth load switch, the control end of the fifth load switch is connected with the fourth fixed bias voltage, the second end of the fourth load switch is connected with the control end of the first output switch, and the second end of the fifth load switch is connected with the second end of the second adjustment switch.

6. The comparator of claim 1, wherein the inverter comprises a first inverting switch and a second inverting switch;

the first end of the first inverting switch is connected with a power supply, the second end of the first inverting switch is used as the output end of the comparator and is connected with the second end of the second inverting switch, the first end of the second inverting switch is grounded, and the control end of the first inverting switch is respectively connected with the control end of the second inverting switch and the first end of the second voltage dividing module.

7. The comparator of claim 1, further comprising a first control switch, a second control switch, a first quiescent current module and a second quiescent current module;

the first end of the first control switch is respectively connected with the first output end of the first control module, the control end of the first output switch is connected with the second end of the second control switch, the second end of the first control switch is respectively connected with the control end of the second output switch and the first end of the second control switch, the control end of the first control switch is connected with the first static current module, and the control end of the second control switch is connected with the second static current module; the first end of the first static current module is connected with the power supply, the second end of the first static current module is grounded, the first end of the second static current module is connected with the power supply, and the second end of the second static current module is grounded;

The first quiescent current module is used for providing a bias quiescent current for the first control switch, and the second quiescent current module is used for providing a bias quiescent current for the second control switch.

8. The comparator of claim 7, wherein the first quiescent current module comprises a fifth current source, a first current switch and a second current switch;

the first end of the fifth current source is connected with the power supply, the second end of the fifth current source is respectively connected with the control end of the first control switch, the control end of the first current switch is connected with the first end of the first current switch, the second end of the first current switch is respectively connected with the control end of the second current switch and the first end of the second current switch, and the second end of the second current switch is grounded.

9. The comparator of claim 7, wherein the second quiescent current module comprises a sixth current source, a third current switch and a fourth current switch;

the first end of the sixth current source is grounded, the second end of the sixth current source is respectively connected with the control end of the second control switch, the control end of the third current switch is connected with the first end of the third current switch, the second end of the third current switch is respectively connected with the control end of the fourth current switch and the first end of the fourth current switch, and the second end of the fourth current switch is connected with the power supply.

10. The comparator according to any one of claims 1 to 9, further comprising a second input module, a second control module and a second acceleration module; the first input end of the second input module is used as a second non-inverting input end of the comparator, and the second input end of the second input module is used as a second inverting input end of the comparator;

the input end of the second control module is connected with the output end of the second input module, the first output end of the second control module is connected with the control end of the second output switch, the second output end of the second control module is connected with the second end of the first adjusting switch, and the second control module is used for adjusting the voltage of the first output end based on the control of the second input module to enable the second output switch to be turned off and adjusting the current of the second output end to enable the first output switch to be turned on when the third voltage of the second non-inverting input end of the comparator is larger than the fourth voltage of the second inverting input end of the comparator; when the third voltage is smaller than the fourth voltage, adjusting the voltage of the first output end based on the control of the second input module to enable the second output switch to be on, and adjusting the current of the second output end to enable the first output switch to be off;

The second acceleration module is respectively connected with the second input module and the second control module, and is used for controlling the current of the second output end of the second control module to be reduced so as to increase the voltage of the control end of the first output switch and controlling the voltage of the first output end of the second control module to be increased when the third voltage is smaller than the fourth voltage.

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