CN219040074U - Integrated chip and data processing circuit chip - Google Patents

Abstract

An integrated chip and a data processing circuit chip, the integrated chip comprising: a memory circuit chip and a data processing circuit chip attached to each other, wherein: the memory circuit chip comprises at least one memory circuit; the data processing circuit chip comprises at least one memory access circuit, wherein the memory access circuit comprises a read-write control sub-circuit and a time sequence correction sub-circuit, and the read-write control sub-circuit and the time sequence correction sub-circuit are electrically connected through a signal line; the memory circuit and the timing correction sub-circuit are electrically connected through bonding contacts. The integrated chip of the embodiment of the disclosure can fully utilize the storage space of the storage circuit chip, and can enable the storage circuit chip and the data processing circuit chip to communicate with each other more quickly while avoiding signal mutual interference between the storage circuit chip and the data processing circuit chip.

Description

Integrated chip and data processing circuit chip

Technical Field

Embodiments of the present disclosure relate to the field of chip design technologies, but are not limited to, and in particular, to an integrated chip and a data processing circuit chip.

Background

In the prior art, the data processing circuit and the memory are designed on separate chips, but when the data processing circuit and the memory communicate with each other, the memory access process is slow, which results in an increase in redundant resources. The data bit width of a chip for calculating hash operation is usually fixed, and the adoption of a general memory access structure can cause the problems of increased redundant resources, low efficiency of accessing a memory chip, complex structure, easy occurrence of design defects and the like, so that the memory access structure is required to be optimized.

Disclosure of Invention

The embodiment of the disclosure provides an integrated chip, comprising: a memory circuit chip and a data processing circuit chip attached to each other, wherein: the memory circuit chip comprises at least one memory circuit; the data processing circuit chip comprises at least one memory access circuit, wherein the memory access circuit comprises a read-write control sub-circuit and a time sequence correction sub-circuit, and the read-write control sub-circuit and the time sequence correction sub-circuit are electrically connected through a signal line; the memory circuit and the timing correction sub-circuit are electrically connected through bonding contacts.

The embodiment of the disclosure also provides a data processing circuit chip, which comprises at least one memory access circuit, wherein the memory access circuit comprises a read-write control sub-circuit and a time sequence correction sub-circuit, and the read-write control sub-circuit and the time sequence correction sub-circuit are electrically connected through a signal line.

According to the integrated chip and the data processing circuit chip, the time sequence correction subcircuit is arranged in the memory access circuit, and the time sequence correction subcircuit and the memory access circuit are integrated in one chip (namely the data processing circuit chip), so that more memory circuits can be contained in the memory circuit chip, more data storage capacity is provided, meanwhile, the memory circuits and the time sequence correction subcircuit are electrically connected through the metal contacts, and meanwhile, the mutual signal interference between the memory circuit chip and the data processing circuit chip is avoided, and meanwhile, the memory circuit chip and the data processing circuit chip can be communicated with each other more quickly.

Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the disclosure. Other advantages of the present disclosure may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The accompanying drawings are included to provide an understanding of the technical aspects of the present disclosure, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present disclosure and together with the embodiments of the disclosure, not to limit the technical aspects of the present disclosure.

Fig. 1 is a schematic structural diagram of an integrated chip according to an exemplary embodiment of the present disclosure;

FIG. 2 is a schematic diagram of another integrated chip according to an exemplary embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a further integrated chip according to an exemplary embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a data processing circuit chip according to an exemplary embodiment of the present disclosure;

fig. 5 is a schematic diagram of a structure of another data processing circuit chip according to an exemplary embodiment of the present disclosure.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail hereinafter with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be arbitrarily combined with each other.

Unless otherwise defined, technical or scientific terms used in the disclosure of the embodiments of the present disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure pertains. The terms "first," "second," and the like, as used in embodiments of the present disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, is intended to mean that elements or items preceding the word encompass the elements or items listed thereafter and equivalents thereof without precluding other elements or items.

As shown in fig. 1, an embodiment of the present disclosure provides an integrated chip, including: a memory circuit chip 2 and a data processing circuit chip 1 attached to each other, wherein:

the memory circuit chip 2 includes at least one memory circuit 201;

the data processing circuit chip 1 includes at least one memory access circuit 10, the memory access circuit 10 including a read-write control sub-circuit (not shown in the figure) and at least one timing correction sub-circuit 102, the read-write control sub-circuit and the timing correction sub-circuit 102 being electrically connected by a signal line (not shown in the figure);

the memory circuit 201 and the timing correction sub-circuit 102 are electrically connected through the bonding contact 3.

The integrated chip of the embodiment of the disclosure integrates the time sequence correction sub-circuit 102 and the memory access circuit 10 in the data processing circuit chip 1 by arranging the time sequence correction sub-circuit 102 in the memory access circuit 10, so that more memory circuits can be accommodated in the memory circuit chip 2, thereby providing more data storage capacity, and simultaneously, the memory circuit 201 and the time sequence correction sub-circuit 102 are electrically connected through the bonding contact 3, thereby avoiding signal mutual interference between the memory circuit chip 2 and the data processing circuit chip 1, and realizing mutual communication between the memory circuit chip 2 and the data processing circuit chip 1.

In preparing the integrated chip of the embodiment of the present disclosure, the memory circuit chip 2 and the data processing circuit chip 1 may be prepared separately first, where the memory circuit chip 2 includes a first substrate, a first circuit layer disposed on the first substrate, and a first insulating layer disposed on the first circuit layer, the first circuit layer includes a memory circuit and a first bonding contact, and the memory circuit and the first bonding contact are electrically connected; the data processing circuit chip 1 comprises a second substrate, a second circuit layer arranged on the second substrate and a second insulating layer arranged on the second circuit layer, wherein the second circuit layer comprises a memory access circuit, the memory access circuit comprises a read-write control sub-circuit and a time sequence correction sub-circuit, the second insulating layer is provided with a plurality of second through holes, metal is deposited in the second through holes to form second Bonding contacts, the time sequence correction sub-circuit is electrically connected with the second Bonding contacts, and a Hybrid Bonding structure is formed through the first Bonding contacts and the second Bonding contacts.

In some exemplary embodiments, as shown in fig. 2, the data processing circuit chip 1 further includes a read data path 12 and a write data path 13, and the read/write control sub-circuit 101 includes a data processing sub-circuit 1011, a data receiving sub-circuit 1012, a read request processing sub-circuit 1013, a write request processing sub-circuit 1014, and a memory access timing control sub-circuit 1015, wherein:

the data processing sub-circuit 1011 is electrically connected to the data receiving sub-circuit 1012 for receiving data from the data receiving sub-circuit 1012 and returning to the read data path 12;

the read request processing sub-circuit 1013 is electrically connected to the memory access timing control sub-circuit 1015, and is configured to receive a read request including a first address, resolve the first address into a plurality of second addresses, and send a read instruction including the second addresses to the memory access timing control sub-circuit 1015;

the write request processing sub-circuit 1014 is electrically connected to the memory access timing control sub-circuit 1015 and the timing correction sub-circuit 102, respectively, and is configured to receive a write request including a third address and first data, resolve the third address into a plurality of fourth addresses, send a write instruction including the fourth address to the memory access timing control sub-circuit 1015, and send the first data to the timing correction sub-circuit 102;

the memory access timing control sub-circuit 1015 is electrically connected to the read request processing sub-circuit 1013, the write request processing sub-circuit 1014, and the timing correction sub-circuit 102, and is configured to receive the read request of the read request processing sub-circuit 1013 and the write request of the write request processing sub-circuit 1014, generate a corresponding timing according to the read request and the write request, and transmit the generated timing to the timing correction sub-circuit 102;

the timing correction sub-circuit 102 is electrically connected to the data receiving sub-circuit 1012, the memory access timing control sub-circuit 1015, and the write request processing sub-circuit 1014, respectively, and is configured to receive and calibrate the timing transmitted by the memory access timing control sub-circuit 1015, perform read/write access to the memory circuit 201 according to the calibrated timing, and send the read data to the data receiving sub-circuit 1012.

In the embodiment of the present disclosure, the data processing circuit chip 1 includes a read request processing sub-circuit 1013, a write request processing sub-circuit 1014, a memory access timing control sub-circuit 1015, a timing correction sub-circuit 102, a data processing sub-circuit 1011, a data receiving sub-circuit 1012, a read data path 12, and a write data path 13.

The read request processing sub-circuit 1013 receives a request including an address corresponding to 1024 bits of data, and parses the address into read requests for (1024/n) addresses, and issues a read instruction to the memory access timing control sub-circuit 1015. A first-in first-out (First In First Out, FIFO) memory or register may be included within the read request processing subcircuit 1013 for caching additional requests to improve the interaction efficiency of the datapath and memory access circuitry.

The write request processing sub-circuit 1014 receives a request containing an address and 512bit data, the address is parsed into write requests for (512/n) addresses, and a write instruction is issued to the memory access timing control sub-circuit 1015. FIFO or registers may be added as needed in the write request processing sub-circuit 1014 for caching the write request, and in some ethernet power chip application scenarios, the write operation has no great requirement on efficiency, so the registers may not be needed to cache the data of the write request.

The memory access timing control sub-circuit 1015 receives the address request from the write request processing sub-circuit 1014 or the read request processing sub-circuit 1013, generates a corresponding timing, and transmits the corresponding timing to the timing correction sub-circuit 102.

The timing correction sub-circuit 102 is used to calibrate the timing of the received signal to ensure efficient transmission of data. In some technologies, the timing correction subcircuit 102 is packaged in a memory circuit chip, occupies a memory area of the memory circuit chip, and reduces a memory space of the memory circuit chip, and the embodiments of the present disclosure use a 3D bonding technology to package the timing correction subcircuit 102 in a data processing circuit chip, so that not only can the timing calibration of access data be satisfied, but also the memory space of the memory circuit chip can be fully expanded.

The data processing sub-circuit 1011 receives the Nbit data from the data receiving sub-circuit 1012 and concatenates it into 1024 bits of data for transfer to the read data path 12.

The data path includes a write data path 13 and a read data path 12, and the data path reads and writes data from and to the memory circuit 201 through the memory access circuit 10.

In some exemplary embodiments, the data processing circuit chip 1 further includes a calculation circuit 11, the calculation circuit 11 being electrically connected to the read data path 12 and the write data path 13, respectively.

In some usage scenarios, the size of one unit operand of the computing unit includes 512 bits and 1024 bits, where 512 bits is the data size that needs to be stored in the storage unit and 1024 bits is the data size that needs to be read out from the storage unit; the common memory cells do not use larger data bit width due to the manufacturing difficulty and other problems, namely, the bit width is smaller than 512 bits.

In some exemplary embodiments, the bit width of the memory circuit 201 is N bits, N being less than 512, and exemplary, n=64 or 128.

In some exemplary embodiments, the data corresponding to the first address is 1024 bits, resolving the first address into x second addresses, x=1024/N.

In some exemplary embodiments, the first data is 512 bits, the third address is resolved into y fourth addresses, y=512/N.

In some exemplary embodiments, as shown in fig. 3, the data processing circuit chip 1 further includes a self-test sub-circuit 14, and the read-write control sub-circuit 101 further includes a channel selection sub-circuit 1016, wherein:

the channel selection sub-circuit 1016 includes a plurality of first input terminals (not shown) and a plurality of first output terminals (not shown), and further includes a second input terminal (not shown) and a second output terminal (not shown) for transmitting data from at least one first input terminal to at least one first output terminal and transmitting data from the second input terminal to the second output terminal;

the read data path 12, the write data path 13, and the self-test sub-circuit 14 are electrically connected to a first input terminal, the read request processing sub-circuit 1013 and the write request processing sub-circuit 1014 are electrically connected to a first output terminal, the data processing sub-circuit 1011 is electrically connected to a second input terminal, and the read data path 12 is electrically connected to a second output terminal.

In this embodiment, the data processing circuit chip 1 further includes a channel selection sub-circuit 1016 and a self-test sub-circuit 14.

Wherein the channel select sub-circuit 1016 is used for path switching between the read/write data paths 12/13 and the self-test sub-circuit 14. The memory access circuit 10 generally performs reading and writing of data based on reading and writing operations of a data path. When the chip is streamed and the yield test is required for the memory access circuit 10 or the memory circuit 201, the circuit can be switched to the self-test sub-circuit 14 to perform self-test for the memory access circuit 10 or the memory circuit 201.

The self-test sub-circuit 14 may generate a read request in 1024 bits and a write request in 512 bits of any address and any data according to the configuration, and may automatically change the number of times the address and data are tested for the configuration. For detecting the yield of the memory access circuit 10 or the memory circuit 201 after chip streaming.

In some example embodiments, the memory circuit 201 may be a dynamic random access memory (Dynamic Random Access Memory, DRAM) memory circuit.

The integrated chip of the embodiment of the disclosure, the memory access circuit 10 is not required to be compatible with other data bit widths, and the complexity of control logic is reduced; because the data format is fixed, excessive cache logic is not needed in the process of bit width matching, the number of needed resources is greatly reduced, and the logic and the detection flow are simplified because the data format is fixed in the self-checking sub-circuit.

According to the integrated chip disclosed by the embodiment of the disclosure, the data processing circuit chip and the memory circuit chip are bonded face to face in a 3D bonding mode, the two chips are isolated by using the insulating layer, signal mutual interference is avoided, and communication between the two chips can be completed through HB (Hybrid Bonding) metal contacts, so that the memory circuit chip and the data processing circuit chip can be communicated with each other more quickly. Furthermore, we integrate the timing correction subcircuit also into the data processing circuit chip so that more memory circuits can be accommodated in the memory circuit chip, providing more data storage capability.

As shown in fig. 4 or 5, the embodiment of the present disclosure further provides a data processing circuit chip 1, including at least one memory access circuit 10, the memory access circuit 10 including a read-write control sub-circuit 101 and a timing correction sub-circuit 102, the read-write control sub-circuit 101 and the timing correction sub-circuit 102 being electrically connected by a signal line.

In some exemplary embodiments, as shown in fig. 4, the data processing circuit chip 1 further includes a read data path 12 and a write data path 13, and the read/write control sub-circuit 101 includes a data processing sub-circuit 1011, a data receiving sub-circuit 1012, a read request processing sub-circuit 1013, a write request processing sub-circuit 1014, and a memory access timing control sub-circuit 1015, wherein:

the data processing sub-circuit 1011 is electrically connected to the data receiving sub-circuit 1012 for receiving data from the data receiving sub-circuit 1012 and returning to the read data path 12;

the read request processing sub-circuit 1013 is electrically connected to the memory access timing control sub-circuit 1015, and is configured to receive a read request including a first address, resolve the first address into a plurality of second addresses, and send a read instruction including the second addresses to the memory access timing control sub-circuit 1015;

the write request processing sub-circuit 1014 is electrically connected to the memory access timing control sub-circuit 1015 and the timing correction sub-circuit 102, respectively, and is configured to receive a write request including a third address and first data, resolve the third address into a plurality of fourth addresses, send a write instruction including the fourth address to the memory access timing control sub-circuit 1015, and send the first data to the timing correction sub-circuit 102;

the memory access timing control sub-circuit 1015 is electrically connected to the read request processing sub-circuit 1013, the write request processing sub-circuit 1014, and the timing correction sub-circuit 102, and is configured to receive the read request of the read request processing sub-circuit 1013 and the write request of the write request processing sub-circuit 1014, generate a corresponding timing according to the read request and the write request, and transmit the generated timing to the timing correction sub-circuit 102;

the timing correction sub-circuit 102 is electrically connected to the data receiving sub-circuit 1012, the memory access timing control sub-circuit 1015, and the write request processing sub-circuit 1014, respectively, and is configured to receive and calibrate the timing transmitted by the memory access timing control sub-circuit 1015, perform read/write access to an external memory circuit according to the calibrated timing, and send the read data to the data receiving sub-circuit 1012.

In some exemplary embodiments, the data processing circuit chip 1 further includes a calculation circuit 11, the calculation circuit 11 being electrically connected to the read data path 12 and the write data path 13, respectively.

In some usage scenarios, the size of one unit operand of the computing unit includes 512 bits and 1024 bits, where 512 bits is the data size that needs to be stored in the storage unit and 1024 bits is the data size that needs to be read out from the storage unit; the common memory cells do not use larger data bit width due to the manufacturing difficulty and other problems, namely, the bit width is smaller than 512 bits.

In some exemplary embodiments, the data corresponding to the first address is 1024 bits, the first address is resolved into x second addresses, x=1024/N, N is the bit width of the memory circuit, N is less than 512, and n=64 or 128, for example.

In some exemplary embodiments, the first data is 512 bits, the third address is resolved into y fourth addresses, y=512/N, N is the bit width of the memory circuit, N is less than 512, and exemplary, n=64 or 128.

In some exemplary embodiments, as shown in fig. 5, the data processing circuit chip 1 further includes a self-test sub-circuit 14, and the read-write control sub-circuit 101 further includes a channel selection sub-circuit 1016, wherein:

the channel selection sub-circuit 1016 includes a plurality of first input terminals (not shown) and a plurality of first output terminals (not shown), and further includes a second input terminal (not shown) and a second output terminal (not shown) for transmitting data from at least one first input terminal to at least one first output terminal and transmitting data from the second input terminal to the second output terminal;

the read data path 12, the write data path 13, and the self-test sub-circuit 14 are electrically connected to a first input terminal, the read request processing sub-circuit 1013 and the write request processing sub-circuit 1014 are electrically connected to a first output terminal, the data processing sub-circuit 1011 is electrically connected to a second input terminal, and the read data path 12 is electrically connected to a second output terminal.

The data processing circuit chip of the embodiment of the disclosure, the memory access circuit 10 is not required to be compatible with other data bit widths, and the complexity of control logic is reduced; because the data format is fixed, excessive cache logic is not needed in the process of bit width matching, the number of needed resources is greatly reduced, and the logic and the detection flow are simplified because the data format is fixed in the self-checking sub-circuit.

In describing embodiments of the present disclosure, it should be noted that, unless explicitly stated and limited otherwise, the terms "mounted," "connected," and "connected" should be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The meaning of the above terms in the present disclosure can be understood by one of ordinary skill in the art as appropriate.

Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit.

While the embodiments disclosed in the present disclosure are described above, the embodiments are only employed for facilitating understanding of the present disclosure, and are not intended to limit the present disclosure. Any person skilled in the art to which this disclosure pertains will appreciate that alterations and changes in form and detail can be made without departing from the spirit and scope of the disclosure, but the scope of the disclosure is still subject to the scope of the appended claims.

Claims (10)

1. An integrated chip, comprising: a memory circuit chip and a data processing circuit chip attached to each other, wherein:

the memory circuit chip comprises at least one memory circuit;

the data processing circuit chip comprises at least one memory access circuit, wherein the memory access circuit comprises a read-write control sub-circuit and a time sequence correction sub-circuit, and the read-write control sub-circuit and the time sequence correction sub-circuit are electrically connected through a signal line;

the memory circuit and the timing correction sub-circuit are electrically connected through bonding contacts.

2. The integrated chip of claim 1, wherein the data processing circuit chip further comprises a read data path and a write data path, the read-write control sub-circuit comprising a data processing sub-circuit, a data receiving sub-circuit, a read request processing sub-circuit, a write request processing sub-circuit, and a memory access timing control sub-circuit, wherein:

the data processing sub-circuit is electrically connected with the data receiving sub-circuit and is used for receiving the data of the data receiving sub-circuit and returning the data to the read data path;

the read request processing sub-circuit is electrically connected with the memory access time sequence control sub-circuit and is used for receiving a read request containing a first address, resolving the first address into a plurality of second addresses and sending a read instruction containing the second addresses to the memory access time sequence control sub-circuit;

the write request processing sub-circuit is electrically connected with the memory access time sequence control sub-circuit and the time sequence correction sub-circuit respectively and is used for receiving a write request containing a third address and first data, resolving the third address into a plurality of fourth addresses, sending the write instruction containing the fourth address to the memory access time sequence control sub-circuit and sending the first data to the time sequence correction sub-circuit;

the memory access time sequence control sub-circuit is respectively and electrically connected with the read request processing sub-circuit, the write request processing sub-circuit and the time sequence correction sub-circuit and is used for receiving the read request of the read request processing sub-circuit and the write request of the write request processing sub-circuit, generating corresponding time sequences according to the read request and the write request and transmitting the generated time sequences to the time sequence correction sub-circuit;

the time sequence correction sub-circuit is respectively and electrically connected with the data receiving sub-circuit, the memory access time sequence control sub-circuit and the write request processing sub-circuit, and is used for receiving and calibrating the time sequence transmitted by the memory access time sequence control sub-circuit, performing read-write access on the memory circuit according to the calibrated time sequence, and sending the read data to the data receiving sub-circuit.

3. The integrated chip of claim 2, wherein the bit width of the memory circuit is N bits, the data corresponding to the first address is 1024 bits, N is less than 1024, and the first address is resolved into x second addresses, x=1024/N.

4. The integrated chip of claim 2, wherein the bit width of the memory circuit is N bits, the first data is 512 bits, N is less than 512, the third address is resolved into y fourth addresses, and y = 512/N.

5. The integrated chip of claim 3 or 4, wherein N = 64 or 128.

6. The integrated chip of claim 2, wherein the data processing circuit chip further comprises a computation circuit electrically connected to the read data path and the write data path, respectively.

7. The integrated chip of claim 2, wherein the data processing circuit chip further comprises a self-test sub-circuit, the read-write control sub-circuit further comprising a channel selection sub-circuit, wherein:

the channel selection sub-circuit comprises a plurality of first input ends and a plurality of first output ends, and also comprises a second input end and a second output end, wherein the channel selection sub-circuit is used for transmitting data of at least one first input end to at least one first output end and transmitting data of the second input end to the second output end;

the read data path, the write data path and the self-checking sub-circuit are respectively and electrically connected with one first input end, the read request processing sub-circuit and the write request processing sub-circuit are respectively and electrically connected with one first output end, the data processing sub-circuit is electrically connected with the second input end, and the read data path is electrically connected with the second output end.

8. A data processing circuit chip comprising at least one memory access circuit, said memory access circuit comprising a read-write control sub-circuit and a timing correction sub-circuit, said read-write control sub-circuit and said timing correction sub-circuit being electrically connected by a signal line.

9. The data processing circuit chip of claim 8, wherein the data processing circuit chip further comprises a read data path and a write data path, the read-write control sub-circuit comprising a data processing sub-circuit, a data receiving sub-circuit, a read request processing sub-circuit, a write request processing sub-circuit, and a memory access timing control sub-circuit, wherein:

the data processing sub-circuit is electrically connected with the data receiving sub-circuit and is used for receiving the data of the data receiving sub-circuit and returning the data to the read data path;

the read request processing sub-circuit is electrically connected with the memory access time sequence control sub-circuit and is used for receiving a read request containing a first address, resolving the first address into a plurality of second addresses and sending a read instruction containing the second addresses to the memory access time sequence control sub-circuit;

the write request processing sub-circuit is electrically connected with the memory access time sequence control sub-circuit and the time sequence correction sub-circuit respectively and is used for receiving a write request containing a third address and first data, resolving the third address into a plurality of fourth addresses, sending the write instruction containing the fourth address to the memory access time sequence control sub-circuit and sending the first data to the time sequence correction sub-circuit;

the memory access time sequence control sub-circuit is respectively and electrically connected with the read request processing sub-circuit, the write request processing sub-circuit and the time sequence correction sub-circuit and is used for receiving the read request of the read request processing sub-circuit and the write request of the write request processing sub-circuit, generating corresponding time sequences according to the read request and the write request and transmitting the generated time sequences to the time sequence correction sub-circuit;

the time sequence correction sub-circuit is respectively and electrically connected with the data receiving sub-circuit, the memory access time sequence control sub-circuit and the write request processing sub-circuit, and is used for receiving and calibrating the time sequence transmitted by the memory access time sequence control sub-circuit, performing read-write access on the memory circuit according to the calibrated time sequence, and sending the read data to the data receiving sub-circuit.

10. The data processing circuit chip of claim 9, further comprising a computation circuit electrically connected to the read data path and the write data path, respectively.

Images