CN219017650U

CN219017650U - Double-sided bonding stacking and sealing structure of substrate

Info

Publication number: CN219017650U
Application number: CN202223290287.5U
Authority: CN
Inventors: 刘燚
Original assignee: National Center for Advanced Packaging Co Ltd
Current assignee: National Center for Advanced Packaging Co Ltd
Priority date: 2022-12-08
Filing date: 2022-12-08
Publication date: 2023-05-12
Anticipated expiration: 2032-12-08

Abstract

The utility model relates to a double-sided bonding stacking and sealing structure of a substrate, which comprises the following steps: the middle part of the substrate is provided with a slotted hole, the front surface of the substrate is provided with a first bonding finger, and the back surface of the substrate is provided with a second bonding finger and a bonding pad; the first chip is inverted on the front surface of the substrate, and pins of the second chip are positioned in the slotted holes; a second chip disposed on the first chip and electrically connected to the substrate; and a third chip disposed on the back surface of the substrate and electrically connected to the substrate and the first chip. The stacked structure adopts the substrate with the slot holes, chips are stacked on the front side and the back side of the substrate, and the chips on the front side and the back side of the substrate are interconnected by utilizing the leads penetrating through the slot holes, the chips in the stacked structure are not crossed with the leads between the chips and the substrate, the risk of line short circuit and line collapse is avoided during packaging, the process difficulty is reduced, and compared with a tiled chip mounting mode, the size of the package size of the stacked structure is reduced.

Description

Double-sided bonding stacking and sealing structure of substrate

Technical Field

The utility model relates to the technical field of semiconductor packaging, in particular to a double-sided bonding stacking and sealing structure of a substrate.

Background

The conventional packaged chip stacking process generally uses a large chip on a lower side and a small chip on an upper side, and connects pins of the chip to a substrate through a bonding process. Fig. 1 shows a schematic cross-sectional view of a chip stack package structure according to the prior art. Because the two chips are wire-bonded and crossed, the risk of wire-touching short circuit and wire collapse exists in encapsulation. When encountering large chips with irregular pin distribution, a tiled chip loading mode is needed. Fig. 2A shows a schematic cross-sectional view of a prior art chip-tiling package. Fig. 2B and 2C show schematic top views of chips in a prior art chip-tiling package. The packaging size is increased by the flat-laying chip loading mode, and the system integration level is reduced.

Disclosure of Invention

In order to solve at least some of the above problems in the prior art, the present utility model provides a double-sided bonding lamination structure for a substrate, comprising:

the middle part of the substrate is provided with a slotted hole, the front surface of the substrate is provided with a first bonding finger, and the back surface of the substrate is provided with a second bonding finger and a bonding pad;

the first chip is inverted on the front surface of the substrate, and pins of the first chip are positioned in the slotted holes;

a second chip disposed on the first chip and electrically connected to the substrate; and

and a third chip disposed on the back surface of the substrate and electrically connected to the substrate and the first chip.

Further, the method further comprises the following steps:

a metal post connected to the pad;

the adapter plate is connected with the substrate through the metal column; and

and the solder balls are arranged on the back surface of the adapter plate.

Further, pins of the second chip are connected with the first bonding fingers of the substrate through leads; and

the back of the second chip is connected with the back of the first chip.

Further, the pins of the third chip are connected with the second bonding finger of the substrate and the pins of the first chip through leads, wherein the leads connecting the pins of the third chip and the pins of the first chip penetrate through the slotted holes.

Further, the adapter plate is provided with a conductive through hole.

Further, the conductive via is electrically connected to the metal post and the solder ball.

Further, the first bonding finger is located at an edge of the substrate; and

the second bonding fingers are positioned at two sides of the slot hole.

Further, the bonding pads are located on two sides of the back surface of the substrate and located on the outer sides of the second bonding fingers.

The utility model has at least the following beneficial effects: the utility model discloses a double-sided bonding stacked structure of a substrate, which adopts the substrate with a slotted hole, stacks chips on the front side and the back side of the substrate, and realizes chip interconnection on the front side and the back side of the substrate by utilizing leads penetrating through the slotted hole.

Drawings

To further clarify the above and other advantages and features of embodiments of the present utility model, a more particular description of embodiments of the utility model will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the utility model and are therefore not to be considered limiting of its scope. In the drawings, for clarity, the same or corresponding parts will be designated by the same or similar reference numerals.

FIG. 1 shows a schematic cross-sectional view of a prior art chip stack package structure;

FIG. 2A shows a schematic cross-sectional view of a prior art chip-tiling package;

FIGS. 2B and 2C show schematic top views of chips in a prior art chip-tiling package;

FIG. 3 illustrates a cross-sectional schematic view of a substrate double-sided bonded stack according to one embodiment of the present utility model;

FIG. 4 illustrates top and bottom views of a substrate according to one embodiment of the utility model; and

fig. 5 shows a schematic cross-sectional view of a process of forming a double-sided bonded-substrate stack structure according to one embodiment of the utility model.

Detailed Description

The utility model is further elucidated below in connection with the embodiments with reference to the drawings. It should be noted that the components in the figures may be shown exaggerated for illustrative purposes and are not necessarily to scale. In the drawings, identical or functionally identical components are provided with the same reference numerals.

In the present utility model, unless specifically indicated otherwise, "disposed on …", "disposed over …" and "disposed over …" do not preclude the presence of an intermediate therebetween. Furthermore, "disposed on or above" … merely indicates the relative positional relationship between the two components, but may also be converted to "disposed under or below" …, and vice versa, under certain circumstances, such as after reversing the product direction.

In the present utility model, the embodiments are merely intended to illustrate the scheme of the present utility model, and should not be construed as limiting.

In the present utility model, the adjectives "a" and "an" do not exclude a scenario of a plurality of elements, unless specifically indicated.

It should also be noted herein that in embodiments of the present utility model, only a portion of the components or assemblies may be shown for clarity and simplicity, but those of ordinary skill in the art will appreciate that the components or assemblies may be added as needed for a particular scenario under the teachings of the present utility model.

It should also be noted herein that, within the scope of the present utility model, the terms "identical", "equal" and the like do not mean that the two values are absolutely equal, but rather allow for some reasonable error, that is, the terms also encompass "substantially identical", "substantially equal". By analogy, in the present utility model, the term "perpendicular", "parallel" and the like in the table direction also covers the meaning of "substantially perpendicular", "substantially parallel".

The utility model is further elucidated below in connection with the embodiments with reference to the drawings.

Fig. 3 is a schematic cross-sectional view of a double-sided bonded substrate stack according to an embodiment of the present utility model. Fig. 4 illustrates top and bottom views of a substrate according to one embodiment of the utility model.

As shown in fig. 3, a stacked package structure with double-sided bonding of substrates includes a substrate 101, a first chip 102, a second chip 103, a third chip 104, a metal pillar 105, an interposer 106, solder balls 107, a molding layer 108, and leads 109.

As shown in fig. 4, the middle part of the substrate 101 has a slot 1011, the front surface of which has a first bonding finger 1012, and the first bonding finger 1012 is located at the edge of the substrate 101; the back surface of the substrate 101 has second bonding fingers 1013 and pads 1014, wherein the second bonding fingers 1013 are located at both sides of the slot 1011, the pads 1014 are located at both sides of the back surface of the substrate 101, and are located at the outer sides of the second bonding fingers 1013; the back surface of the substrate 101 also has a 1-foot mark 1015 for identifying the mounting direction of the chip.

As shown in fig. 3, the first chip 102 is disposed on the front surface of the substrate 101. The middle of the front side of the first chip 102 has pins. The first chip 102 is flip-chip mounted on the front surface of the substrate 101, and pins of the first chip 102 are located in the slots 1011.

The back surface of the second chip 103 is connected to the back surface of the first chip 102. Pins on the front side of the second chip 103 are connected to first bonding fingers 1012 on the front side of the substrate by leads 109.

The back surface of the third chip 104 is connected with the back surface of the substrate 101, and the pins on the front surface of the third chip 104 are connected with the second bonding finger 1013 on the back surface of the substrate and the pins of the first chip 102 through the leads 109, wherein the leads connecting the pins of the third chip 104 and the pins of the first chip 102 pass through the slots 1011. The number of third chips 104 may be one or more.

The metal posts 105 are connected to pads 1014 on the back side of the substrate 101.

The interposer 106 is connected to the substrate 101 through the metal posts 105. The interposer 106 has conductive vias 1061 therein. The metal posts 105 are electrically connected to the conductive vias 1061.

Solder balls 107 are disposed on the back side of the interposer 106 and electrically connected to the conductive vias 1061.

The molding layer 108 encapsulates the substrate 101, the first chip 102, the second chip 103, the third chip 104, the metal posts 105, and the leads 109.

The process for forming the double-sided bonding lamination structure of the substrate comprises the following steps:

in step 1, the first chip 202 is flip-chip attached to the front surface of the substrate 201. The middle part of the substrate 201 is provided with a slot 2011, the front surface of the slot 2011 is provided with a first bonding finger, and the first bonding finger is positioned at the edge of the substrate 201; the back of the substrate 201 is provided with second bonding fingers and bonding pads, wherein the second bonding fingers are positioned at two sides of the slot, and the bonding pads are positioned at two sides of the back of the substrate 201 and are positioned at the outer sides of the second bonding fingers; the back side of the substrate 201 also has a 1-pin mark for identifying the mounting direction of the chip. The front surface of the first chip 202 is connected to the front surface of the substrate 201, and pins of the first chip 202 are located in slots 2011 of the substrate 201.

Step 2, a third chip 203 is arranged on the back surface of the substrate 201. The number of third chips 203 may be one or more. In the present embodiment, 2 third chips 203 are disposed on both sides of the slot 2011, and the back surface thereof is connected to the substrate.

In step 3, pins of the third chip 203 are connected to the second bonding fingers of the substrate via the leads 204, and pins of the third chip 203 are connected to pins of the first chip 202.

In step 4, the metal posts 205 are disposed on the back surface of the substrate 201 by connecting the metal posts 205 with the pads.

In step 5, a second chip 206 is disposed on the first chip 202, wherein the back side of the second chip 206 is connected to the back side of the first chip 202.

In step 6, pins of the second chip 206 are connected to the first bonding fingers of the substrate 201 via the leads 204.

Step 7, the metal post 205 is connected to the adapter plate 207. The interposer 207 has conductive vias 2071 therein. The metal posts 205 are electrically connected to the conductive vias 2071.

In step 8, the plastic package substrate 201, the first chip 202, the second chip 206, the third chip 203, the metal pillars 205, and the leads 204 form a plastic package layer 208.

In step 8, solder balls 209 are disposed on the back surface of the interposer 207. Solder balls 208 are electrically connected to conductive vias 2071.

While various embodiments of the present utility model have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to those skilled in the relevant art that various combinations, modifications, and variations can be made therein without departing from the spirit and scope of the utility model. Thus, the breadth and scope of the present utility model as disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. The utility model provides a double-sided bonding's of base plate fold seal structure which characterized in that includes:

2. The double-sided bonded substrate stack of claim 1, further comprising:

a metal post connected to the pad;

the adapter plate is connected with the substrate through the metal column; and

and the solder balls are arranged on the back surface of the adapter plate.

3. The double-sided bonded package structure of the substrate according to claim 1, wherein pins of the second chip are connected to the first bonding fingers of the substrate by leads; and

the back of the second chip is connected with the back of the first chip.

4. The double-sided substrate bonded stack structure of claim 1, wherein pins of the third chip are connected with the second bonding fingers of the substrate and pins of the first chip by leads, wherein the leads connecting the pins of the third chip with the pins of the first chip pass through slots.

5. The double-sided bonded substrate stack structure of claim 2, wherein the interposer has conductive vias therein.

6. The double-sided bonded substrate stack structure of claim 5, wherein the conductive via is electrically connected to the metal stud and the solder ball.

7. The double-sided bonded substrate stack of claim 1, wherein the first bonding finger is located at an edge of the substrate; and

the second bonding fingers are positioned at two sides of the slot hole.

8. The double-sided bonded stack structure of the substrate according to claim 1, wherein the bonding pads are located on both sides of the back surface of the substrate and are located on the outer sides of the second bonding fingers.