CN219016430U - Current detection circuit - Google Patents
Current detection circuit Download PDFInfo
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- CN219016430U CN219016430U CN202221932711.9U CN202221932711U CN219016430U CN 219016430 U CN219016430 U CN 219016430U CN 202221932711 U CN202221932711 U CN 202221932711U CN 219016430 U CN219016430 U CN 219016430U
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Abstract
The utility model discloses a current detection circuit, which in a specific example comprises a first sampling circuit, a second sampling circuit, an analog-to-digital converter, an arithmetic unit and a control unit, wherein a first input end of the first sampling circuit is connected with an output end of a device to be detected, a second input end of the first sampling circuit is connected with the control unit, and an output end of the first sampling circuit is connected with the analog-to-digital converter; the first sampling circuit is turned on/off in response to a first control signal sent by the control unit; the first input end of the second sampling circuit is connected with the output end of the device to be tested, the second input end of the second sampling circuit is connected with the control unit, the output end of the second sampling circuit is connected with the analog-to-digital converter, and the second sampling circuit is turned on/off in response to a second control signal sent by the control unit; the output end of the analog-to-digital converter is connected with the arithmetic unit.
Description
Technical Field
The present utility model relates to the field of circuits. And more particularly to a current detection circuit.
Background
At present, a current detection circuit is still an important means for detecting the quality of a device to be detected by detecting the current of the device to be detected, and the current value is mainly obtained by collecting the voltages at two ends of a load and calculating the voltages at two ends of different loads, and the corresponding current data are different, so that the data under two loads of the device to be detected are judged, and the accuracy of detecting the quality of the device to be detected is further enhanced.
Disclosure of Invention
The present utility model is directed to a current detection circuit that solves at least one of the problems of the prior art.
In order to achieve the above purpose, the utility model adopts the following technical scheme:
the first aspect of the present utility model provides a current detection circuit comprising a first sampling circuit, a second sampling circuit, an analog-to-digital converter, an operator and a control unit,
the first input end of the first sampling circuit is connected with the output end of the device to be tested, the second input end of the first sampling circuit is connected with the control unit, and the output end of the first sampling circuit is connected with the analog-to-digital converter; the first sampling circuit is turned on/off in response to a first control signal sent by the control unit;
the first input end of the second sampling circuit is connected with the output end of the device to be tested, the second input end of the second sampling circuit is connected with the control unit, the output end of the second sampling circuit is connected with the analog-to-digital converter, and the second sampling circuit is turned on/off in response to a second control signal sent by the control unit;
the output end of the analog-to-digital converter is connected with the arithmetic unit.
Optionally, the first sampling circuit and the second sampling circuit each comprise a current acquisition circuit and a signal control circuit, wherein,
the input end of the current acquisition circuit is connected with the output end of the device to be tested, and the output end of the current acquisition circuit is connected with the analog-to-digital converter;
the input end of the signal control circuit is connected with the control unit, and the output end of the signal control circuit is connected to the control end of the current acquisition circuit.
Optionally, the signal control circuit includes a first field effect transistor, a gate of the first field effect transistor is connected to the control unit through a first resistor, a source of the first field effect transistor is connected to a control end of the current acquisition circuit through a second resistor, and a drain of the first field effect transistor is grounded.
Optionally, the current detection circuit further comprises a stop sampling circuit,
the first end of the stop sampling circuit is used as a voltage input end of the current detection circuit to be connected with a signal input end of the device to be tested, the second end of the stop sampling circuit is used as a voltage output end of the current detection circuit, the third end of the stop sampling circuit is connected with the third control signal input end, and the stop sampling circuit is turned on/off in response to a third control signal;
the second resistor is grounded at one end, and the other end is connected between the grid electrode of the second field effect transistor and the second resistor.
Optionally, the current collecting circuit includes a second field effect transistor and a sampling resistor, a drain electrode of the second field effect transistor is connected to an output end of the device under test, a gate electrode of the second field effect transistor is connected to an output end of the signal control circuit, a source electrode of the second field effect transistor is connected to one end of the sampling resistor, and the other end of the sampling resistor is grounded.
Optionally, the analog-to-digital converters are respectively connected to two ends of the sampling resistor to obtain the voltage of the sampling resistor.
Optionally, the resistances of the sampling resistors in the first sampling circuit and the second sampling circuit are different.
Optionally, the current detection circuit further includes a test circuit, a first input end of the test circuit is connected to an output end of the device under test, a second input end of the test circuit is connected to the control unit, and an output end of the test circuit is connected to an input end of the detection device.
Optionally, the test circuit includes: the device comprises a test transmission circuit and a test control circuit, wherein the input end of the test transmission circuit is connected with the output end of a device to be tested, and the output end of the test transmission circuit is connected to the input end of a detection device;
the input end of the test control circuit is connected with the control unit, and the output end of the test control circuit is connected to the control end of the test transmission circuit.
The beneficial effects of the utility model are as follows:
the current detection circuit provided by the embodiment detects the currents of different states of the device to be detected according to the control signals, and the detection circuit does not need to be manually switched by a worker, so that the working efficiency is improved, the working time is shortened, and the circuit structure is simple and convenient to use.
Drawings
The following describes the embodiments of the present utility model in further detail with reference to the drawings.
Fig. 1 shows a schematic diagram of a current detection circuit according to the present utility model.
Detailed Description
In order to more clearly illustrate the present utility model, the present utility model will be further described with reference to examples and drawings. Like parts in the drawings are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and that this utility model is not limited to the details given herein.
As shown in fig. 1, a current detection circuit provided in one embodiment of the present utility model includes a first sampling circuit 11, a second sampling circuit 12, an analog-to-digital converter ADC, an arithmetic unit and a control unit (not shown in the figure), where a first input terminal 110 of the first sampling circuit 11 is connected to an output terminal of a device to be tested, a second input terminal 116 is connected to an output terminal of the control unit, an output terminal thereof is connected to the analog-to-digital converter ADC, and the first sampling circuit 11 is turned on/off in response to a first control signal IO1 sent by the control unit;
the first input end 120 of the second sampling circuit 12 is connected with the output end of the device to be tested, the second input end 126 of the second sampling circuit is connected with the output end of the control unit, and the output end of the second sampling circuit 12 is connected with the analog-to-digital converter ADC; the second sampling circuit 12 is turned on/off in response to a second control signal IO2 issued by the control unit;
and the output end of the analog-to-digital converter ADC is connected with the arithmetic unit.
The current detection circuit provided by the embodiment can detect the current of the device to be detected under different states according to the control signals sent by the control unit, does not need manual switching of the detection circuit by a worker, improves the working efficiency, reduces the working time, and has a simple circuit structure and convenient use.
In one possible implementation, the first sampling circuit 11 and the second sampling circuit 12 each comprise a current acquisition circuit and a signal control circuit, wherein,
the input end of the current acquisition circuit is connected with the output end of the device to be tested, and the output end of the current acquisition circuit is connected with the analog-to-digital converter;
the input end of the signal control circuit is connected with the control unit, and the output end of the signal control circuit is connected to the control end of the current acquisition circuit.
Taking the first sampling circuit 11 as an example, the signal control circuit of the first sampling circuit 11 includes a first field effect transistor Q1, a gate 115 of the first field effect transistor Q1 is connected to the control unit through a first resistor R1, a source 113 of the first field effect transistor Q1 is connected to a gate 112 of a corresponding current collecting circuit through a second resistor R2, and a drain 114 of the first field effect transistor is grounded.
In a specific embodiment, the signal control circuit of the first sampling circuit 11 further includes a third resistor R3, where one end of the third resistor R3 is grounded, and the other end is connected between the gate 115 of the first field effect transistor Q1 and the first resistor R1.
In one possible implementation manner, the current collection circuit of the first sampling circuit 11 includes a second field effect transistor Q2 and a first sampling resistor R5, where a drain 110 of the second field effect transistor Q2 is connected to an output terminal of the device under test, a source 111 of the second field effect transistor Q2 is connected to one end of the first sampling resistor R5, and the other end of the first sampling resistor R5 is grounded.
Specifically, the two ends 117 and 118 of the first sampling resistor R5 are respectively connected to the first input terminal P1 and the second input terminal N1 of the analog-to-digital converter, and the first sampling circuit 11 is turned on/off in response to the first control signal IO 1.
Taking the second sampling circuit 12 as an example, the signal control circuit of the second sampling circuit 12 includes a third field effect transistor Q3, where a gate 125 of the third field effect transistor Q3 is connected to the control unit through a fourth resistor R5, a source 123 of the third field effect transistor Q3 is connected to a gate 122 of the current collecting circuit through a fifth resistor R6, and a drain 124 of the third field effect transistor Q3 is grounded.
In a specific embodiment, the signal control circuit of the second sampling circuit 12 further includes a sixth resistor R7, where one end of the sixth resistor R7 is grounded, and the other end is connected between the gate 125 of the third field effect transistor Q3 and the fourth resistor R5.
In one possible implementation manner, the current collecting circuit of the second sampling circuit 12 includes a fourth field effect transistor Q4 and a second sampling resistor R9, where a drain 120 of the fourth field effect transistor Q4 is connected to an output terminal of the device under test, a source 121 of the fourth field effect transistor Q4 is connected to one end of the second sampling resistor R9, and the other end of the second sampling resistor R9 is grounded.
The first input end 120 of the second sampling circuit 12 is connected with the output end of the device under test, the second input end 126 is connected with the control unit to receive a second control signal IO2, two ends 127 and 128 of the second sampling resistor R9 are respectively connected with the third input end P2 and the fourth input end N2 of the analog-digital converter, and the second sampling circuit 12 is turned on/off in response to the second control signal IO 2; the output end of the analog-to-digital converter is connected with the input end of the arithmetic unit.
The current detection circuit that this embodiment provided can carry out the current detection under the different states respectively according to control signal, need not the manual switching detection circuit of staff, has improved work efficiency, has reduced operating time, and circuit structure is simple convenient to use.
It should be noted that the resistances of the sampling resistors of the first sampling circuit 11 and the second sampling circuit 12 are different.
In a specific embodiment, the resistance value of the first sampling resistor R5 is 3.9Ω, the voltage signal collected by the first sampling circuit 11 is converted into a digital signal by the analog-to-digital converter, and the arithmetic unit converts the voltage signal transmitted by the analog-to-digital converter into current data, so as to realize current detection under different states of the device to be tested.
In a specific embodiment, the resistance value of the second sampling resistor R9 is 0.15Ω, the voltage signal collected by the second sampling circuit 12 is converted into a digital signal by the analog-to-digital converter ADC, and the arithmetic unit converts the voltage signal transmitted by the analog-to-digital converter into current data, so as to realize detection of the current of the device to be tested.
In a specific embodiment, the current detection circuit further comprises a test circuit 13.
The first input end 130 of the test circuit 13 is connected to the output end of the device under test, the second input end 136 of the test circuit 13 is connected to the control unit, the output end 131 of the test circuit 13 is connected to the input end of the detection device, and the test circuit 13 is turned on/off in response to the third control signal IO3 sent by the control unit.
In a specific embodiment, the test circuit 13 includes a test transmission circuit, an input 130 of which is connected to an output of the DUT, an output of which is connected to an input of the test equipment, and a test control circuit, an input 136 of which is connected to the control unit to receive the third control signal IO3, and an output of which is connected to a control 132 of the test transmission circuit.
In a specific embodiment, the test control circuit of the test circuit 13 includes a fifth field effect transistor Q2, a seventh resistor R9, and an eighth resistor R10.
The gate 135 of the fifth field effect transistor Q5 is connected to the control unit through the seventh resistor R9, the source 133 of the fifth field effect transistor Q5 is connected to the control end 132 of the test transmission circuit through the eighth resistor R10, and the drain 134 of the fifth field effect transistor Q5 is grounded.
In a specific embodiment, the test control circuit further includes a ninth resistor R11, where one end of the ninth resistor R11 is grounded, and the other end is connected between the gate 136 of the fifth field effect transistor Q5 and the seventh resistor R9.
In a specific embodiment, the test transmission circuit includes a sixth field effect transistor Q6, a drain 130 of the sixth field effect transistor Q6 is connected to the output terminal of the device under test, and a source 131 of the sixth field effect transistor Q6 is connected to the input terminal of the detection device.
In a specific embodiment, the control unit is, for example, a single-chip microcomputer, and the first control signal output end, the second control signal output end and the third control signal output end of the single-chip microcomputer are respectively connected with the first input ends of the first sampling circuit 11, the second sampling circuit 12 and the testing circuit 13.
It should be noted that, during detection, only one high level can exist in the first control signal IO1, the second control signal IO2 and the third control signal IO3 output by the single chip microcomputer; when the first control signal IO1 is at a high level, the second control signal IO2 and the third control signal IO3 are at a low level, the first field effect transistor Q1 and the second field effect transistor Q2 are turned on, the analog-to-digital converter ADC collects voltages at two ends of the first sampling resistor R5, and when the resistance value of the first sampling resistor R5 is far greater than that of the second sampling resistor R9, the current detection circuit detects a small current; when the second control signal IO2 is at a high level, the third field effect transistor Q3 and the fourth field effect transistor Q4 are turned on, the analog-to-digital converter collects voltages at two ends of the second sampling resistor R9, and if the resistance of the first sampling resistor R5 is far greater than the resistance of the second sampling resistor R9, the current detection circuit is configured to detect a large current; if the third control signal IO3 is at a high level, the current detection circuit skips sampling, does not sample the voltage value, and directly outputs a signal to the detection device.
In a specific embodiment, the device to be tested is a liquid crystal panel, the liquid crystal panel displays a picture corresponding to a state, each state needs to detect a large current and a small current, current values under different sampling resistors in different states are obtained, and the quality of the liquid crystal panel is judged according to the detected current values.
It should be noted that, before detection, the current values of the liquid crystal panel when displaying different images corresponding to different loads need to be tested respectively to obtain two normal ranges, and the quality of the device to be detected is judged according to the normal ranges.
In one possible implementation, the first field effect transistor Q1, the second field effect transistor Q2, the third field effect transistor Q3, the fourth field effect transistor Q4, the fifth field effect transistor Q5 and the sixth field effect transistor Q6 are NMOS transistors, and it should be understood by those skilled in the art that the gates of the NMOS transistors are turned on when they are at a high level.
In a specific embodiment, the operator is integrated in the analog-to-digital converter, further reducing the size of the detection circuit.
In the description of the present utility model, it should be noted that the azimuth or positional relationship indicated by the terms "upper", "lower", etc. are based on the azimuth or positional relationship shown in the drawings, and are merely for convenience of describing the present utility model and simplifying the description, and are not indicative or implying that the apparatus or element in question must have a specific azimuth, be constructed and operated in a specific azimuth, and thus should not be construed as limiting the present utility model. Unless specifically stated or limited otherwise, the terms "mounted," "connected," and "coupled" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to the specific circumstances.
It is further noted that in the description of the present utility model, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
It should be understood that the foregoing examples of the present utility model are provided merely for the purpose of clearly illustrating the present utility model and are not to be construed as limiting the embodiments of the present utility model, and that various other changes and modifications can be made by one skilled in the art based on the above description, which are not intended to be exhaustive or all of the embodiments, and all obvious changes and modifications that come within the spirit of the utility model.
Claims (10)
1. A current detection circuit is characterized by comprising a first sampling circuit, a second sampling circuit, an analog-to-digital converter, an arithmetic unit and a control unit,
the first input end of the first sampling circuit is connected with the output end of the device to be tested, the second input end of the first sampling circuit is connected with the control unit, and the output end of the first sampling circuit is connected with the analog-to-digital converter; the first sampling circuit is turned on/off in response to a first control signal sent by the control unit;
the first input end of the second sampling circuit is connected with the output end of the device to be tested, the second input end of the second sampling circuit is connected with the control unit, the output end of the second sampling circuit is connected with the analog-to-digital converter, and the second sampling circuit is turned on/off in response to a second control signal sent by the control unit;
the output end of the analog-to-digital converter is connected with the arithmetic unit.
2. The current detection circuit according to claim 1, wherein,
the first sampling circuit and the second sampling circuit both comprise a current acquisition circuit and a signal control circuit, wherein,
the input end of the current acquisition circuit is connected with the output end of the device to be tested, and the output end of the current acquisition circuit is connected with the analog-to-digital converter;
the input end of the signal control circuit is connected with the control unit, and the output end of the signal control circuit is connected to the control end of the current acquisition circuit.
3. The current detection circuit according to claim 2, wherein,
the signal control circuit comprises a first field effect transistor, wherein the grid electrode of the first field effect transistor is connected to the control unit through a first resistor, the source electrode of the first field effect transistor is connected to the control end of the current acquisition circuit through a second resistor, and the drain electrode of the first field effect transistor is grounded.
4. The current detection circuit of claim 3, further comprising a third resistor having one end connected to ground and the other end connected between the gate of the first field effect transistor and the first resistor.
5. The current detection circuit according to claim 4, wherein the current collection circuit comprises a second field effect transistor and a sampling resistor, a drain electrode of the second field effect transistor is connected to an output terminal of the device under test, a gate electrode of the second field effect transistor is connected to an output terminal of the signal control circuit, a source electrode of the second field effect transistor is connected to one end of the sampling resistor, and the other end of the sampling resistor is grounded.
6. The current detection circuit of claim 5, wherein the analog-to-digital converters are respectively connected to both ends of the sampling resistor to obtain the voltage of the sampling resistor.
7. The current detection circuit according to claim 6, wherein resistance values of sampling resistors in the first sampling circuit and the second sampling circuit are different.
8. The current detection circuit of claim 5, wherein the first field effect transistor and the second field effect transistor each employ NMOS transistors.
9. The current detection circuit of claim 1, further comprising a test circuit, a first input of the test circuit being connected to an output of the device under test, a second input of the test circuit being connected to a control unit, an output of the test circuit being connected to an input of a detection device.
10. The current detection circuit of claim 9, wherein the test circuit comprises: the device comprises a test transmission circuit and a test control circuit, wherein the input end of the test transmission circuit is connected with the output end of a device to be tested, and the output end of the test transmission circuit is connected to the input end of a detection device;
the input end of the test control circuit is connected with the control unit, and the output end of the test control circuit is connected to the control end of the test transmission circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221932711.9U CN219016430U (en) | 2022-07-26 | 2022-07-26 | Current detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221932711.9U CN219016430U (en) | 2022-07-26 | 2022-07-26 | Current detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219016430U true CN219016430U (en) | 2023-05-12 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221932711.9U Active CN219016430U (en) | 2022-07-26 | 2022-07-26 | Current detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219016430U (en) |
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2022
- 2022-07-26 CN CN202221932711.9U patent/CN219016430U/en active Active
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