CN218957728U - Packaging substrate and electronic package - Google Patents
Packaging substrate and electronic package Download PDFInfo
- Publication number
- CN218957728U CN218957728U CN202223417121.5U CN202223417121U CN218957728U CN 218957728 U CN218957728 U CN 218957728U CN 202223417121 U CN202223417121 U CN 202223417121U CN 218957728 U CN218957728 U CN 218957728U
- Authority
- CN
- China
- Prior art keywords
- substrate
- connection structure
- layer
- metal
- polarity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The embodiment of the application discloses a packaging substrate and an electronic package, relates to the technical field of integrated circuits, and aims to effectively improve the quality of a power supply. The package substrate includes: a substrate and an interconnect layer; the interconnection layer is arranged on the substrate, and comprises a first dielectric layer and a first metal layer which are alternately stacked, wherein the first metal layer comprises a metal connecting wire; the substrate comprises second metal layers and second dielectric layers which are alternately arranged, wherein each two adjacent second metal layers and one second dielectric layer sandwiched between the two second metal layers form a capacitor unit, one second metal layer in each capacitor unit is used for being connected with a power supply, and the other second metal layer is used for being connected with the ground. The present application is applicable to transmitting signals.
Description
Technical Field
The present disclosure relates to integrated circuit technology, and more particularly, to a package substrate and an electronic package.
Background
At present, as the core number of high-end high-performance chips such as a Central Processing Unit (CPU), an image processor (GPU) and the like is continuously increased, the chips are larger and larger, and the yield is gradually reduced; to improve chip yield, the industry has generally moved to small chips (chips) for high-end high-performance chips, reducing the area of individual chips. After the small chip is turned to, high bandwidth interconnection is needed between small chip dies (die), and advanced packaging is needed to perform high density interconnection to meet the requirement.
The high-density interconnected substrate has higher requirements on the quality of the power supply, so that a decoupling capacitor is arranged outside the substrate, and the decoupling capacitor is arranged outside the substrate and far away from the power supply, so that the decoupling effect is poor, and the quality of the power supply is poor.
Disclosure of Invention
In view of this, the embodiments of the present application provide a package substrate and an electronic package, which can effectively improve the power quality.
In a first aspect, embodiments of the present application provide a package substrate, including: a substrate and an interconnect layer; the interconnection layer is arranged on the substrate, and comprises a first dielectric layer and a first metal layer which are alternately stacked, wherein the first metal layer comprises a metal connecting wire; the substrate comprises second metal layers and second dielectric layers which are alternately arranged, wherein each two adjacent second metal layers and one second dielectric layer sandwiched between the two second metal layers form a capacitor unit, one second metal layer in each capacitor unit is used for being connected with a power supply, and the other second metal layer is used for being connected with the ground.
Optionally, the second metal layer and the second dielectric layer are respectively parallel to the interconnection layer; alternatively, the second metal layer and the second dielectric layer are perpendicular to the interconnection layer, respectively.
Optionally, the second metal layer and the second dielectric layer are perpendicular to the interconnection layer, respectively; the substrate is provided with grooves, the second metal layers and the second dielectric layers are alternately arranged along the side walls of the grooves towards the center of the grooves, and the grooves are filled with the second metal layers and the second dielectric layers.
Optionally, the second metal layer and the second dielectric layer are planar or curved.
Optionally, a first connection structure and a second connection structure are provided in the substrate; the first connection structure is used for coupling a second metal layer in a first polarity in each capacitor unit, and the second connection structure is used for coupling a second metal layer in a second polarity in each capacitor unit, wherein the first polarity is opposite to the second polarity.
Optionally, a third connection structure and a fourth connection structure are provided in the interconnection layer; one end of the third connecting structure is connected with the first connecting structure in the substrate, and the other end of the third connecting structure is exposed on the surface of the interconnection layer far away from the substrate; and one end of the fourth connecting structure is connected with the second connecting structure in the substrate, and the other end of the fourth connecting structure is exposed on the surface of the interconnection layer far away from the substrate.
Optionally, the first connection structure and the second connection structure pass through the substrate, and ends of the first connection structure and the second connection structure are exposed at a surface of the substrate remote from the interconnect layer.
Optionally, the material of the first dielectric layer is polyimide.
Optionally, the material of the second dielectric layer is ceramic.
In a second aspect, embodiments of the present application provide an electronic package, including: the semiconductor device comprises a first substrate, a second substrate, a first crystal grain and a second crystal grain; the second substrate is arranged in a cavity with an upward opening of the first substrate; the second substrate is the package substrate according to any one of the foregoing embodiments; the upper surface of the first substrate and the upper surface of the second substrate are provided with bumps; a part of pins of the first crystal grain are connected with the bumps on the first substrate, and the other part of pins are connected with the bumps on the second substrate; a part of pins of the second crystal grain are connected with the bumps on the first substrate, and the other part of pins are connected with the bumps on the second substrate; at least a portion of the bumps on the second substrate are connected to first metal connection lines in the interconnection layer of the second substrate, so that the first die and the second die are interconnected by the first metal connection lines.
Optionally, the width of the bump connected with the first die on the first substrate is larger than the width of the bump connected with the first die on the second substrate; the width of the protruding blocks connected with the second crystal grains on the first substrate is larger than that of the protruding blocks connected with the second crystal grains on the second substrate.
Optionally, a pitch between bumps on the first substrate connected to the first die is greater than a pitch between bumps on the second substrate connected to the first die; the pitch between the bumps connected with the second crystal grain on the first substrate is larger than the pitch between the bumps connected with the second crystal grain on the second substrate.
Optionally, a first connection structure and a second connection structure are arranged in the substrate of the second substrate; the first connection structure is used for coupling a second metal layer in a first polarity in each capacitor unit, and the second connection structure is used for coupling a second metal layer in a second polarity in each capacitor unit, wherein the first polarity is opposite to the second polarity; a third connection structure and a fourth connection structure are arranged in the interconnection layer of the second substrate; one end of the third connecting structure is connected with the first connecting structure in the substrate, and the other end of the third connecting structure is exposed on the surface of the interconnection layer away from the substrate and is used for being connected with one of power supply or ground; and one end of the fourth connecting structure is connected with the second connecting structure in the substrate, and the other end of the fourth connecting structure is exposed on the surface of the interconnection layer away from the substrate and is used for being connected with the other one of power supply and ground.
Optionally, a first connection structure and a second connection structure are arranged in the substrate of the second substrate; the first connection structure is used for coupling a second metal layer in a first polarity in each capacitor unit, and the second connection structure is used for coupling a second metal layer in a second polarity in each capacitor unit, wherein the first polarity is opposite to the second polarity; the first connection structure and the second connection structure penetrate through the substrate of the second substrate, and the tail ends of the first connection structure and the second connection structure are exposed on the surface, away from the interconnection layer, of the substrate and are used for being connected with power supply or ground in the first substrate respectively.
The embodiment of the application provides a packaging substrate and an electronic package, wherein an interconnection layer is arranged on a substrate, the interconnection layer comprises a first dielectric layer and a first metal layer which are alternately stacked, and the first metal layer comprises a metal connecting wire; the substrate comprises second metal layers and second dielectric layers which are alternately arranged, wherein each two adjacent second metal layers and one second dielectric layer sandwiched between the two second metal layers form a capacitor unit, one second metal layer in each capacitor unit is used for being connected with a power supply, and the other second metal layer is used for being connected with the ground.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a package substrate according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a package substrate according to another embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a package substrate according to another embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of an electronic package according to an embodiment of the present disclosure;
FIG. 5 is a schematic structural diagram of a first substrate according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of a bump on a first substrate and a second substrate according to an embodiment of the present disclosure;
FIG. 7 is a schematic view of a ceramic film and a metal layer according to an embodiment of the present disclosure;
FIG. 8 is a schematic diagram of a structure of drilling holes in a ceramic film according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of connection between a capacitor unit in a second substrate and a power line and a ground line in a first substrate according to an embodiment of the present disclosure.
Detailed Description
Embodiments of the present application are described in detail below with reference to the accompanying drawings. It should be understood that the described embodiments are merely some, but not all, of the embodiments of the present application. All other embodiments, based on the embodiments herein, which would be apparent to one of ordinary skill in the art without making any inventive effort, are intended to be within the scope of the present application.
As shown in fig. 1, an embodiment of the present application provides a package substrate, which may include: a substrate 11 and an interconnect layer 12; wherein the interconnection layer 12 is disposed on the substrate 11, the interconnection layer 12 includes a first dielectric layer 120 and a first metal layer 122 that are alternately stacked, and the first metal layer 122 includes a metal connection line;
the substrate 11 includes second metal layers 110 and second dielectric layers 112 alternately arranged, wherein each two adjacent second metal layers 110 and one second dielectric layer 112 sandwiched therebetween form a capacitor unit C0, one second metal layer 110 in each capacitor unit C0 is used for connecting a power supply, and the other second metal layer 110 is used for connecting a ground.
The substrate 11 supports the interconnect layer 12.
The material of the first dielectric layer 120 may be silicon oxide, but the silicon oxide has a high requirement on the environment of the processing equipment.
The material of the second dielectric layer 112 may be silicon, glass, polyimide or ceramic, and in this embodiment, the material of the second dielectric layer is ceramic, and since the dielectric coefficient of the ceramic is larger than that of silicon and glass, the capacity of the capacitor unit including the second dielectric layer is larger, so that the decoupling effect can be better improved, and the power quality can be effectively improved.
The material of the first and second metal layers 122 and 110 may be copper.
It will be appreciated that two second metal layers 110 and a second dielectric layer 112 therebetween may be disposed in the substrate to form a capacitor unit, or multiple second metal layers 110 and second dielectric layers therebetween may be disposed to form multiple capacitor units.
In the case of the package substrate as an interconnection substrate for interconnection between two dies, the first metal layer 122 includes metal connection lines for signal transmission between the two dies.
In the package substrate provided in this embodiment of the present application, the second metal layers 110 and the second dielectric layers 112 that are alternately arranged are disposed in the substrate 11, where each two adjacent second metal layers 110 and one second dielectric layer 112 sandwiched between them may form a capacitor unit C0, one second metal layer 110 in each capacitor unit C0 is used for connecting to a power supply, and the other second metal layer 110 is used for connecting to a ground, so that when the capacitor structure is connected to the power supply and the ground, decoupling filtering can be performed on the power supply and the ground, and because the capacitor structure is disposed in the package substrate, compared with the case that the capacitor is disposed outside the package substrate in the prior art, the decoupling path can be effectively shortened, the decoupling effect is greatly improved, and thus the power quality can be effectively improved.
In the embodiment of the present application, the specific arrangement direction of the second metal layers 110 and the second dielectric layers 112 that are alternately arranged is not limited, as long as the second metal layers 110 and the second dielectric layers 112 are parallel to each other. For example, each of the second metal layer 110 and the second dielectric layer 112 may be parallel to the interconnect layer 12, may be perpendicular to the interconnect layer 12, or may be at any angle to the interconnect layer 12. Alternatively, the substrate 11 may be provided with one or more capacitor units C0 in one or more alignment directions, which is not limited in the embodiments of the present application.
Specifically, referring to fig. 1, for the case where each of the second metal layer 110 and the second dielectric layer 112 is parallel to the interconnect layer 12, respectively, the capacitance unit C0 may be obtained by sequentially depositing the second metal layer 110 and the second dielectric layer 112. Referring to fig. 2, for the case where each of the second metal layer 110 and the second dielectric layer 112 is perpendicular to the interconnection layer 12, in one embodiment of the present application, a groove may be provided in the substrate 11, and the second metal layer 110 and the second dielectric layer 112 may be alternately arranged along a sidewall of the groove toward a center of the groove, and filled in the groove.
Alternatively, the cross-sectional shape of the groove is not limited, and may be, for example, circular, square, triangular, polygonal, or the like.
In the embodiment of the present application, the surfaces of the second metal layer 110 and the second dielectric layer 112 may be both planar, or may be both curved, or the surface of the second metal layer 110 may be planar, and the surface of the second dielectric layer 112 may be curved.
In the embodiment of the present application, the first connection structure 114 and the second connection structure 116 are provided in the substrate 11; the first connection structure 114 is used for coupling the second metal layer 110 in each capacitor cell having a first polarity, and the second connection structure 116 is used for coupling the second metal layer 110 in each capacitor cell having a second polarity, wherein the first polarity is opposite to the second polarity.
The first connection structure 114 and the second connection structure 116 may be electrical conductors, in particular, vias may be provided in the substrate 11, it being understood that the vias comprise electrical conductors. The first connection structure 114 couples the second metal layer 110 of the first polarity in each of the capacitor cells, i.e., couples the second metal layer 110 of the first polarity in each of the capacitor cells through the conductor in the via, and the second connection structure 116 couples the second metal layer 110 of the second polarity in each of the capacitor cells, i.e., couples the second metal layer 110 of the second polarity in each of the capacitor cells through the conductor in the via.
The first connection structure 114 is used for coupling the second metal layer 110 with the first polarity in each capacitor unit, and the second connection structure 116 is used for coupling the second metal layer 110 with the second polarity in each capacitor unit, so that the first metal layer 110 with the first polarity and the second metal layer 110 with the second polarity of each capacitor unit can be conveniently led out from the substrate 11 through the first connection structure 114 and the second connection structure 116 and then connected with the power supply and the ground, thereby improving decoupling effect and effectively improving the quality of the power supply.
In the embodiment of the present application, the third connection structure 124 and the fourth connection structure 126 are disposed in the interconnect layer 12; one end of the third connection structure 124 is connected to the first connection structure 114 in the substrate 11, and the other end is exposed at a surface of the interconnect layer 12 away from the substrate 11; the fourth connection structure 126 has one end connected to the second connection structure 102 in the substrate 11 and the other end exposed at a surface of the interconnect layer 12 remote from the substrate 11.
The third connection structure 124 and the fourth connection structure 126 may be vias, and it is understood that the vias include electrical conductors, and one end of the third connection structure 124 is connected to the first connection structure 114 in the substrate 11, that is, one end of the electrical conductor is connected to the first connection structure 114 in the substrate 11; one end of the fourth connection structure 126 is connected to the second connection structure 116 in the substrate 11, i.e. one end of the electrical conductor is connected to the second connection structure 116 in the substrate 11.
The other end of the third connection structure 124 is exposed on the surface of the interconnection layer 12 away from the substrate 11, and the other end of the fourth connection structure 126 is exposed on the surface of the interconnection layer 12 away from the substrate 11, so that the other end of the third connection structure 124 and the other end of the fourth connection structure 126 exposed on the surface of the interconnection layer 12 away from the substrate 11 can be conveniently connected with the power supply and the ground outside the interconnection layer 12 respectively, namely, the connection with the power supply and the ground outside the interconnection layer 12 at the nearest routing distance is convenient, the decoupling effect is improved, and the power supply quality is effectively improved.
In the embodiment of the present application, the first connection structure 114 and the second connection structure 116 penetrate through the substrate 11, and the ends of the first connection structure 114 and the second connection structure 116 are exposed at the surface of the substrate 11 away from the interconnect layer 12.
The ends of the first connection structure 114 and the second connection structure 116 are exposed on the surface of the substrate 11, which is far away from the interconnection layer 12, so that the ends of the first connection structure 114 and the second connection structure 116 can be conveniently connected with the power supply and the ground outside the substrate 11 respectively, and thus, the connection with the power supply and the ground outside the interconnection layer 12 at the nearest routing distance is facilitated, the decoupling effect is improved, and the power supply quality is effectively improved.
Referring to fig. 4, an electronic package provided in an embodiment of the present application may include: a first substrate 1, a second substrate 2, a first die 3, and a second die 4; wherein, the second base plate 2 is arranged in the cavity with the upward opening of the first base plate 1; the second substrate 2 is the package substrate in any of the foregoing embodiments;
the upper surface of the first substrate 1 and the upper surface of the second substrate 2 are provided with bumps; part of pins of the first crystal grain 3 are connected with the bumps on the first substrate 1, and the other part of pins are connected with the bumps on the second substrate 2; part of pins of the second crystal grain 4 are connected with the bumps on the first substrate 1, and the other part of pins are connected with the bumps on the second substrate 2;
at least a portion of the bumps on the second substrate 2 are connected to first metal connection lines in the interconnect layer 12 of the second substrate 2 so that the first die 3 and the second die 4 are interconnected by the first metal connection lines.
Die (die) is a small integrated circuit body fabricated from semiconductor material that is not encapsulated.
The first die 3 and the second die 4 are provided on the first substrate 1 and the second substrate 2.
Referring to fig. 5, the first substrate 1 is etched by exposure development to form a high-precision cavity having an upward opening, and the second substrate 2 is then embedded in the cavity of the first substrate 1.
The bumps on the first substrate 1 and the bumps on the second substrate 2 may include copper pillars and solder balls. Bumps, which may also be copper pillars and solder balls, may be provided on the leads of the first die 3 and the second die 4 before connection to the bumps.
The bumps on the first substrate 1 and the bumps on the second substrate 2 are connected with the pins on the first die 3 and the pins on the second die 4 through a welding process.
At least a portion of the bumps on the second substrate 2 are connected to first metal connection lines in the interconnect layer 12 of the second substrate 2, and the bumps on the second substrate 2 are connected to the first die 3 and the second die 4, such that the first die 3 and the second die 4 are interconnected by the first metal connection lines, such that signals can be transferred between the first die 3 and the second die 4 via the first metal connection lines.
In this embodiment, the second substrate 2 is disposed in the cavity with the upward opening of the first substrate 1, the second substrate 2 is the package substrate in any of the foregoing embodiments, and the upper surface of the first substrate 1 and the upper surface of the second substrate 2 are both provided with bumps; part of pins of the first crystal grain 3 are connected with the bumps on the first substrate 1, and the other part of pins are connected with the bumps on the second substrate 2; part of pins of the second crystal grain 4 are connected with the bumps on the first substrate 1, and the other part of pins are connected with the bumps on the second substrate 2; at least a part of the bump on the second substrate 2 is connected with the first metal connecting wire in the interconnection layer 12 of the second substrate 2, so that the first crystal grain 3 and the second crystal grain 4 are interconnected through the first metal connecting wire, and the capacitor structure is contained in the substrate 11 of the packaging substrate, so that decoupling filtering can be carried out on the power supply and the ground when the capacitor structure is connected with the power supply and the ground, and the capacitor structure is arranged in the packaging substrate, so that the decoupling path can be effectively shortened, the decoupling effect is greatly improved, and the power supply quality is effectively improved as compared with the case that the capacitor is arranged outside the packaging substrate in the prior art.
Referring to fig. 6, in an embodiment of the present application, the width of the bump 5 connected to the first die 3 on the first substrate 1 is larger than the width of the bump 6 connected to the first die 3 on the second substrate 2; the width of the bump 7 connected to the second die 4 on the first substrate 1 is larger than the width of the bump 8 connected to the second die 4 on the second substrate 2.
The width of the bump 5 connected to the first die 3 on the first substrate 1 is larger than the width of the bump 6 connected to the first die 3 on the second substrate 2, so that more bumps 6 can be arranged on the second substrate 2 to be connected to the leads of the first die 3 on the same area.
The width of the bump 7 connected to the second die 4 on the first substrate 1 is larger than the width of the bump 8 connected to the second die 4 on the second substrate 2, so that more bumps 8 can be arranged on the second substrate 2 to be connected to the pins of the second die 4 on the same area.
Referring to fig. 6, in an embodiment of the present application, the pitch between the bumps on the first substrate 1 connected to the first die 3 is greater than the pitch between the bumps on the second substrate 2 connected to the first die 3; the pitch between the bumps on the first substrate 1 connected to the second die 4 is larger than the pitch between the bumps on the second substrate 2 connected to the second die 4.
The pitch between the bumps on the first substrate 1 connected to the first die 3 is larger than the pitch between the bumps on the second substrate 2 connected to the first die 3, so that more bumps can be provided on the second substrate 2 connected to the first die 3 on the same area.
The pitch between the bumps on the first substrate 1 connected to the second die 4 is larger than the pitch between the bumps on the second substrate 2 connected to the second die 4, so that more bumps on the second substrate 2 can be arranged to be connected to the second die 4 on the same area.
In the electronic package, the first die 3 and/or the second die 4 have a power pin and a ground pin, and decoupling capacitors can be provided for the power pin and the ground pin to improve the power quality, referring to fig. 3, in an embodiment of the present application, the substrate of the second substrate 2 is provided with a first connection structure 114 and a second connection structure 116; the first connection structure 114 is used for coupling the second metal layer 110 in each capacitor unit with a first polarity, and the second connection structure 116 is used for coupling the second metal layer 110 in each capacitor unit with a second polarity, wherein the first polarity is opposite to the second polarity; a third connection structure 124 and a fourth connection structure 126 are provided in the interconnect layer of the second substrate 2; the third connection structure 124 has one end connected to the first connection structure 114 in the substrate and the other end exposed at a surface of the interconnect layer 12 remote from the substrate for connection to one of power or ground; the fourth connection structure 126 has one end connected to the second connection structure 116 in the substrate and the other end exposed at a surface of the interconnect layer 12 remote from the substrate 11 for connection to the other of power or ground.
In this embodiment, the third connection structure 124 in the interconnection layer 12 is connected to the first connection structure 114 in the substrate 11, and the first connection structure 114 is used to couple the second metal layer 110 in the first polarity in each capacitor unit, the fourth connection structure 126 in the interconnection layer is connected to the second connection structure 116 in the substrate 11, and the second connection structure 116 is used to couple the second metal layer 110 in the second polarity in each capacitor unit, so that the third connection structure 124 is exposed at an end of the interconnection layer 12 away from the surface of the substrate 11 and can be used to connect to a power supply, and the fourth connection structure 126 is exposed at an end of the interconnection layer 12 away from the surface of the substrate 11 and can be used to connect to ground.
In the electronic package, there may be a power line (power supply) and a ground line (ground) in the first substrate 1 for providing power to the first die 3 and/or the second die 4, and a decoupling capacitor may be provided to the power supply and the ground in the first substrate 1 to improve the power quality, see fig. 1 and 3, and in a further embodiment of the present application, a first connection structure 114 and a second connection structure are provided in the substrate 11 of the second substrate 2; the first connection structure 114 is used for coupling the second metal layer in the first polarity in each capacitor unit, and the second connection structure is used for coupling the second metal layer in the second polarity in each capacitor unit, wherein the first polarity is opposite to the second polarity; the first connection structure 114 and the second connection structure 116 penetrate the substrate of the second substrate, and the ends of the first connection structure 114 and the second connection structure 116 are exposed at the surface of the substrate 11 remote from the interconnect layer 12 for connection to power or ground, respectively, in the first substrate 1.
In this embodiment, the first connection structure 114 is used to couple the second metal layer 110 in the first polarity in each capacitor unit, the second connection structure 116 is used to couple the second metal layer 110 in the second polarity in each capacitor unit, and the ends of the first connection structure 114 and the second connection structure 116 are exposed on the surface of the substrate, which is far away from the interconnection layer 12, so that the first connection structure 114 can be connected to the power supply in the first substrate 1, and the second connection structure 116 can be connected to the ground in the first substrate 1, thereby improving the decoupling effect of the power supply in the first substrate 1 and improving the power supply quality in the first substrate.
The following describes a specific embodiment of the fabrication process according to the present application.
1. First, a high-precision cavity is formed on a first substrate by exposure, development and etching, see fig. 5.
2. And manufacturing a second substrate.
2.1 for the second substrate, a ceramic capacitor support sheet was first prepared.
Referring to fig. 7 and 8, firstly, mechanical drilling is performed on a ceramic film, the thickness of the ceramic film (dielectric layer) 9 is typically 10 to 20um, the via hole is typically about 60 to 70um, then the via hole is subjected to metal hole filling and a metal layer 10 is printed on the ceramic surface, and the thickness is about 10 um; and then stacking a second layer of ceramic film, mechanically drilling, then filling metal holes into the through holes, printing a metal layer on the second layer of ceramic film, and the like to finish the preparation of the multilayer ceramic and the metal layer, and finally sintering at high temperature.
Wherein, the multilayer ceramic film and the metal layer form a comb-shaped plane capacitor 111, which is led out to the surface through the metal in the via hole to be used as a ceramic capacitor supporting plate.
2.2 manufacturing an interposer 12 on the ceramic capacitor support sheet to complete the manufacture of the second substrate.
After the ceramic capacitor support sheet is prepared, low-cost polyimide is covered as a dielectric layer, and the thickness is about 7 um.
Etching a via hole on the dielectric layer to be connected with the top capacitor of the ceramic capacitor support sheet, wherein the aperture is generally about 10 um; electroplating the high-density copper circuit, wherein the typical line width and line distance is about 2um/2 um; and then covering the polyimide with low cost again as a dielectric layer, continuing etching the via hole and electroplating the high-density copper circuit until all the high-density circuit is manufactured, and finally cutting and separating the high-density circuit into a single second substrate.
2.3, the second substrate is assembled with the first substrate.
Referring to fig. 4, the first substrate 1 and the second substrate 2 are assembled using double-sided adhesive films. Copper pillars and solder balls are electroplated on the upper surfaces of the first substrate 1 and the second substrate 2.
In some examples, the copper pillar (bump) pitch of the first substrate 1 region is about 130um, and the diameter is about 70 um; the pitch of the copper pillars (bumps) 302 of the second substrate 2 is about 50um, the diameter is about 25um, and the heights are uniform.
And 2.4, packaging the electronic package.
Referring to fig. 4, the chip is flip-chip welded at the corresponding positions of the first substrate 1 and the second substrate 2, wherein the chip is also two kinds of pitch copper pillars and solder balls, the pitch of the copper pillars is about 130um and the diameter is about 70um in the region corresponding to the first substrate 1; the pitch of the copper pillars 302 of the second substrate 2 is about 50um, the diameter is about 25um, and the heights are uniform.
After welding, the communication between the two chips can be performed through the second substrate 2, and meanwhile, the power supply of the chips such as PHY chips is decoupled through the ceramic capacitor in the second substrate 2 via hole connection supporting sheet, so that decoupling paths are reduced, decoupling capacitor 11a is increased, power quality is improved, and frequency is improved.
The power supply of the chip is kept vertically connected with the capacitor in the second substrate 2, so that decoupling paths can be further reduced, the quality of the power supply is improved, and the frequency is improved.
In the case of connecting the capacitance in the second substrate 2 with the power and ground lines in the first substrate 1, the second substrate 2 may also be soldered in the cavity by solder balls 9 when embedded in the cavity of the first substrate 1 and connected with the power and ground lines in the first substrate 1 through vias in the first substrate 1, see fig. 9.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily conceivable by those skilled in the art within the technical scope of the present application should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (14)
1. A package substrate, the package substrate comprising: a substrate and an interconnect layer; the interconnection layer is arranged on the substrate, and comprises a first dielectric layer and a first metal layer which are alternately stacked, wherein the first metal layer comprises a metal connecting wire;
the substrate comprises second metal layers and second dielectric layers which are alternately arranged, wherein each two adjacent second metal layers and one second dielectric layer sandwiched between the two second metal layers form a capacitor unit, one second metal layer in each capacitor unit is used for being connected with a power supply, and the other second metal layer is used for being connected with the ground.
2. The package substrate of claim 1, wherein the second metal layer and the second dielectric layer are each parallel to the interconnect layer; alternatively, the second metal layer and the second dielectric layer are perpendicular to the interconnection layer, respectively.
3. The package substrate of claim 2, wherein the second metal layer and the second dielectric layer are perpendicular to the interconnect layer, respectively; the substrate is provided with grooves, the second metal layers and the second dielectric layers are alternately arranged along the side walls of the grooves towards the center of the grooves, and the grooves are filled with the second metal layers and the second dielectric layers.
4. The package substrate of claim 1, wherein the second metal layer and the second dielectric layer are planar or curved.
5. The package substrate according to any one of claims 1 to 4, wherein a first connection structure and a second connection structure are provided in the substrate; the first connection structure is used for coupling a second metal layer in a first polarity in each capacitor unit, and the second connection structure is used for coupling a second metal layer in a second polarity in each capacitor unit, wherein the first polarity is opposite to the second polarity.
6. The package substrate of claim 5, wherein a third connection structure and a fourth connection structure are disposed in the interconnect layer;
one end of the third connecting structure is connected with the first connecting structure in the substrate, and the other end of the third connecting structure is exposed on the surface of the interconnection layer far away from the substrate;
and one end of the fourth connecting structure is connected with the second connecting structure in the substrate, and the other end of the fourth connecting structure is exposed on the surface of the interconnection layer far away from the substrate.
7. The package substrate of claim 5, wherein the first and second connection structures pass through the substrate and ends of the first and second connection structures are exposed at a surface of the substrate remote from the interconnect layer.
8. The package substrate of any one of claims 1 to 4, wherein the material of the first dielectric layer is polyimide.
9. The package substrate according to any one of claims 1 to 4, wherein the material of the second dielectric layer is ceramic.
10. An electronic package, comprising: the semiconductor device comprises a first substrate, a second substrate, a first crystal grain and a second crystal grain; the second substrate is arranged in a cavity with an upward opening of the first substrate; the second substrate is the package substrate of any of the preceding claims 1-9;
the upper surface of the first substrate and the upper surface of the second substrate are provided with bumps; a part of pins of the first crystal grain are connected with the bumps on the first substrate, and the other part of pins are connected with the bumps on the second substrate; a part of pins of the second crystal grain are connected with the bumps on the first substrate, and the other part of pins are connected with the bumps on the second substrate;
at least a portion of the bumps on the second substrate are connected to first metal connection lines in the interconnection layer of the second substrate, so that the first die and the second die are interconnected by the first metal connection lines.
11. The electronic package of claim 10, wherein a width of the bump on the first substrate connected to the first die is greater than a width of the bump on the second substrate connected to the first die;
the width of the protruding blocks connected with the second crystal grains on the first substrate is larger than that of the protruding blocks connected with the second crystal grains on the second substrate.
12. The electronic package of claim 10, wherein a pitch between bumps on the first substrate connected to the first die is greater than a pitch between bumps on the second substrate connected to the first die;
the pitch between the bumps connected with the second crystal grain on the first substrate is larger than the pitch between the bumps connected with the second crystal grain on the second substrate.
13. The electronic package according to any one of claims 10 to 12, wherein a first connection structure and a second connection structure are provided in a substrate of the second substrate; the first connection structure is used for coupling a second metal layer in a first polarity in each capacitor unit, and the second connection structure is used for coupling a second metal layer in a second polarity in each capacitor unit, wherein the first polarity is opposite to the second polarity;
a third connection structure and a fourth connection structure are arranged in the interconnection layer of the second substrate;
one end of the third connecting structure is connected with the first connecting structure in the substrate, and the other end of the third connecting structure is exposed on the surface of the interconnection layer away from the substrate and is used for being connected with one of power supply or ground;
and one end of the fourth connecting structure is connected with the second connecting structure in the substrate, and the other end of the fourth connecting structure is exposed on the surface of the interconnection layer away from the substrate and is used for being connected with the other one of power supply and ground.
14. The electronic package according to any one of claims 10 to 12, wherein a first connection structure and a second connection structure are provided in a substrate of the second substrate; the first connection structure is used for coupling a second metal layer in a first polarity in each capacitor unit, and the second connection structure is used for coupling a second metal layer in a second polarity in each capacitor unit, wherein the first polarity is opposite to the second polarity;
the first connection structure and the second connection structure penetrate through the substrate of the second substrate, and the tail ends of the first connection structure and the second connection structure are exposed on the surface, away from the interconnection layer, of the substrate and are used for being connected with power supply or ground in the first substrate respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223417121.5U CN218957728U (en) | 2022-12-20 | 2022-12-20 | Packaging substrate and electronic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223417121.5U CN218957728U (en) | 2022-12-20 | 2022-12-20 | Packaging substrate and electronic package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218957728U true CN218957728U (en) | 2023-05-02 |
Family
ID=86139174
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202223417121.5U Active CN218957728U (en) | 2022-12-20 | 2022-12-20 | Packaging substrate and electronic package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN218957728U (en) |
-
2022
- 2022-12-20 CN CN202223417121.5U patent/CN218957728U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10283492B2 (en) | Laminated interposers and packages with embedded trace interconnects | |
| WO2022051103A1 (en) | Bonded structure with interconnect structure | |
| US8810008B2 (en) | Semiconductor element-embedded substrate, and method of manufacturing the substrate | |
| US11063017B2 (en) | Embedded organic interposer for high bandwidth | |
| KR101139147B1 (en) | Body having electronic component mounted thereon, method for manufacturing same, and interposer | |
| EP2234158A1 (en) | A three-dimensional electronics package | |
| US20040140538A1 (en) | Flex-based ic package construction employing a balanced lamination | |
| WO2021018014A1 (en) | Tsv-based multi-chip package structure and method for manufacturing same | |
| US8736074B2 (en) | Multi chip semiconductor device | |
| EP3745457A1 (en) | Semiconductor package having discrete antenna device | |
| KR100920039B1 (en) | Stacked semiconductor package and method of manufacturing thereof | |
| KR102134933B1 (en) | Wiring substrate and wiring substrate fabrication method | |
| JP2007109826A (en) | Wiring board, semiconductor device, and its manufacturing method | |
| KR20130054424A (en) | Method of making a multi-chip module having a reduced thickness and related devices | |
| US20080217748A1 (en) | Low cost and low coefficient of thermal expansion packaging structures and processes | |
| CN218957728U (en) | Packaging substrate and electronic package | |
| EP4199069A1 (en) | Microelectronic assemblies with glass substrates and thin film capacitors | |
| JP4028211B2 (en) | Semiconductor device | |
| KR101243304B1 (en) | Interposer and method for manufacturing thereof | |
| CN216251116U (en) | Expandable millimeter wave phased array unit and active antenna array surface | |
| CN116053252A (en) | Packaging substrate and electronic package | |
| US11219120B2 (en) | Stress relief opening for reducing warpage of component carriers | |
| CN114122675A (en) | Expandable millimeter wave phased array unit, preparation method and active antenna array surface | |
| TWI615933B (en) | Semiconductor device and method of manufacturing semiconductor device | |
| CN113299626B (en) | Conductive assembly for multi-chip packaging and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |