CN218866065U - Fault abnormal state holding circuit, device and robot - Google Patents
Fault abnormal state holding circuit, device and robot Download PDFInfo
- Publication number
- CN218866065U CN218866065U CN202220338358.5U CN202220338358U CN218866065U CN 218866065 U CN218866065 U CN 218866065U CN 202220338358 U CN202220338358 U CN 202220338358U CN 218866065 U CN218866065 U CN 218866065U
- Authority
- CN
- China
- Prior art keywords
- circuit
- fault
- signal
- power supply
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Emergency Protection Circuit Devices (AREA)
Abstract
The application belongs to the technical field of power utilization safety protection, and particularly relates to a fault abnormal state holding circuit, a device and a robot, wherein the fault abnormal state holding circuit samples output current of a power supply through a current sampling circuit to generate a current sampling signal, a fault detection circuit generates a fault detection signal and a fault detection latch signal according to the current sampling signal, the fault holding circuit holds the fault detection signal, a control circuit generates a reset control signal according to the fault detection latch signal, and a fault release circuit is connected with or disconnected from the fault holding circuit and a power supply grounding end according to the reset control signal, so that when abnormal faults such as overcurrent and the like occur in power supply of the power supply, the fault signals are reported in real time to carry out safe power failure processing on a system, meanwhile, the fault signals are kept, troubleshooting is facilitated, the fault abnormal state is released after the fault is completely cleared, and potential safety hazards of power utilization are effectively reduced.
Description
Technical Field
The application belongs to the technical field of power consumption safety protection, and particularly relates to a fault abnormal state holding circuit, a fault abnormal state holding device and a robot.
Background
The traditional robot scheme is that a Hall current detection chip integrated with an error reporting function is used for monitoring power output current (such as battery discharge current), when current overcurrent is detected, an error reporting pin outputs an error reporting signal to control a power switch, and when different overcurrent thresholds are required to be set under different application environments, corresponding circuit parameters and chip models are required to be modified, so that the scheme is high in cost and poor in replaceability, the threshold of the overcurrent current cannot be set randomly under the condition that the model of the chip is not changed, the error reporting signal can be output only when the maximum current specified by the chip is exceeded, and the application flexibility is not high enough; meanwhile, error reporting signals for controlling the power switch are transient, so that troubleshooting and removal of faults are not facilitated, and potential safety hazards exist.
Therefore, the conventional technical scheme has the defects that the power supply fault abnormal state is short in maintenance time, the potential safety hazard of power utilization and the limitation of an applicable scene are not facilitated to be eliminated, and the flexibility is poor.
Disclosure of Invention
An object of the application is to provide a trouble abnormal state holding circuit, device and robot, aim at solving the power supply trouble abnormal state that exists among the traditional technical scheme hold time short, be unfavorable for troubleshooting, lead to having power consumption potential safety hazard and be suitable for the scene limitation, the poor problem of flexibility.
A first aspect of an embodiment of the present application provides a fault abnormal state holding circuit, including:
the current sampling circuit is used for sampling the output current of the power supply and generating a current sampling signal;
the fault detection circuit is connected with the current sampling circuit and used for generating a fault detection signal and a fault detection latching signal according to the current sampling signal;
a fault holding circuit connected to the current sampling circuit and the fault detection circuit for holding the fault detection signal and the fault detection latch signal;
the control circuit is connected with the fault detection circuit and used for generating a reset control signal according to the fault detection latch signal;
and the fault release circuit is connected with the fault holding circuit and the control circuit and is used for connecting or disconnecting the fault holding circuit with a power supply grounding terminal according to the reset control signal.
In one embodiment, the fault abnormal state holding circuit further includes:
the power supply switch circuit is connected with the control circuit and the power supply and is used for switching off or switching on the power supply of the power supply according to a power supply control signal;
the control circuit is further configured to generate the power supply control signal based on the fault detection latch signal.
In one embodiment, the fault abnormal state holding circuit further includes:
the voltage monitoring circuit is connected with the power supply and the control circuit and is used for sampling the output voltage of the power supply to generate a voltage monitoring signal;
the control circuit is further configured to generate the power supply control signal according to the fault detection latch signal or the voltage monitoring signal to control turning off or turning on the power supply of the power supply.
In one embodiment, the fault abnormal state holding circuit further includes:
and the hardware protection circuit is connected with the fault detection circuit and the power supply and is used for switching on or switching off the power supply for supplying power to a post-stage circuit according to the fault detection latching signal.
In one embodiment, the fault detection circuit includes:
a reference unit for generating a reference signal according to the second voltage signal;
the comparison unit is connected with the reference unit, the current sampling circuit and the fault holding circuit and is used for generating the fault detection signal and an initial fault detection signal according to the reference signal and the current sampling signal;
and the fault latch unit is connected with the comparison unit and the control circuit and is used for generating the fault detection latch signal according to the initial fault detection signal.
In one embodiment, the comparing unit includes: the circuit comprises a comparator, a first capacitor, a second capacitor, a third capacitor, a first resistor, a second resistor and a third resistor; the positive input end of the comparator, the first end of the first capacitor, and the first end of the first resistor are connected to the fault holding circuit and the current sampling circuit, the second end of the first capacitor and the second end of the first resistor are connected to a power ground, the positive power terminal of the comparator and the first end of the second capacitor are connected to a first voltage signal, the negative power terminal of the comparator and the second end of the second capacitor are connected to the power ground, the output end of the comparator is connected to the fault latch unit and the first end of the second resistor, the second end of the second resistor is connected to the first end of the third capacitor, the first end of the third resistor, and the fault holding circuit, the second end of the third capacitor and the second end of the third resistor are connected to the first voltage signal, and the second end of the third capacitor and the second end of the third resistor are also connected to the fault holding circuit.
In one embodiment, the fail latch unit includes: a fourth resistor and a fifth resistor; the first end of the fifth resistor is connected to a third voltage signal, the second end of the fifth resistor and the first end of the fourth resistor are connected to the comparison unit, and the second end of the fourth resistor is connected to the control circuit.
In one embodiment, the fault holding circuit comprises: the sixth resistor, the first triode and the first diode; the base electrode of the first triode and the emitting electrode of the first triode are connected with the fault detection circuit, the collector electrode of the first triode is connected with the first end of the sixth resistor, the second end of the sixth resistor and the anode of the first diode are connected with the fault release circuit, and the cathode of the first diode is connected with the current sampling circuit and the fault detection circuit.
A second aspect of the embodiments of the present application provides a malfunction abnormal state holding apparatus including a malfunction abnormal state holding circuit as described in any one of the above.
A third aspect of embodiments of the present application provides a robot including the malfunction abnormal state maintaining circuit according to any one of the above.
The embodiment of the application provides a trouble abnormal state holding circuit, it samples in order to generate current sampling signal through the output current of current sampling circuit to the power, and the fault detection circuit basis fault detection signal and fault detection latch signal are generated to current sampling signal, and the fault holding circuit keeps the fault detection signal with fault detection latch signal, control circuit basis fault detection latch signal generates the control signal that resets, and fault release circuit basis reset control signal intercommunication or disconnection fault holding circuit and power earthing terminal's connection to the realization when power supply appears overflowing isosexual fault, reports the fault signal in real time and carries out the safe outage processing to the system, can also keep the fault signal simultaneously, is favorable to the troubleshooting to get rid of the trouble, only after the complete troubleshooting, can restart and restore normally, has effectively reduced the power consumption safety risk.
Drawings
Fig. 1 is a schematic structural diagram of a fault abnormal state holding circuit according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a fault abnormal state holding circuit according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a fault abnormal state holding circuit according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a fault abnormal state holding circuit according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a fault abnormal state holding circuit according to an embodiment of the present application;
fig. 6 is a schematic diagram of an exemplary circuit of a fault abnormal state holding circuit according to an embodiment of the present application.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Fig. 1 shows a schematic structural diagram of a fault abnormal state holding circuit provided in an embodiment of the present application, and for convenience of description, only the parts related to this embodiment are shown, and details are as follows:
a first aspect of an embodiment of the present application provides a fault abnormal state holding circuit, including: current sampling circuit 10, fault detection circuit 20, fault holding circuit 30, control circuit 40, and fault release circuit 50, wherein:
a current sampling circuit 10 for sampling an output current of the power supply 01 to generate a current sampling signal; the fault detection circuit 20 is connected with the current sampling circuit 10 and used for generating a fault detection signal and a fault detection latch signal according to the current sampling signal; a fault holding circuit 30 connected to the current sampling circuit 10 and the fault detection circuit 20, for holding the fault detection signal and the fault detection latch signal; a control circuit 40 connected to the failure detection circuit 20 for generating a reset control signal based on the failure detection latch signal; and a fault release circuit 50 connected to the fault holding circuit 30 and the control circuit 40, for connecting or disconnecting the fault holding circuit 30 to the power ground terminal according to the reset control signal.
In a specific implementation, the power supply 01 may be a battery, such as a dry battery, a lead-acid battery, a nickel-cadmium battery, a nickel-lithium ion battery, or the like, and may also be another power supply capable of outputting current to supply power to a subsequent load.
The current sampling circuit 10 samples the output current of the power supply 01 to generate a current sampling signal and transmits the current sampling signal to the fault detection circuit 20. The fault detection circuit 20 judges whether fault abnormality such as overcurrent occurs in the output current of the power supply 01 according to the current sampling signal, correspondingly generates a fault detection signal and a fault detection latch signal, the fault detection signal is fed back to the fault holding circuit 30, the fault detection latch signal is directly output to the control circuit 40, the control circuit 40 generates a reset control signal according to the fault detection latch signal and transmits the reset control signal to the fault release circuit 50, and the fault release circuit 50 is connected with or disconnected from the fault holding circuit 30 and the power supply grounding end according to the reset control signal, so that the fault holding circuit 30 maintains the current sampling signal, further the fault detection signal is maintained, troubleshooting and removal of faults are facilitated, the power utilization risk is reduced, and the power utilization safety is improved.
The fault detection signal comprises a first level fault detection signal and a second level fault detection signal, the fault detection latch signal comprises a first level fault detection latch signal and a second level fault detection latch signal, and the reset control signal comprises a first level reset control signal and a second level reset control signal. Optionally, the first level is a high level, and the second level is a low level.
When the power supply 01 supplies power normally, the fault detection circuit 20 generates a high-level fault detection signal and a high-level fault detection latch signal according to the current sampling signal, the high-level fault detection signal enables the fault holding circuit 30 to be disconnected from the first voltage signal, so that the current sampling signal input to the fault detection circuit 20 is not affected, the high-level fault detection latch signal is fed back to the control circuit 40, the control circuit 40 can generate a low-level reset control signal or generate a high-level reset control signal according to the high-level fault detection latch signal or be idle without responding, and the fault release circuit 50 can be used for connecting or disconnecting the fault holding circuit 30 with the ground terminal of the power supply; when overcurrent fault occurs during power supply of a power supply 01, a fault detection circuit 20 generates a low-level fault detection signal and a low-level fault detection latch signal according to a current sampling signal, the low-level fault detection signal enables a fault holding circuit 30 to conduct a first voltage signal and output the first voltage signal to the fault detection circuit 20, the low-level fault detection latch signal is fed back to a control circuit 40, the control circuit 40 generates a low-level reset control signal according to the low-level fault detection latch signal, a fault release circuit 50 disconnects the fault holding circuit 30 from a power ground terminal according to the low-level reset control signal, and the fault holding circuit 30 can keep the level of the current sampling signal input to the fault detection circuit 20 by combining the first voltage signal conducted by the fault holding circuit 30, so that the fault abnormal state at the moment is maintained, fault is conveniently checked and removed, and the electric safety risk is reduced.
When the fault is eliminated, the reset restart signal can be triggered through user operation, the control circuit 40 generates a high-level reset control signal according to the reset restart signal, the fault release circuit 50 is controlled to connect the fault holding circuit 30 with the power supply ground terminal, the first voltage signal is connected to the power supply ground terminal, the level of the current sampling signal is reduced, so that the abnormal fault state is released and removed, and the power supply recovers to normal power supply after the fault is removed.
According to the embodiment of the application, through the fault abnormal state maintaining circuit, when abnormal faults such as overcurrent and the like occur in power supply (such as a battery), a fault signal can be stably maintained, fault removal is facilitated, normal recovery is realized only after complete fault removal, and potential safety hazards and risks of power utilization are effectively reduced.
In one embodiment, referring to fig. 2, the abnormal fault condition holding circuit further includes: a power supply switch circuit 60; wherein the content of the first and second substances,
a power supply switch circuit 60 connected to the control circuit 40 and the power supply 01, for turning off or turning on the power supply of the power supply 01 according to the power supply control signal; the control circuit 40 is further configured to generate the power supply control signal according to the failure detection latch signal.
In a specific implementation, the power supply control signal includes a low level power supply control signal and a high level power supply control signal. When the power supply 01 supplies power normally, the control circuit 40 judges that the power supply of the power supply 01 is normal according to the high-level fault detection latch signal, and correspondingly generates a low-level power supply control signal to control and keep the power supply of the power supply 01 to a system; when the power supply of the power supply 01 has an overcurrent fault, the control circuit 40 judges that the output current of the power supply 01 has an abnormal fault such as overcurrent according to the low-level fault detection latch signal, and correspondingly generates a high-level power supply control signal to control the power supply of the power supply 01 to the system to be cut off. The power supply switch circuit 60 is also connected to the power supply 01 and a subsequent system, and serves as a switch for the power supply of the power supply 01 to the system, and when abnormal faults such as overcurrent occur in the output current of the power supply 01, the power supply of the power supply 01 to the system is timely turned off through the power supply switch 01, so that the system is protected from overcurrent damage.
According to the embodiment of the application, when the power supply (such as a battery) supplies power and abnormal faults such as overcurrent occur, the fault signal can be reported in real time to perform safe power-off processing on the system, the safe reliability of power supply 01 is guaranteed, meanwhile, the fault signal can be kept, and fault removal is facilitated.
In one embodiment, referring to fig. 3, the abnormal fault condition holding circuit further includes: a voltage monitoring circuit 70; wherein the content of the first and second substances,
a voltage monitoring circuit 70 connected to the power supply 01 and the control circuit 40, for sampling the output voltage of the power supply 01 to generate a voltage monitoring signal; the control circuit 40 is further configured to generate a power supply control signal according to the fault detection latch signal or the voltage monitoring signal to control turning off or on the power supply of the power supply 01.
In specific implementation, the voltage and current that electronic components in a system and a subsequent circuit (for example, a subsequent PCBA board) that need to use electricity can bear are limited, and if the voltage and current exceed the limit, high-temperature heating or even burning out will occur to cause fire and other adverse effects. In order to better protect and avoid potential safety hazards caused by failure of a power supply control system or fault of a rear-stage PCBA due to abnormal power supply fault of a power supply 01 (such as a battery), double monitoring of a current sampling circuit 10 and a voltage monitoring circuit 70 is adopted, battery voltage monitoring is carried out through a control circuit 40 in combination with a current sampling result, battery discharge voltage is also sampled through a hardware circuit (namely the voltage monitoring circuit 70), when the battery discharge voltage exceeds a set range, battery discharge is immediately stopped, double protection is carried out, damage to the system and the rear-stage PCBA due to overcurrent or overvoltage of the battery is avoided, and the potential safety hazards are further provided, and power utilization risks are reduced.
In one embodiment, referring to fig. 4, the fault abnormal state holding circuit further includes: a hardware protection circuit 80; wherein the content of the first and second substances,
and the hardware protection circuit 80 is connected with the fault detection circuit 20 and the power supply 01 and is used for switching on or switching off the power supply of the power supply 01 to the subsequent circuit according to the fault detection latch signal.
In the specific implementation, taking the power supply 01 as a battery as an example for explanation, through real-time monitoring of the battery discharge current, when the battery discharge current is abnormal, for example, the battery discharge current exceeds a preset overcurrent threshold, the fault detection circuit 20 outputs a low-level fault detection latch signal, the hardware protection circuit 80 immediately turns off the power supply switch of the subsequent circuit after detecting the low-level fault detection latch signal, and meanwhile, the control circuit 40 also turns off the battery discharge path after detecting the low-level fault detection latch signal, so as to achieve the effect of protecting the battery, the power control system and the subsequent PCBA board.
In one embodiment, referring to fig. 5, the fault detection circuit 20 includes: a reference unit 201, a comparison unit 202, and a fail latch unit 203; wherein the content of the first and second substances,
a reference unit 201 for generating a reference signal according to the second voltage signal; a comparing unit 202 connected to the reference unit 201, the current sampling circuit 10 and the fault holding circuit 30, for generating a fault detection signal and an initial fault detection signal according to the reference signal and the current sampling signal; and a failure latch unit 203 connected to the comparison unit 202 and the control circuit 40 for generating a failure detection latch signal according to the initial failure detection signal.
In a specific implementation, the reference unit 201 generates a reference signal according to the second voltage signal, and the reference signal is used as an input signal of the positive input terminal of the comparison unit 202. The current sampling signal is used as an input signal of the negative input terminal of the comparison unit 202, and the comparison unit 202 generates a high-level fault detection signal and a high-level fault detection latch signal or generates a low-level fault detection signal and a low-level fault detection latch signal according to the reference signal and the current sampling signal. The high-level fault detection signal causes the fault holding circuit 30 to disconnect the first voltage signal from the negative input terminal of the comparing unit 202, and the low-level fault detection signal causes the fault holding circuit 30 to connect the first voltage signal to the negative input terminal of the comparing unit 202.
Optionally, in one embodiment, referring to fig. 6, the comparing unit 202 includes: the circuit comprises a comparator U127, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first resistor R1, a second resistor R2 and a third resistor R3; a positive input terminal + IN of the comparator U127 is connected to the reference unit 201, a negative input terminal-IN of the comparator U127, a first terminal of the first capacitor C1, and a first terminal of the first resistor R1 are connected to the fault holding circuit 30 and the current sampling circuit 10, a second terminal of the first capacitor C1 and a second terminal of the first resistor R1 are connected to a power ground terminal, a positive power terminal V + of the comparator U127 and a first terminal of the second capacitor C2 are connected to the first voltage signal, a negative power terminal V-of the comparator U127 and a second terminal of the second capacitor C2 are connected to the power ground terminal, an output terminal VOUT of the comparator U127 is connected to the fault latch unit 203 and a first terminal of the second resistor R2, a second terminal of the second resistor R2 is connected to a first terminal of the third capacitor C3, a first terminal of the third resistor R3, and the fault holding circuit 30, a second terminal of the third capacitor C3 and a second terminal of the third resistor R3 are connected to the first voltage signal, and a second terminal of the third capacitor C3 and a second terminal of the third resistor R3 are also connected to the fault holding circuit 30.
In specific implementation, the second capacitor C2 may be replaced by a capacitor bank formed by connecting a plurality of capacitors in parallel, and the capacitance value parameter is adjusted to meet the specific application requirement. Optionally, the first voltage signal is MAIN _3V3, and the voltage value thereof is 3.3V. The positive input terminal + IN of the comparator U127 is the positive input terminal of the comparing unit 202, and the negative input terminal-IN of the comparator U127 is the negative input terminal of the comparing unit 202. Optionally, the comparator U127 uses a single-path general low-voltage comparator LMV331.
Alternatively, in one embodiment, referring to fig. 6, the fail latch unit 203 includes: a fourth resistor R4 and a fifth resistor R5; a first end of the fifth resistor R5 is connected to the third voltage signal, a second end of the fifth resistor R5 and a first end of the fourth resistor R4 are connected to the comparing unit 202, and a second end of the fourth resistor R4 is connected to the control circuit 40.
In specific implementation, the third voltage signal, the second voltage signal and the first voltage signal may be the same as MAIN _3V3, or may be different from each other, and are designed according to specific requirements.
Optionally, referring to fig. 6, the reference unit 201 includes: a resistor R7, a resistor R8, a capacitor C4 and a capacitor C5; the first end of the resistor R7 and the first end of the capacitor C5 are connected to a second voltage signal (MAIN _3V 3), the second end of the capacitor C5 is connected to the power ground, the second end of the resistor R7 is connected to the first end of the resistor R8 and the first end of the capacitor C4, and the second end of the resistor R8 and the second end of the capacitor C4 are connected to the power ground.
In specific implementation, after the voltage value of the second voltage signal is set, the reference signal value generated by the reference unit 201 can be adjusted by adjusting the ratio between the resistor R7 and the resistor R8, so that the use flexibility is high, and different overcurrent thresholds (i.e., reference signal values) can be set according to different application occasions without redesigning a circuit or replacing the circuit as a whole.
In one embodiment, referring to fig. 6, the fail-safe circuit 30 includes: a sixth resistor R6, a first triode U130 and a first diode D62; the base of the first triode U130 and the emitter of the first triode U130 are connected to the fault detection circuit 20, the collector of the first triode U130 is connected to the first end of the sixth resistor R6, the second end of the sixth resistor R6 and the anode of the first diode D62 are connected to the fault release circuit 50, and the cathode of the first diode D62 is connected to the current sampling circuit 10 and the fault detection circuit 20.
In one embodiment, the first diode D62 has a low turn-on voltage and a fast switching characteristic. Optionally, the first transistor U130 is a PNP transistor, and other switching tubes with the same or equivalent functions are also protected by this application.
In one embodiment, referring to fig. 6, the fault release circuit 50 includes: a capacitor C6, a resistor R9, a resistor R10 and a first field effect transistor Q15; the first end of the resistor R10 is connected to the control circuit 40, the second end of the resistor R10 is connected to the first end of the resistor R9, the first end of the capacitor C6, and the gate of the first fet Q15, the second end of the resistor R9, the second end of the capacitor C6, and the source of the first fet Q15 are connected to the power ground, and the drain of the first fet Q15 is connected to the second end of the sixth resistor R6 in the fault holding circuit 30 and the anode of the first diode D62.
Optionally, in this embodiment, the first field effect transistor Q15 is an N-channel MOS transistor. In other embodiments, the first fet Q15 may also be a switching transistor, such as an NPN transistor, having the same or equivalent function as the first fet Q15.
In one embodiment, referring to fig. 6, the current sampling circuit 10 includes: the current sensing circuit comprises a current sensing chip U2, a capacitor C7, a capacitor C8, a diode D0, a resistor R11 and a resistor R12; the positive input end (IP 1+ and IP2 +) of the current sensing chip U2 is connected with an output current signal (BYT _ OUT _ P) of the power supply 01, the negative output end (IP 1-and IP 2-) of the current sensing chip U2 is connected with a supply voltage signal (24 VIN) output by the power supply 01, a ground terminal GND of the current sensing chip U2 is connected with a power supply ground terminal, an output terminal VIOUT of the current sensing chip U2 is connected with a first terminal of a resistor R12, a second terminal of the resistor R12 and a first terminal of a capacitor C8 are connected with a first terminal of a resistor R11, a second terminal of the resistor R11 is connected with an anode of a diode D0, a cathode of the diode D0 is connected with a cathode of a first diode D62 and a negative input terminal-IN of a comparator U127, a power supply terminal VCC of the current sensing chip U2 is connected with a first terminal of a capacitor C7 and connected with a fourth voltage signal, and a second terminal of the capacitor C7 is connected with the power supply ground terminal.
The diode D0 can prevent the signal from flowing backward to the current sampling circuit 10 after the fault holding circuit 30 turns on the first voltage signal, thereby ensuring the accurate reliability of the power supply fault abnormality detection of the power supply 01.
Optionally, the fourth voltage signal is the same as the first voltage signal, and both are MAIN _3V3.
Optionally, the current sensing chip U2 adopts a single-chip hall current sensor, and an output current signal (BYT _ OUT _ P) of the power supply 01 passes through the single-chip hall current sensor, and is subjected to electromagnetic induction, i.e., signal processing, and outputs a current sampling signal, thereby realizing detection of the discharge current of the power supply 01.
Alternatively, the first diode D62 and the diode D0 may be replaced by schottky diodes, such as a common cathode schottky diode of type BAT 54C.
In specific implementation, the control circuit 40 is a Micro Controller Unit (MCU), which is a chip-level computer, and has functions of data processing, analyzing, determining, storing, and calculating, and can meet application requirements for different combination controls in different application occasions.
The operation principle of the abnormal fault state holding circuit will be briefly described below with reference to fig. 6:
the resistor R7 and the resistor R8 are connected IN series for voltage division, different reference signal values are obtained by adjusting the resistance values of the resistor R7 and the resistor R8 to adjust the voltage division value, and the reference signal is used as an input signal of the positive input end + IN of the comparator U127; the current sampling signal is transmitted to a negative input terminal-IN of the comparator U127 as an input signal of the negative input terminal-IN of the comparator U127; the fifth resistor R5 is a pull-up resistor of the output terminal VOUT of the comparator U127.
When the output current of the power supply 01 (such as a battery) is normal and the circuit works normally, the reference signal of the positive input terminal + IN of the comparator U127 is greater than the current sampling signal of the negative input terminal-IN of the comparator U127, at this time, the output terminal VOUT of the comparator U127 outputs a high-level initial fault detection signal by default, and the high-level fault detection signal is output from the second terminal of the second resistor R2 to the base of the first triode U130, so that the first triode U130 is cut off according to the high-level fault detection signal, and at this time, the power is supplied normally.
When the output current of the power supply 01 has an overcurrent fault, the reference signal of the positive input terminal + IN of the comparator U127 is smaller than the current sampling signal of the negative input terminal-IN of the comparator U127, and at this time, the output terminal VOUT of the comparator U127 outputs a default low-level initial fault detection signal, and outputs the low-level fault detection signal from the second terminal of the second resistor R2 to the base of the first transistor U130, so that the first transistor U130 conducts the first voltage signal (MAIN _3V 3) according to the low-level fault detection signal, the first voltage signal (MAIN _3V 3) flows through the first transistor U130, the sixth resistor R6, and the first diode D62 to pull up the voltage of the negative input terminal-IN of the comparator U127, at this time, the voltage of the negative input terminal-IN of the comparator U127 is always greater than the voltage of the positive input terminal + IN of the comparator U127, the comparator U127 always outputs a low level, so that the fault detection circuit 20 keeps outputting a low-level fault detection signal and a low-level fault detection latch signal (IBUS-FO), the low-level fault detection latch signal (IBUS-FO) is output from the second terminal of the fourth resistor R4 to the control circuit 40, the MCU IN the control circuit 40 generates a high-level power supply control signal according to the low-level fault detection latch signal (IBUS-FO), the field-effect transistor U3 IN the power supply switch circuit 60 cuts off power supply to the system according to the high-level power supply control signal, and the purpose of shutting off a battery power supply path to protect a battery, the system, and the like is achieved; meanwhile, the MUC IN the control circuit 40 generates a low-level reset control signal (BST-ACS 711) according to the low-level fault detection latch signal, and the first fet Q15 disconnects the anode terminal of the first diode D62 from the power ground terminal, that is, disconnects the fault holding circuit 30 from the power ground terminal, and maintains the level of the current sampling signal input to the negative input terminal-IN of the comparator U127, so as to achieve the purpose of holding the fault signal (that is, keeping the fault detection circuit 20 output the low-level fault detection signal and the low-level fault detection latch signal), so as to remove the fault.
When the fault is removed, the MCU generates a high-level reset control signal (BST-ACS 711) according to a reset restart signal generated by a user operation, the first fet Q15 is turned on according to the high-level reset control signal (BST-ACS 711), and connects the anode terminal of the first diode D62 to the power ground, that is, connects the fault holding circuit 30 to the power ground, and pulls down the voltage at the negative input terminal-IN of the comparator U127, so that the output terminal VOUT of the comparator U127 is restored to an output high level at this time, and the low-level fault detection signal is released, that is, the abnormal fault state is released.
The fault abnormal state holding circuit of the embodiment of the application can not only realize real-time reporting of the fault signal, but also can hold the fault signal (such as a low-level fault detection signal and a low-level fault detection latch signal), is favorable for fault elimination, and can be recovered to be normal only by restarting after completely eliminating the fault; in addition, the overcurrent threshold (namely the reference signal) can be set by setting the resistor voltage division limit value, the use flexibility is higher, different overcurrent thresholds can be set according to different application occasions, and a hardware circuit is constructed by using common components, so that the selection is flexible, the cost is low, the reliability and the practicability of overcurrent protection are improved, and the safety of the product is also well improved.
A second aspect of the embodiments of the present application provides a malfunction abnormal state holding apparatus including a malfunction abnormal state holding circuit as described in any one of the above.
According to the fault abnormal state holding device, through the fault abnormal state holding circuit, when abnormal faults such as overcurrent occur when power is supplied by a power supply (such as a battery), a fault signal can be reported in real time to perform safe power failure processing on a system, meanwhile, the fault signal can be held, fault removal is facilitated, only after the fault is completely removed, the system can be recovered to be normal, and potential safety hazards and risks of power utilization are effectively reduced; meanwhile, the overcurrent protection reliability and the practicability are realized, and the cost is low.
A third aspect of embodiments of the present application provides a robot including a malfunction abnormal state maintaining circuit as claimed in any one of the above.
The robot in the embodiment of the application can report the fault signal in real time to perform safe power failure processing on a system when the power supply (such as a battery) supplies power and has abnormal faults such as overcurrent and the like through the fault abnormal state maintaining circuit, can maintain the fault signal at the same time, is favorable for removing the fault, can recover to be normal only after the fault is completely removed, and effectively reduces the potential safety hazard and risk of power utilization; meanwhile, the overcurrent protection reliability and the practicability are realized, and the cost is saved.
It will be clear to those skilled in the art that, for convenience and simplicity of description, the foregoing functional circuits, units and modules are merely illustrated in terms of their division, and in practical applications, the foregoing functional distribution may be implemented by different functional circuits, units and modules as needed, that is, the internal structure of the device may be divided into different functional circuits, units and modules to implement all or part of the above described functions. In addition, specific names of the functional circuits, units and modules are only used for distinguishing one functional circuit from another, and are not used for limiting the protection scope of the present application.
In the above embodiments, the description of each embodiment has its own emphasis, and reference may be made to the related description of other embodiments for parts that are not described or recited in any embodiment.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A malfunction abnormal state holding circuit, characterized by comprising:
the current sampling circuit is used for sampling the output current of the power supply and generating a current sampling signal;
the fault detection circuit is connected with the current sampling circuit and used for generating a fault detection signal and a fault detection latching signal according to the current sampling signal;
a fault holding circuit connected to the current sampling circuit and the fault detection circuit for holding the fault detection signal and the fault detection latch signal;
the control circuit is connected with the fault detection circuit and used for generating a reset control signal according to the fault detection latch signal;
and the fault release circuit is connected with the fault holding circuit and the control circuit and is used for connecting or disconnecting the fault holding circuit with a power supply grounding end according to the reset control signal.
2. The malfunction abnormal state holding circuit according to claim 1, wherein the malfunction abnormal state holding circuit further comprises:
the power supply switch circuit is connected with the control circuit and the power supply and is used for switching off or switching on the power supply of the power supply according to a power supply control signal;
the control circuit is further configured to generate the power supply control signal based on the fault detection latch signal.
3. The malfunction abnormal state holding circuit according to claim 2, wherein the malfunction abnormal state holding circuit further comprises:
the voltage monitoring circuit is connected with the power supply and the control circuit and is used for sampling the output voltage of the power supply to generate a voltage monitoring signal;
the control circuit is further configured to generate the power supply control signal according to the fault detection latch signal or the voltage monitoring signal to control turning off or turning on the power supply of the power supply.
4. The malfunction abnormal state holding circuit according to claim 1, further comprising:
and the hardware protection circuit is connected with the fault detection circuit and the power supply and is used for switching on or switching off the power supply to supply power to the post-stage circuit according to the fault detection latch signal.
5. The fault abnormal state holding circuit according to claim 1, wherein the fault detection circuit comprises:
a reference unit for generating a reference signal according to the second voltage signal;
the comparison unit is connected with the reference unit, the current sampling circuit and the fault holding circuit and is used for generating the fault detection signal and an initial fault detection signal according to the reference signal and the current sampling signal;
and the fault latch unit is connected with the comparison unit and the control circuit and used for generating the fault detection latch signal according to the initial fault detection signal.
6. The malfunction abnormal state holding circuit according to claim 5, wherein the comparison unit includes: the circuit comprises a comparator, a first capacitor, a second capacitor, a third capacitor, a first resistor, a second resistor and a third resistor; wherein the content of the first and second substances,the positive input end of the comparator is connected with the reference unit, the negative input end of the comparator, the first end of the first capacitor and the first end of the first resistor are connected with the fault holding circuit and the current sampling circuit, the second end of the first capacitor and the second end of the first resistor are connected with the power grounding end, and the positive power source end of the comparator and the first end of the second capacitor are connected with a first voltage signal ， The negative power supply end of the comparator and the second end of the second capacitor are connected with a power supply grounding end, the output end of the comparator is connected with the fault latch unit and the first end of the second resistor, the second end of the second resistor is connected with the first end of the third capacitor, the first end of the third resistor and the fault holding circuit, the second end of the third capacitor and the second end of the third resistor are connected with the first voltage signal, and the second end of the third capacitor and the second end of the third resistor are also connected with the fault holding circuit.
7. The malfunction abnormal state retaining circuit according to claim 5, wherein the malfunction latch unit includes: a fourth resistor and a fifth resistor; wherein, the first end of the fifth resistor is connected with a third voltage signal ， And the second end of the fifth resistor and the first end of the fourth resistor are connected with the comparison unit, and the second end of the fourth resistor is connected with the control circuit.
8. The fault abnormal state retention circuit of claim 1, wherein the fault retention circuit comprises: the sixth resistor, the first triode and the first diode; the base electrode of the first triode and the emitting electrode of the first triode are connected with the fault detection circuit, the collector electrode of the first triode is connected with the first end of the sixth resistor, the second end of the sixth resistor and the anode of the first diode are connected with the fault release circuit, and the cathode of the first diode is connected with the current sampling circuit and the fault detection circuit.
9. A malfunction abnormal state holding apparatus characterized in that the malfunction abnormal state holding apparatus comprises a malfunction abnormal state holding circuit according to any one of claims 1 to 8.
10. A robot characterized by comprising the malfunction abnormal state holding circuit according to any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220338358.5U CN218866065U (en) | 2022-02-18 | 2022-02-18 | Fault abnormal state holding circuit, device and robot |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220338358.5U CN218866065U (en) | 2022-02-18 | 2022-02-18 | Fault abnormal state holding circuit, device and robot |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218866065U true CN218866065U (en) | 2023-04-14 |
Family
ID=87364444
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220338358.5U Active CN218866065U (en) | 2022-02-18 | 2022-02-18 | Fault abnormal state holding circuit, device and robot |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN218866065U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116505474A (en) * | 2023-05-05 | 2023-07-28 | 无锡市稳先微电子有限公司 | Battery protection circuit and electronic device |
| CN117131459A (en) * | 2023-10-26 | 2023-11-28 | 苏州四方杰芯电子科技有限公司 | Power-on reset circuit abnormality detection analysis method and system |
-
2022
- 2022-02-18 CN CN202220338358.5U patent/CN218866065U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116505474A (en) * | 2023-05-05 | 2023-07-28 | 无锡市稳先微电子有限公司 | Battery protection circuit and electronic device |
| CN116505474B (en) * | 2023-05-05 | 2023-10-24 | 无锡市稳先微电子有限公司 | Battery protection circuit and electronic device |
| CN117131459A (en) * | 2023-10-26 | 2023-11-28 | 苏州四方杰芯电子科技有限公司 | Power-on reset circuit abnormality detection analysis method and system |
| CN117131459B (en) * | 2023-10-26 | 2024-01-26 | 苏州四方杰芯电子科技有限公司 | Power-on reset circuit abnormality detection analysis method and system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN218866065U (en) | Fault abnormal state holding circuit, device and robot | |
| WO2018076794A1 (en) | Redundant backup control circuit of battery management system | |
| CN103490374A (en) | Mass production test device and short-circuit current foldback circuit thereof | |
| CN208508514U (en) | A kind of short-circuit protection circuit of switching circuit | |
| CN113113894A (en) | Power failure detection and power supply protection circuit | |
| CN111864697A (en) | Overcurrent protection circuit and method and system for judging whether power supply is overhauled | |
| US5206538A (en) | Automatic system battery reconnect circuit responsive to insertion of new battery replacement | |
| CN106300642B (en) | A kind of dual power supply redundancy cold standby circuit with power supply status output | |
| CN110032263A (en) | A kind of server and its power-down protection circuit | |
| CN100449901C (en) | Apparatus for preventing equipment internal combustion from drawing outward | |
| TWM464913U (en) | Voltage abnormality protection circuit for uninterruptable power supply | |
| CN207021659U (en) | A kind of DC protection circuit | |
| CN205484714U (en) | Circuit is listened to killer switch state | |
| CN202374353U (en) | Television and motherboard power supply short-circuit detection circuit thereof | |
| CN115360668A (en) | Direct current input circuit and control method thereof | |
| CN108644144A (en) | A kind of DC fan failure monitoring system | |
| CN112751410A (en) | Power supply control circuit of low-voltage direct-current circuit | |
| CN111934301A (en) | High-power hot plug control circuit and method | |
| CN105322499A (en) | Short-circuit protection circuit based on power supply load abnormality | |
| CN211670631U (en) | Power protection system based on high-speed camera standard interface | |
| CN218276118U (en) | UPS device and electronic equipment | |
| CN204833034U (en) | Steady voltage source can be monitored to quick -break type three -terminal | |
| CN219892946U (en) | Power supply switching circuit with hot plug function | |
| CN217332573U (en) | High-temperature test reliability protection circuit | |
| CN204856273U (en) | Wide region P type monitoring steady voltage protective power supply |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |