CN218850757U

CN218850757U - Key scanning circuit

Info

Publication number: CN218850757U
Application number: CN202223155788.2U
Authority: CN
Inventors: 张召德
Original assignee: Qingdao Magene Intelligence Technology Co Ltd
Current assignee: Qingdao Magene Intelligence Technology Co Ltd
Priority date: 2022-11-28
Filing date: 2022-11-28
Publication date: 2023-04-11
Anticipated expiration: 2032-11-28

Abstract

The utility model discloses a key scanning circuit, including parallelly connected two according to the key group, include according to the key group: the key matrix comprises a key unit and a total resistor connected with the key unit in series; the key unit comprises a plurality of key branches, and each key branch comprises a key and a matching resistor; the switch assembly comprises a first switch assembly and a second switch assembly, the first switch assembly and the second switch assembly are respectively connected to two ends of the key matrix in series and are respectively controlled to be switched on or switched off by signals output by the MCU; when the switch assembly is switched on, the MCU provides power for the key matrix; outputting a voltage signal for representing the pressing condition of a key at a connecting position between the key unit and the total resistor; when the switch assembly is conducted and at least one key in the key unit corresponding to the switch assembly is pressed down, the output voltage signals are different. The utility model is used for solve and use the more and more problem of signal connection line of MCU port in the prior art.

Description

Key scanning circuit

Technical Field

The utility model relates to a button detects technical field, especially relates to a button scanning circuit.

Background

The key scanning circuit has extensive application in various circuit systems, the present key scanning circuit includes a plurality of key switches, each key switch's one end ground connection respectively, the other end passes through the wire respectively with the power be connected respectively simultaneously with MCU (Microcontroller Unit, little the control Unit) three IO port connection, consequently, it needs to consume a plurality of ports of MCU, and the quantity of IO port is limited in circuit system, the phenomenon that the IO port is not enough often can appear, and the signal line is connected too much.

Disclosure of Invention

In order to solve the technical problem, the utility model provides a key scanning circuit for use the more and more problem of signal connection line of MCU port in solving the prior art.

Therefore, the utility model discloses a following technical scheme realizes:

the application relates to a key scanning circuit, including two parallelly connected key groups, key group includes:

the key matrix comprises a key unit and a total resistor connected with the key unit in series; the key unit comprises a plurality of key branches, and each key branch comprises a key and a matching resistor;

the switch assembly comprises a first switch assembly and a second switch assembly, the first switch assembly and the second switch assembly are respectively connected to two ends of the key matrix in series and are respectively controlled to be switched on or switched off by signals output by the MCU; when the switch assembly is conducted, the MCU provides a power supply for the key matrix; outputting a voltage signal used for representing the pressing condition of a key at the connecting position between the key unit and the total resistor;

when the switch assembly is conducted and at least one key in the key unit corresponding to the switch assembly is pressed down, the output voltage signals are different; the switch components in the two key groups are not conducted at the same time.

In some embodiments of the present application, the first switching assembly comprises a first switching element, the second switching assembly comprises a second switching element;

the first switch element and the second switch element are respectively connected in series with two ends of the key matrix and are respectively controlled to be switched on or switched off by signals output by two output ports of the MCU; and when the switch assembly is switched on, the two output ports and the key matrix form a power supply loop.

In some embodiments of the present application, the AD port of the MCU is connected at a connection position between the key matrix and the total resistance.

In some embodiments of the present application, the keys and the matching resistors in the key branches are connected in series, and the plurality of key branches are connected in parallel;

the resistance value of each matching resistor in the key unit is different from the resistance value of any plurality of matching resistors connected in parallel.

In some embodiments of the present application, the keys in the key branches are connected in parallel with matching resistors, and the plurality of key branches are connected in series;

the resistance value of each matching resistor in the key unit is different from the resistance value of any plurality of matching resistors after being connected in series.

In some embodiments of the present application, the two key groups include a first key group and a second key group;

one end of a first switch element in the first key group is connected with the total resistor in the first key group, the other end of the first switch element is connected with a first output port of the two output ports of the MCU, and a control end of the first switch element is connected with a second output port of the two output ports of the MCU;

one end of a second switch element in the first key group is connected with the key unit in the first key group, the other end of the second switch element is connected with the second output port, and a control end of the second switch element is connected with the first output port;

one end of a second switch element in the second key group is connected with the key unit in the second key group, the other end of the second switch element is connected with the first output port, and a control end of the second switch element is connected with the second output port;

one end of a first switch element in the second key set is connected with the total resistor in the second key set, the other end of the first switch element is connected with the second output port, and the control end of the first switch element is connected with the first output port.

In some embodiments of the present application, one of the first switching element and the second switching element is one of a switching element that is turned on at a high level and a switching element that is turned on at a low level, and the other is the other of the switching element that is turned on at a high level and the switching element that is turned on at a low level.

In some embodiments of the present application, the first switching element is a PMOS transistor, and the second switching element is an NMOS transistor;

the source electrode of a PMOS tube in the first key group is connected with the total resistor in the first key group, the drain electrode of the PMOS tube is connected with the first output port, and the grid electrode of the PMOS tube is connected with the second output port;

the source electrode of an NMOS tube in the first key group is connected with the key unit in the first key group, the drain electrode is connected with the second output port, and the grid electrode is connected with the first output port;

the source electrode of an NMOS tube in the second key group is connected with the key unit in the second key group, the drain electrode is connected with the first output port, and the grid electrode is connected with the second output port;

and the source electrode of the PMOS tube in the second key group is connected with the total resistor in the second key group, the drain electrode is connected with the second output port, and the grid electrode is connected with the first output port.

In some embodiments of the present application, the two key groups include a first key group and a second key group, the first switch element is a first diode, and the second switch element is a second diode;

the anode of a first diode in the first key group is connected with a first output port in the two output ports of the MCU, and the cathode of the first diode is connected with the total resistor in the first key group;

the cathode of a second diode in the first key group is connected with a second output port in the two output ports of the MCU, and the anode of the second diode is connected with the key unit in the first key group;

the anode of a first diode in the second key group is connected with the second output port, and the cathode of the first diode is connected with the total resistor in the second key group;

and the cathode of a second diode in the second key group is connected with the first output port, and the anode of the second diode is connected with the key unit in the second key group.

In some embodiments of the present application, the key scanning circuit further comprises:

and the delay unit is connected with the MCU and can delay a plurality of times.

Compared with the prior art, the key scanning circuit of the embodiment has the following advantages and beneficial effects:

(1) The method comprises the steps that two key groups connected in parallel are arranged, each key group comprises a key matrix, the key matrix comprises a key unit and a total resistor, the key unit comprises a plurality of key branches, each key branch comprises a key and a matching resistor, the key matrix is selected to be used by closing a signal control switch component output by an output port of an MCU, and when at least one key in a projection matrix is correspondingly pressed, the key is represented by a voltage signal output at a connecting position between the key matrix and the total resistor, so that when the corresponding voltage signal is obtained, which key in the key unit is pressed can be known, fewer ports of the MCU are adopted, fewer signal lines are connected between the MCU and the key groups, and the key scanning circuit is simple and easy to implement;

(2) The key unit comprises a plurality of key branches, and each key can be pressed independently or combined with each other, so that various key combination modes can be scanned.

Other features and advantages of the present invention will become more apparent from the following detailed description of the invention when read in conjunction with the accompanying drawings.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a circuit diagram of a first embodiment of a key scanning circuit according to the present invention;

fig. 2 is a circuit diagram of a second embodiment of the key scanning circuit provided by the present invention;

fig. 3 is a circuit diagram of a third embodiment of the key scanning circuit according to the present invention.

Reference numerals:

10-MCU; 20-a first key group; 21/21' -key matrix; 30-a second key group; 31/31' -key matrix.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

It should be noted that in the description of the present invention, the terms of direction or positional relationship indicated by the terms "upper", "lower", "left", "right", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, which are only for convenience of description, and do not indicate or imply that the device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In order to realize the scanning of various keys under the condition of using few ports and few signal lines of the MCU 10, the application relates to a key scanning circuit.

Referring to fig. 1 to 3, the key scanning circuit includes two key groups in parallel, including a first key group 20 and a second key group 30.

The first key group 20 and the second key group 30 are not used at the same time, that is, only one of the key groups is selected to be used at the same time, as will be described in detail below.

The key group comprises a key matrix and a switch component.

The switch assembly is connected in series with the main branch of the key matrix and is used for enabling the key matrix to be put into use when the switch assembly is closed, namely, the situation that the key in the key matrix is pressed down can be detected, and the key matrix is not put into use when the switch assembly is disconnected.

The key matrix comprises key units and total resistors connected in series with the key units, the key units comprise a plurality of key branches, each key branch comprises a key and a matching resistor, and the key and the matching resistor can be connected in series or in parallel, and the following description is specifically referred to.

The switch assembly comprises a first switch assembly and a second switch assembly, the first switch assembly and the second switch assembly are respectively connected to two ends of the key matrix in series, and are respectively controlled to be switched on or switched off by signals output by the output port of the MCU 10.

When the first switch component and the second switch component are respectively controlled by the MCU 10 to be conducted, the MCU 10 provides power for the key matrix, and the key matrix between the first switch component and the second switch component is put into use; when the first switch assembly and the second switch assembly are controlled to be disconnected by the MCU 10, the MCU 10 cannot provide power to the key matrix, and the key matrix between the first switch assembly and the second switch assembly is not used.

When the key matrix is put into use, and at least one key in the key unit is pressed, different voltage signals are output, namely when any key in the key unit is pressed and any plurality of keys in the key unit are simultaneously pressed, different voltage signals are respectively output so as to judge the pressed key condition according to different voltage signals.

IN the application, the connection position between the key matrix and the total resistor is connected with the AD port ADC _ IN of the MCU 10, and is used for receiving the output voltage signal OUT1, so as to conveniently determine the key pressing condition, for example, the MCU 10 may control to output a file of the key pressing condition according to the voltage signal OUT1 received at the AD port ADC _ IN.

The number of key branches is affected by circuit noise and is generally less than the number of bits of the ADC in the MCU 10.

In this application, the first switch assembly includes a first switch element, the second switch assembly includes a second switch element, and the first switch element and the second switch element are controlled by a signal output by the MCU 10.

The first switch element and the second switch element are respectively connected in series to two ends of the key matrix and are respectively controlled to be switched on or off by signals output by two output ports of the MCU 10.

When the switch assembly is turned on (i.e., both the first switch element and the second switch element are turned on), the two output ports of the MCU 10 and the key matrix form a power supply loop, and the key matrix in the power supply loop is used.

In the present application, the key matrix 21 includes a total resistance R10 and a key unit a, and the key matrix 31 includes a total resistance R20 and a key unit B.

In the present application, the number of the key branches in the key unit a and the key unit B is three for example.

Referring to fig. 1, each key branch includes a juxtaposed key and a matching resistor.

The key unit A comprises a first key branch, a second key branch and a third key branch which are connected in parallel.

The first key branch comprises a key SW11 and a matching resistor R11 connected in series, the second key branch comprises a key SW12 and a matching resistor R12 connected in series, and the third key branch comprises a key SW13 and a matching resistor R13 connected in series.

In order to detect the pressing condition of the keys and the combination keys thereof in the key matrix 21, the resistances of the matching resistors R11, R12, and R13 are different from each other, and any two parallel resistances are different from each other and also different from the three parallel resistances.

The key unit B includes a first key branch, a second key branch and a third key branch connected in parallel with each other.

The first key branch comprises a key SW21 and a matching resistor R21 connected in series, the second key branch comprises a key SW22 and a matching resistor R22 connected in series, and the third key branch comprises a key SW23 and a matching resistor R23 connected in series.

In order to detect the pressing of the keys and the combination keys in the key matrix 31, the resistances of the matching resistors R21, R22, and R23 are different from each other, and any two parallel resistors have different resistances from each other, and also have different resistances from three parallel resistors.

Since the

key matrixes

21 and 31 are not put into use at the same time, the switch components in the first key group 20 and the switch components in the second key group 30 are not turned on at the same time, that is, the first switch element in the first key group 20 and the first switch element in the second key group 30 receive different signals output by the MCU 10, and the second switch element in the first key group 20 and the second switch element in the second key group 30 receive different signals output by the MCU 10, so that when the first switch element and the second switch element in the first key group 20 are turned on, the first switch element and the second switch element in the second key group 30 are turned off.

In the present application, the first switching element and the second switching element may be switching elements having control terminals.

One end of a first switch element in the first key group 20 is connected to the total resistor R10 in the first key group 20, the other end of the first switch element is connected to a first output port GPIO _ OUT1 of the two output ports of the MCU 10, and the control end of the first switch element is connected to a second output port GPIO _ OUT2 of the two output ports of the MCU 10.

One end of the second switch element in the first key group 20 is connected to the key unit a in the first key group 20, the other end is connected to the second output port GPIO _ OUT2, and the control end is connected to the first output port GPIO _ OUT1.

One end of a second switch element in the second key group 30 is connected to the key unit B in the second key group 30, the other end is connected to the first output port GPIO _ OUT1, and the control end is connected to the second output port GPIO _ OUT2.

One end of a first switch element in the second key group 30 is connected to the total resistor R20 in the second key group 30, the other end is connected to the second output port GPIO _ OUT2, and the control end is connected to the first output port GPIO _ OUT1.

Because the first switch element and the second switch element in the first key group 20 are controlled by the signals output by the second output port GPIO _ OUT2 and the first output port GPIO _ OUT1, respectively, and the first switch element and the second switch element in the second key group 30 are controlled by the signals output by the first output port GPIO _ OUT1 and the first output port GPIO _ OUT2, respectively, when the first switch element and the second switch element in the first key group 20 are controlled to be turned on, the first switch element and the second switch element in the second key group 30 are not turned on, and at this time, it can be satisfied that the second key group 30 is not put into use while supplying power to the key matrix 21 in the first key group 20.

As described above, one of the first switch element and the second switch element selects one of the switch element turned on at a high level and the switch element turned on at a low level, and the other of the first switch element and the second switch element selects the other of the switch element turned on at a high level and the switch element turned on at a low level, that is, the first switch element and the second switch element belonging to the same key group should be different.

In the present application, the first switching element selects a switching element that is turned on at a low level, for example, a PMOS transistor, and the second switching element selects a switching element that is turned on at a high level, for example, an NMOS transistor.

Referring to fig. 1, for the first key set 20, the first switch element is a PMOS transistor Q8, and the second switch element is an NMOS transistor Q11.

For the second key set 30, the first switch element is a PMOS transistor Q9, and the second switch element is an NMOS transistor Q10.

Referring to fig. 1, the first key group 20 includes a key matrix 21, a first switching element Q8, and a second switching element Q11.

The first output port GPIO _ OUT1 of the MCU 10 outputs a signal IN1 and is connected to the drain of the first switching element Q8, the drain of the second switching element Q10, the gate of the second switching element Q11, and the drain of the first switching element Q9.

The first output port GPIO _ OUT2 of the MCU 10 outputs a signal IN2 and is connected to the gate of the first switching element Q8, the drain of the second switching element Q11, the gate of the second switching element Q10, and the drain of the first switching element Q9.

The source of the first switching element Q8 is connected to one end of the total resistance R10 which is not connected to the key unit a, and the source of the second switching element Q11 is connected to one end of the key unit a which is not connected to the total resistance R10.

The source of the first switching element Q9 is connected to one end of the total resistance R20 which is not connected to the key unit B, and the source of the second switching element Q10 is connected to one end of the total resistance R20 which is not connected to the key unit B.

IN this manner, when the signal IN1 output from the MCU 10 is at a high level and the signal IN2 is at a low level, the first switching element Q8 and the second switching element Q11 are turned on, and the first switching element Q9 and the second switching element Q10 are turned off.

The high level IN1, the low level IN2 and the first key set 20 form a loop, so that the first key set 20 is used, and the high level IN1 provides power for the first key set 20.

IN addition, IN the present application, the connection position between the key unit a and the total resistor R10 IN the first key group 20 and the connection position between the key unit B and the total resistor R20 IN the second key group 30 are both connected to the AD port ADC _ IN of the MCU 10, respectively, and are configured to receive the output voltage OUT1.

For example, R10=1k Ω, R11=1k Ω, R12=2k Ω, R13=4k Ω.

If the high level IN1 provides the corresponding 1V power supply, the voltage OUT1 is 1V when the key is not pressed; when the key SW11 is pressed, the voltage OUT1 is 0.5V; when the key SW12 is pressed, the voltage OUT1 is 0.667V; when the key SW13 is pressed, the voltage OUT1 is 0.8V; when the keys SW11 and SW12 are pressed, the voltage OUT1 is 0.4V; when the keys SW11 and SW13 are pressed, the voltage OUT1 is 0.444V; when the keys SW12 and SW13 are pressed down, the voltage OUT1 is 0.571V; when the keys SW11, SW12 and SW13 are pressed, the voltage OUT1 is 0.363V.

IN this way, it is possible to determine whether a key is pressed IN the key matrix 21 based on the voltage OUT1 output to the AD port AD _ IN port of the MCU 10.

IN this manner, when the signal IN1 output from the MCU 10 is low and IN2 is high, the first and second switching elements Q8 and Q11 are turned off, and the first and second switching elements Q9 and Q10 are turned off.

And the low level IN1, the high level IN2 and the second key group 30 form a loop, so that the second key group 30 is put into use, and the high level IN2 provides power for the second key group 30.

For example, R20=1k Ω, R21=1k Ω, R22=2k Ω, and R23=4k Ω.

If the high level IN2 provides the corresponding 1V power, the voltage OUT1 is 1V when the key is not pressed; when the key SW21 is pressed, the voltage OUT1 is 0.5V; when the key SW22 is pressed down, the voltage OUT1 is 0.667V; when the key SW23 is pressed, the voltage OUT1 is 0.8V; when the keys SW21 and SW22 are pressed, the voltage OUT1 is 0.4V; when the keys SW21 and SW23 are pressed, the voltage OUT1 is 0.444V; when the keys SW22 and SW23 are pressed down, the voltage OUT1 is 0.571V; when the keys SW21, SW22 and SW23 are pressed, the voltage OUT1 is 0.363V.

IN this way, it is possible to determine whether a key is pressed IN the key matrix 31, based on the voltage OUT1 output to the AD port AD _ IN port of the MCU 10.

The first switching element may be a switching element that is turned on at a high level, such as an NMOS transistor, and the second switching element may be a switching element that is turned on at a low level, such as a PMOS transistor.

At this time, the operation principle of the key scanning circuit is similar to that described above.

In other embodiments, the switching element described above may also select a switching tube NPN or PNP, etc., and the principle operation process is similar to that described above, which is not described herein again.

The first switch assembly/the second switch assembly may also include a plurality of switch elements, and correspondingly, each of the plurality of switch elements needs to be controlled by a signal output by the output port of the MCU 10 to be turned on or off, so that the number of the switch elements is not limited to the number described above, and the number of the signals output by the output port of the MCU 10 is not limited to two, as long as one key group can be put into use while the other key group is not put into use, so as to ensure the accuracy of key scanning.

Other switching elements may also be selected using the principle of unidirectional conduction.

In the present application, the switching elements in the present application can be realized by using diodes by utilizing the characteristic of unidirectional conduction of diodes.

Referring to fig. 2, the first switch element in the first key set 20 is D1, the second switch element is D2, the first switch element in the second key set 30 is D3, and the fourth switch element is D4.

The anode of the first switch element D1 is connected to the first output port GPIO _ OUT1, the cathode is connected to one end of the total resistor R10 which is not connected to the key unit a, the anode of the second switch element D2 is connected to one end of the total resistor R10 which is not connected to the key unit a, and the cathode is connected to the second output port GPIO _ OUT2.

The anode of the first switch element D3 is connected to the second output port GPIO _ OUT2, the cathode is connected to one end of the total resistor R20 which is not connected to the key unit B, the anode of the second switch element D4 is connected to one end of the key unit B which is not connected to the total resistor R20, and the cathode is connected to the first output port GPIO _ OUT1.

The key matrix 21 in the first key group 20 includes a total resistance R10 and a key unit a.

The key unit A comprises a first key branch, a second key branch and a third key branch which are connected in series.

The first key branch comprises a key SW11 and a matching resistor R11 which are connected in parallel, the second key branch comprises a key SW12 and a matching resistor R12 which are connected in parallel, and the third key branch comprises a key SW13 and a matching resistor R13 which are connected in parallel.

The key matrix 31 in the second key group 30 includes a total resistance R20 and a key unit B.

The key unit B comprises a first key branch, a second key branch and a third key branch which are connected in series.

The first key branch comprises a key SW21 and a matching resistor R21 connected in parallel, the second key branch comprises a key SW22 and a matching resistor R22 connected in parallel, and the third key branch comprises a key SW23 and a matching resistor R23 connected in parallel.

When the signal IN1 output from the MCU 10 is at a high level and IN2 is at a low level, the first and second switching elements D1 and D2 are turned on, and the first and second switching elements D3 and D4 are turned off.

The high level IN1, the low level IN2 and the first key set 20 form a loop, so that the first key set 20 is used, and the high level IN1 provides power for the first key set 20, while the second key set 30 is not used.

As described above, the matching resistors in the same key unit have different resistance values, and the resistance values of any of the matching resistors connected in parallel are also different from each other and from each matching resistor.

As described above, based on the value of the high level IN1 and the resistance values of the matching resistors, the key press condition IN the key matrix 21 can be determined according to the output voltage OUT1.

Similarly, when IN1 is at low level, IN2 is at high level, and it is judged that a key is pressed IN the key matrix 31.

In other embodiments, the switch element may also be an optical coupler, and the first switch element in the first key group 20 is taken as an example for description.

The positive pole of the light emitting diode of the optocoupler is connected with the first output port GPIO _ OUT1 of the MCU 10, the negative pole of the light emitting diode is grounded, the collector of the triode is powered by external power, and the emitter of the triode is connected with the total resistor R10 and is not connected with one end of the key unit A.

IN this way, when the signal IN1 output by the first output port GPIO _ OUT1 is at a high level, the optocoupler is turned on.

Referring to fig. 3, the first key group 20 includes a key matrix 21', a first switching element Q8, and a second switching element Q11.

The key matrix 21 'includes a total resistance R10 and a key cell a'.

The key unit A' comprises a first key branch, a second key branch and a third key branch which are connected in series.

The resistances of the matching resistors R11, R12, and R13 are different from each other, and the resistances of any two resistors connected in series are different from each other, and also different from the resistances of the three resistors connected in series.

The second key group 30 includes a key matrix 22', a first switching element Q9, and a second switching element Q10.

The key matrix 22 'includes a total resistance R20 and a key cell B'.

The key unit B' includes a first key branch, a second key branch, and a third key branch connected in series.

The matching resistors R21, R22, and R23 have different resistances, and any two resistors connected in series have different resistances and also have different resistances from three resistors connected in series.

Referring to the above description, when the signal IN1 output from the MCU 10 is at the high level and the IN2 is at the low level, the first and second switching elements Q8 and Q11 are turned on, and the first and second switching elements Q9 and Q10 are turned off.

And the high level IN1, the low level IN2 and the first key group 20 form a loop, so that the first key group 20 is put into use, and the high level IN1 provides power for the first key group 20.

IN addition, IN the present application, the connection position between the key unit a 'and the total resistor R10 IN the first key group 20 and the connection position between the key unit B' and the total resistor R20 IN the second key group 30 are both connected to the AD port ADC _ IN of the MCU 10, respectively, for receiving the output voltage OUT1.

For example, R10=1k Ω, R11=1k Ω, R12=2k Ω, R13=4k Ω.

If the high level IN1 provides the corresponding 1V power supply, the voltage OUT1 is 1V when the key is not pressed; when the key SW11 is pressed down, the voltage OUT1 is 0.857V; when the key SW12 is pressed down, the voltage OUT1 is 0.833V; when the key SW13 is pressed, the voltage OUT1 is 0.75V; when the keys SW11 and SW12 are pressed, the voltage OUT1 is 0.8V; when the keys SW11 and SW13 are pressed, the voltage OUT1 is 0.667V; when the keys SW12 and SW13 are pressed, the voltage OUT1 is 0.5V; when the keys SW11, SW12 and SW13 are pressed, the voltage OUT1 is 0.875V.

IN this way, it is possible to determine whether a key is pressed IN the key matrix 21' based on the voltage OUT1 output to the AD port AD _ IN port of the MCU 10.

IN this manner, when the signal IN1 output from the MCU 10 is at a low level and the signal IN2 is at a high level, the first switching element Q8 and the second switching element Q11 are turned off, and the first switching element Q9 and the second switching element Q10 are turned off.

The low level IN1, the high level IN2 and the second key set 30 form a loop, so that the second key set 30 is used, and the high level IN2 provides power for the second key set 30.

For example, R20=1k Ω, R21=1k Ω, R22=2k Ω, R23=4k Ω.

Similarly as analyzed above, the voltage OUT1 at the AD port AD _ IN port of the MCU 10 when different keys SW21, SW22, and SW23 are pressed can be obtained, and the condition of pressing a key IN the key matrix 31' can be determined.

The key scanning circuit provided by the application only needs to use three ports of the MCU 10, and does not need complex connecting wires, so that the scanning detection of various key combinations can be realized.

IN the present application, for the accuracy of scanning and detecting the key, the signal OUT1 may be collected through the ADC _ IN port of the MCU 10 after 2ms delay after the MCU 10 outputs the signals IN1 and IN2, so as to ensure the stability of the collected signal.

The above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that various changes in the form and details of the embodiments may be made, or equivalents may be substituted for elements thereof; such modifications and substitutions do not depart from the spirit and scope of the present invention, which is claimed.

Claims

1. A key scan circuit, comprising two key groups connected in parallel, the key groups comprising:

the switch assembly comprises a first switch assembly and a second switch assembly, the first switch assembly and the second switch assembly are respectively connected to two ends of the key matrix in series and are respectively controlled to be switched on or switched off by signals output by the MCU; when the switch assembly is switched on, the MCU provides a power supply for the key matrix; outputting a voltage signal for representing the key pressing condition at the connecting position between the key unit and the total resistor;

2. The key scanning circuit of claim 1 wherein the first switching assembly includes a first switching element and the second switching assembly includes a second switching element;

the first switch element and the second switch element are respectively connected in series with two ends of the key matrix and are respectively controlled to be switched on or switched off by signals of two output ports of the MCU; and when the switch assembly is switched on, the two output ports and the key matrix form a power supply loop.

3. The key scan circuit of claim 1, wherein the AD port of the MCU is connected at a connection location between the key matrix and the total resistance.

4. The key scanning circuit of claim 2, wherein the keys of the key branches are connected in series with matching resistors, and the plurality of key branches are connected in parallel;

5. The key scanning circuit of claim 2, wherein the keys in the key branches are connected in parallel with matching resistors, and the plurality of key branches are connected in series;

6. The key scanning circuit of claim 2, wherein the two key groups include a first key group and a second key group;

7. The key scanning circuit of claim 6,

one of the first switching element and the second switching element is one of a switching element that is turned on at a high level and a switching element that is turned on at a low level, and the other is the other of the switching element that is turned on at a high level and the switching element that is turned on at a low level.

8. The key scan circuit of claim 7, wherein the first switching element is a PMOS transistor, and the second switching element is an NMOS transistor;

the source electrode of a PMOS tube in the first key group is connected with the total resistor in the first key group, the drain electrode is connected with the first output port, and the grid electrode is connected with the second output port;

9. The key scanning circuit of claim 2, wherein the two key groups include a first key group and a second key group, the first switching element is a first diode, and the second switching element is a second diode;

10. The key scanning circuit of claim 2, further comprising: