CN218829985U - Gigabit Ethernet MAC controller capable of being integrated in SoC system - Google Patents

Abstract

The gigabit Ethernet MAC controller capable of being integrated in an SoC system comprises a DMA controller module, an FIFO controller module, an MAC module, an AXI host interface, an APB slave interface and a TBI interface/SGMII interface. The DMA controller module is connected with a memory of the SoC system through an AXI host interface to carry out data interaction and is connected with the CPU through an APB slave interface for communication; the FIFO controller module is connected between the DMA controller module and the MAC module and used for providing cache for sending data and receiving data; the MAC module is connected with the physical layer PHY through a TBI interface/SGMII interface and is used for acquiring sending data from the FIFO controller module and sending the data to the physical layer PHY; and is used for receiving data from the physical layer PHY and then transmitting the data to the FIFO controller module. The scheme can be integrated in an SoC system, and the transmission rate is improved by improving the hardware structure of the controller and optimizing the interface selection; the problem of cross-time domain transmission in transmission is also solved.

Description

Gigabit Ethernet MAC controller capable of being integrated in SoC system

Technical Field

The application belongs to the technical field of electronic information, relates to a chip circuit hardware structure of an SoC system, and particularly relates to a gigabit Ethernet MAC controller which can be integrated in the SoC system.

Background

The modern society is an information-based society, and computer networks are used in almost all fields, and become an essential part in people's lives. With the increasing popularity and spread of the internet in the 21 st century, computer networking technology has played a very important role in various human production activities over 40 years of accumulation. Compared with metropolitan area networks and wide area networks, the local area networks have small coverage, but have higher data transmission rate, smaller delay and lower error rate. Due to the advantages of local area networks, local area networks are widely used to connect personal computers or workstations of campuses, factories and institutions to facilitate sharing of resources and data communication among the personal computers or workstations.

The Ethernet technology belongs to one of local area network link layer standards, and mainly comprises a plurality of stations, various transmission media required by mutual information transmission among the stations, and equipment for connecting each station with a network. The ethernet has a simple structure, low cost, easily expandable data bandwidth and strong flexibility, so that in the development process, the ethernet overcomes other local area network technologies such as token bus, token ring, wangtet, FDDI and the like by virtue of the advantages of low cost, high rate, low delay and the like, and becomes the network technology with the highest market share in the local area network range at present. The front body of the Ethernet is an A lot aloha network which is introduced by Xerox company, and the Ethernet is only suitable for interconnection of hundreds of personal workstations within a kilometer range, and the speed is 2.94Mbps; the company Xerox, in turn, collaborated with the companies Intel and DEC to derive industry standards for ethernet, namely ethernet: data link layer and physical layer specification version 1.0 "; in 1982, version 2.0 was published at a rate of 10Mbps, which is commonly referred to as ethernet DIX or ethernet ii. In the early 80 s of the 20 th century, the IEEE 802 Commission developed a LAN architecture, namely the IEEE 802 reference model.

The traditional ethernet MAC controller generally adopts the MII interface or the GMII interface to meet the transmission rate, and nowadays, the computer network is rapidly developed, and the transmission rate of the ethernet adopting these two interfaces can not meet the daily work requirement of people. Based on the situation, how to enrich the interfaces of the ethernet MAC controller, improve the transmission rate, and better control the sending and receiving of the ethernet data frames becomes a problem to be solved urgently.

SUMMERY OF THE UTILITY MODEL

In order to solve the defects of the prior art, the application provides a gigabit ethernet MAC controller which can be integrated in an SoC system and improve the transmission rate by improving the hardware structure of the controller and optimizing the interface selection; the problem of cross-time domain transmission in transmission is also solved.

In order to achieve the above purpose, the utility model adopts the following technology:

a gigabit Ethernet MAC controller can be integrated in an SoC system and comprises a DMA controller module, an FIFO controller module, an MAC module, an AXI host interface, an APB slave interface and a TBI interface/SGMII interface which are connected in sequence.

The DMA controller module is connected with a memory of the SoC system through an AXI host interface to carry out data interaction and is connected with the CPU through an APB slave interface for communication;

the FIFO controller module is connected between the DMA controller module and the MAC module and used for providing cache for sending data and receiving data;

the MAC module is connected with the physical layer PHY through a TBI interface/SGMII interface and is used for acquiring sending data from the FIFO controller module and sending the data to the physical layer PHY; and is used to receive data from the physical layer PHY and transmit it to the FIFO controller module.

The DMA controller module comprises a DMA arbitration module, a DMA receiving and sending channel connected with the DMA arbitration module and a DMA register, wherein the DMA register is connected with the DMA receiving and sending channel which is connected with the FIFO controller module; the DMA arbitration module is connected with an AXI host interface, and the DMA register is connected with an APB slave interface.

The DMA transceiving channel comprises a DMA transmitting channel and a DMA receiving channel, and the FIFO controller module comprises an FIFO transmitting controller and an FIFO receiving controller; the number of the DMA sending channels and the number of the DMA receiving channels are both 8, the DMA sending channels are respectively in one-to-one correspondence with the memory queues of the FIFO sending controller and the FIFO receiving controller, the DMA sending channels are connected with the FIFO sending controller, and the DMA receiving channels are connected with the FIFO receiving controller.

The memory queue of the FIFO sending controller is a sending FIFO, the memory queue of the FIFO receiving controller is a receiving FIFO, the queues of the sending FIFO and the receiving FIFO are both 8, and are both asynchronous FIFOs with synchronous modules. Optionally, the transmission FIFO and the reception FIFO are both formed using dual port RAMs.

The MAC module comprises an MAC sending unit and an MAC receiving unit, the FIFO sending controller is connected with the MAC sending unit, and the FIFO receiving controller is connected with the MAC receiving unit; the MAC sending unit and the MAC receiving unit are connected with the physical layer PHY through a TBI interface/SGMII interface.

The utility model has the advantages that:

1. the gigabit Ethernet MAC controller can be integrated in an SoC system, an AXI bus is adopted to connect interactive data with a system memory, an APB bus is adopted to communicate with a CPU so as to facilitate the CPU to configure a DMA register, a TBI interface/SGMII interface is adopted to connect a physical layer PHY, the transmission rate of 10M/100M/1000M can be realized, and compared with the prior art, the transmission rate is obviously improved;

2. the FIFO controller module is used for caching so that the cached data can be adjusted and the problem of cross-time domain transmission in the transmission process is solved; meanwhile, the FIFO sending controller and the FIFO receiving controller are both provided with memories with queues of 8 and are in one-to-one correspondence with the DMA sending channels and the receiving channels respectively, and the middle bridge function is more stable and effective when the FIFO sending controller and the FIFO receiving controller are used as caches.

Drawings

Fig. 1 is an overall architecture diagram of a gigabit ethernet MAC controller according to an embodiment of the present application.

Fig. 2 is a block diagram of a DMA controller module according to an embodiment of the present application.

Fig. 3 is a block diagram of a FIFO controller module according to an embodiment of the present application.

Fig. 4 is a diagram of a MAC module structure according to an embodiment of the present application.

Fig. 5 is a signal diagram of a TBI interface according to an embodiment of the present application.

Fig. 6 is a signal diagram of an SGMII interface according to an embodiment of the present application.

Detailed Description

To make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the following detailed description of the embodiments of the present invention is made with reference to the accompanying drawings, however, the described embodiments of the present invention are some, not all embodiments of the present invention.

An embodiment of the present application provides a gigabit ethernet MAC controller that can be integrated in an SoC system, as shown in fig. 1, including a DMA controller module, an FIFO controller module, and an MAC module, which are connected in sequence. In this example, the AXI host interface uses an AXI bus 3.0 to perform data interaction with the system memory, the APB slave interface uses an APB bus 3.0 to communicate with the CPU, and the CPU configures the DMA register in the DMA controller module through the slave interface. The interfaces of the MAC module and the physical layer PHY adopt a TBI interface and an SGMII interface, so that the transmission rate of 1000Mbps can be achieved, and the transmission rate is obviously improved relative to other types of interfaces.

Specifically, the DMA controller module is connected with a memory of the SoC system through an AXI host interface to perform data interaction, and is connected with a CPU through an APB slave interface to communicate; the FIFO controller module is connected between the DMA controller module and the MAC module and used for providing cache for sending data and receiving data; the MAC module is connected with the physical layer PHY through a TBI interface/SGMII interface and is used for acquiring sending data from the FIFO controller module and sending the data to the physical layer PHY; and is used to receive data from the physical layer PHY and transmit it to the FIFO controller module.

Fig. 5 is a signal diagram of the TBI interface used in this example. The data bit width of the TBI interface is 10 bits, and when the TBI interface is used for sending data, the data bit width of 8 bits/10 bits can be converted, so that the transmission rate can be remarkably improved compared with the traditional GMII interface with the data bit width of 8 bits. In the interface signal of TBI, RX _ CLK is a half-frequency clock recovered from received data, the clock frequency is 62.5MHz, and RX _CLKis not a differential signal but two independent signals with a phase difference of 180 degrees between them, and data is sampled at the rising edge of both clocks.

Fig. 6 shows a signal diagram of the SGMII interface used in this example. The SGMII interface is also a serial GMII interface, data receiving and transmitting are respectively provided with a pair of differential signal lines, the clock frequency is 615MHz, and double-clock edge sampling is adopted, namely data is sampled on both the rising edge and the falling edge of a clock signal. In the SGMII interface signal, the reference clock RX _ CLK is provided by the PHY and is not normally used, and both transceiving and receiving can recover the clock from the data. In serial data transmitted by TXD, two bits of control information TX _ EN/TX _ ER are inserted for every 8 bits of data, and similarly, in RXD received data, two bits of control information RX _ DV/RX _ ER are inserted for every 8 bits of data, so the total data rate is 1.25gbps =625mbps 2. The SGMII interface not only has a fast transmission speed, but also has a much lower cost compared to the conventional GMII and RGMII interfaces.

As an alternative implementation form, as shown in fig. 2, the DMA controller module of this example includes a DMA arbitration module, a DMA transceiving channel connected to the DMA arbitration module, and a DMA register. The DMA register is connected with a DMA receiving and transmitting channel, the DMA receiving and transmitting channel is connected with the FIFO controller module, and the DMA receiving and transmitting channel comprises a DMA transmitting channel and a DMA receiving channel. The DMA arbitration module is connected with an AXI host interface, and the DMA register is connected with an APB slave interface.

And the DMA arbitration module performs data interaction with a memory of the SoC system through an AXI host interface. The DMA register acquires the information written by the CPU from the interface of the APB slave machine for storage, and the DMA arbitration module determines whether the transmission is transmitted or received according to the information in the DMA register, so that the DMA transmitting channel is controlled to transmit data or the DMA receiving channel is controlled to receive data. If the DMA transmission channel is in the transmission process, the DMA arbitration module transmits control information, transmits the control information to a bus through an AXI host interface, and transmits 'permission to transmit' to the DMA transmission channel after the bus responds successfully; for the receiving process, it is similar to the transmitting process. Optionally, the DMA controller module in this example employs a descriptor-based DMA controller.

In this example, the FIFO controller module is connected between the DMA controller module and the MAC module, and is configured to provide a buffer for sending data and receiving data, so that data can be appropriately adjusted in the buffer, and the problem of clock domain crossing transmission of data during transmission can be effectively solved. The transmission memory and the receiving memory of the FIFO controller module are both realized by using FIFO, the FIFO queue is designed to be 8, the depth is set to be 1K, the data bit width is 128bit, and the signal between a read clock and a write clock belongs to cross-clock domain transmission during design, so that the two FIFOs are both asynchronous FIFOs and are provided with synchronous modules, can support simultaneous reading and writing, and can be formed by adopting dual-port RAMs.

Specifically, as an alternative implementation form, as shown in fig. 3, the FIFO controller module includes a FIFO transmission controller and a FIFO reception controller, which are respectively used for performing transmission and reception control. The memory queue of the FIFO sending controller is a sending FIFO, and the memory queue of the FIFO receiving controller is a receiving FIFO. The DMA sending channel and the DMA receiving channel are both 8, and are respectively in one-to-one correspondence with the sending FIFO queue and the receiving FIFO queue, the DMA sending channel is connected with the FIFO sending controller, and the DMA receiving channel is connected with the FIFO receiving controller. The FIFO sending controller is mainly responsible for reading data and control signals from the sending FIFO, and the FIFO receiving controller is mainly responsible for writing the data and control signals into the receiving FIFO so as to carry out data interaction with the DMA controller module and the MAC module.

The FIFO sending controller is used for buffering the sending data read by the host system memory and transmitted from the DMA sending channel through the DMA arbitration module in the sending FIFO and sending the sending data to the MAC controller module when the sending threshold of the FIFO buffer is reached. The FIFO receiving controller is used for caching the received data received by the MAC module in a receiving FIFO, transmitting the received data to a DMA receiving channel when the received data reaches a FIFO cache receiving threshold value, and sending the received data to a host system memory through the DMA arbitration module.

In this example, as shown in fig. 4, the MAC module includes a MAC transmission unit and a MAC reception unit, the FIFO transmission controller is connected to the MAC transmission unit, and the FIFO reception controller is connected to the MAC reception unit. The MAC sending unit is used for assembling the sending data transmitted by the FIFO sending controller into an Ethernet data frame and sending the Ethernet data frame to the physical layer PHY through a TBI interface/SGMII interface; the MAC receiving unit is used for receiving the data frame sent by the physical layer PHY from the TBI interface/SGMII interface and transmitting the data frame to the FIFO receiving controller.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and it is apparent that those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application.

Claims (10)

1. A gigabit Ethernet MAC controller capable of being integrated in an SoC system is characterized by comprising a DMA controller module, an FIFO controller module and an MAC module which are connected in sequence;

the DMA controller module is connected with a memory of the SoC system through an AXI host interface to carry out data interaction and is connected with the CPU through an APB slave interface for communication;

the FIFO controller module is connected between the DMA controller module and the MAC module and used for providing cache for sending data and receiving data;

the MAC module is connected with the physical layer PHY through a TBI interface/SGMII interface.

2. The gigabit ethernet MAC controller of claim 1 wherein the MAC module is configured to obtain the transmit data from the FIFO controller module and transmit the transmit data to the physical layer PHY; and is used to receive data from the physical layer PHY and transmit it to the FIFO controller module.

3. The gigabit Ethernet MAC controller according to claim 1, wherein the DMA controller module comprises a DMA arbitration module, a DMA transmit-receive channel connected to the DMA arbitration module, and a DMA register, the DMA register is connected to the DMA transmit-receive channel, and the DMA transmit-receive channel is connected to the FIFO controller module; the DMA arbitration module is connected with an AXI host interface, and the DMA register is connected with an APB slave interface.

4. The gigabit ethernet MAC controller of claim 3, wherein the DMA register is configured to obtain and store information written by the CPU through the APB slave interface, and the DMA arbitration module is configured to control the DMA transmit/receive channel according to the information in the DMA register.

5. The gigabit ethernet MAC controller of claim 3 wherein the DMA transmit/receive channel comprises a DMA transmit channel and a DMA receive channel, the FIFO controller module comprising a FIFO transmit controller and a FIFO receive controller;

the number of the DMA sending channels and the number of the DMA receiving channels are both 8, the DMA sending channels are respectively in one-to-one correspondence with the memory queues of the FIFO sending controller and the FIFO receiving controller, the DMA sending channels are connected with the FIFO sending controller, and the DMA receiving channels are connected with the FIFO receiving controller.

6. The gigabit ethernet MAC controller of claim 5, wherein the memory queue of the FIFO transmit controller is a transmit FIFO, the memory queue of the FIFO receive controller is a receive FIFO, the queues of the transmit FIFO and the receive FIFO are both 8, and are both asynchronous FIFOs with synchronous modules.

7. The gigabit ethernet MAC controller of claim 6 wherein the transmit FIFO and the receive FIFO are each implemented using dual port RAMs.

8. The gigabit ethernet MAC controller of claim 6, wherein the FIFO transmit controller is configured to buffer the transmit data transmitted from the DMA transmit channel in a transmit FIFO, and to transmit the buffered transmit data to the MAC controller module; the FIFO receiving controller is used for buffering the received data transmitted from the MAC module in the receiving FIFO and transmitting the buffered data to the DMA receiving channel.

9. The gigabit ethernet MAC controller of claim 5 wherein the MAC module comprises a MAC transmit unit and a MAC receive unit, the FIFO transmit controller being coupled to the MAC transmit unit and the FIFO receive controller being coupled to the MAC receive unit; the MAC sending unit and the MAC receiving unit are connected with the physical layer PHY through a TBI interface/SGMII interface.

10. The gigabit ethernet MAC controller of claim 9, wherein the MAC sending unit is configured to assemble the sending data transmitted by the FIFO sending controller into ethernet data frames, and send the ethernet data frames to the physical layer PHY through the TBI interface/SGMII interface; the MAC receiving unit is used for receiving the data frame sent by the physical layer PHY from the TBI interface/SGMII interface and transmitting the data frame to the FIFO receiving controller.

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