CN218769501U - Power semiconductor device - Google Patents
Power semiconductor device Download PDFInfo
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- CN218769501U CN218769501U CN202222314158.9U CN202222314158U CN218769501U CN 218769501 U CN218769501 U CN 218769501U CN 202222314158 U CN202222314158 U CN 202222314158U CN 218769501 U CN218769501 U CN 218769501U
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Abstract
The utility model discloses a power semiconductor device, include: a substrate having a first top surface; the first copper layer is connected to the first top surface, and an isolation through hole is formed in the first copper layer; and the two chip units are arranged on the first copper layer side by side, and the isolation through hole is positioned between the two chip units. The power semiconductor is provided with the isolation through holes between the chips arranged side by side, so that the thermal coupling of each chip is reduced from the angle of the interval, and the junction temperature of the chips is reduced.
Description
Technical Field
The utility model relates to the field of semiconductor technology, especially, relate to a power semiconductor device.
Background
To achieve high power output, the application of high power semiconductor devices is gradually replacing single chip devices. However, compared with a single-chip device, the heat conduction layer of the high-power semiconductor device is required to conduct heat power which is several times or even dozens of times higher than that of the single-chip device, so that the high-power semiconductor device has the problem of high junction temperature. The junction temperature distribution in the high-power semiconductor device is more complicated, and one part of the temperature rise of each chip is generated by the temperature rise of each chip, and the other part of the temperature rise of each chip is generated by the thermal coupling with other adjacent chips. High junction temperatures lead to accelerated failure and reduced lifetime of high power semiconductor devices.
SUMMERY OF THE UTILITY MODEL
Based on this, the present invention provides a power semiconductor device, which is provided with an isolation through hole between chips arranged side by side, and reduces the thermal coupling of each chip from an interval perspective, thereby reducing the junction temperature of each chip.
The utility model provides a pair of power semiconductor device, include:
a substrate having a first top surface;
the first copper layer is connected to the first top surface, and an isolation through hole is formed in the first copper layer;
and the two chip units are arranged on the first copper layer side by side, and the isolation through hole is positioned between the two chip units.
Further, the two chip units are arranged on the first copper layer side by side along the length direction of the substrate.
Further, the length direction of the chip unit is the same as the width direction of the substrate, and the length of the isolation through hole is smaller than that of the chip unit.
Furthermore, the chip unit is provided with a second top surface, a source electrode of the chip unit is arranged on the second top surface, the length direction of the source electrode is the same as that of the chip unit, and the length of the isolation through hole is not larger than that of the source electrode.
Further, the distance between the isolation through hole and the two chip units is equal.
Further, the width of the isolation through hole is not more than 50% of the distance between the two chip units.
Furthermore, the second top surface is connected with a cushion block, the cushion block is provided with a third top surface and a third bottom surface which are oppositely arranged, and the third bottom surface is connected to the source electrode through a first sintered silver layer.
Furthermore, the cushion block is made of copper-molybdenum alloy.
Further, the length of the buffer cushion block is equal to that of the source electrode.
Further, the lead frame comprises a first connecting plate and a second connecting plate; the substrate is provided with a first bottom surface opposite to the first top surface, the first top surface is also connected with a second copper layer, and the first bottom surface is connected with a third copper layer;
the first connecting plate is connected with the first copper layer, and the second connecting plate is connected to the third top surface through a second sintered silver layer;
the second top surface of the chip unit is also provided with a grid electrode of the chip unit, and the grid electrode of the chip unit is connected with the second copper layer through a first bonding lead;
the chip unit is provided with a second bottom surface, a drain electrode of the chip unit is arranged on the second bottom surface, and the drain electrode of the chip unit is connected to the first copper layer through a third sintered silver layer.
The utility model provides a power semiconductor device, it is provided with the isolation through-hole between the chip that sets up side by side, has reduced the thermal coupling of each chip from the spaced angle to further reduce the junction temperature of each chip; the utility model further limits the length and width of the isolation through hole to ensure that the heat dissipation of the isolation through hole is not reduced while the heat conduction efficiency is not reduced; the utility model also effectively avoids the problem of reliability failure caused by the difference of larger thermal expansion coefficients between the lead frame and the chip by arranging the buffer cushion block between the chip and the lead frame, wherein the thermal expansion coefficient of the buffer cushion block is between the lead frame and the chip; finally, the utility model discloses still connect chip and copper layer, chip and cushion block respectively through the sintering silver layer, cushion block and lead frame have improved the overall stability of device, and then have improved power semiconductor device's life.
For a better understanding and practice, the invention is described in detail below with reference to the accompanying drawings.
Drawings
Fig. 1 is a schematic structural diagram of a power semiconductor device according to an embodiment of the present invention;
FIG. 2 is a top view of FIG. 1;
fig. 3 is a schematic diagram of an embodiment of the present invention with the lead frame removed;
FIG. 4 is a top view of FIG. 3;
fig. 5 is an enlarged view of a portion of the structure of fig. 1.
Reference numerals: 1. a substrate; 11. a first top surface; 12. a first bottom surface; 21. a first copper layer; 22. a second copper layer; 23. isolating the through holes; 24. a third copper layer; 3. a chip unit; 31. a first bonding wire; 32. a second bonding wire; 33. a source electrode; 4. a lead frame; 41. a first connecting plate; 42. a second connecting plate; 43. a third connecting plate; 5. cushion the cushion.
Detailed Description
It should be understood that the embodiments described are only some embodiments of the present application, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the embodiments in the present application.
The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of the present application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the application, as detailed in the claims that follow. In the description of the present application, it is to be understood that the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not necessarily used to describe a particular order or sequence, nor are they to be construed as indicating or implying relative importance. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
Further, in the description of the present application, "a plurality" means two or more unless otherwise specified. "and/or" describes the association relationship of the associated object, indicating that there may be three relationships, for example, a and/or B, which may indicate: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.
It is to be understood that the embodiments of the present application are not limited to the precise arrangements described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the embodiments of the present application is limited only by the following claims.
To address the technical problems in the background art, referring to fig. 1 to 3, the present invention provides a power semiconductor device, which, in one embodiment, includes a substrate 1, a first copper layer 21, and two chip units 3. The substrate 1 includes a first top surface 11 and a first bottom surface 12, a first copper layer 21 is connected to the first top surface 11, and an isolation via 23 is disposed on the first copper layer 21. Two chip units 3 are arranged side by side on the first copper layer 21, and an isolation via 23 is located between the two chip units 3.
Wherein, the utility model discloses a chip unit 3 can be one or more of silicon-based chip, carborundum-based chip or gallium nitride-based chip, and it can be IGBT chip, DIODE chip, HEMT chip or MOSFET chip. The substrate 1 may be a ceramic plate or other insulating and thermally conductive plate.
The embodiment of the utility model provides a through set up isolation through-hole 23 between two chip units 3, reduced every chip unit 3's thermal coupling from the spaced angle to every chip unit 3's junction temperature has been reduced.
The arrangement of the two chip units 3 can be determined according to the requirement, and referring to fig. 3, preferably, the two chip units 3 are arranged on the first copper layer 21 side by side along the length direction of the substrate 1, so as to reduce the area of the substrate 1, and further reduce the area of the whole power chip.
Since too large a length of the isolation via 23 will sacrifice too much heat conducting area of the first copper layer 21, and the area of the current path of the first copper layer 21 is reduced, and the current density is too large, which will result in the overall heat conducting efficiency of the power semiconductor device being reduced, in a specific embodiment, as shown in fig. 1-3, the length direction of the chip unit 3 is the same as the width direction of the substrate 1, and the length of the isolation via 23 is smaller than the length of the chip unit 3. Preferably, the chip unit 3 has a second top surface, the second top surface is provided with a source 33 of the chip unit 3, the length direction of the source 33 is the same as the length direction of the chip unit 3, and the length of the isolation through hole 23 is not greater than the length of the source 33.
Referring to fig. 3 and 4, in a specific embodiment, in order to ensure that two independent chip units 3 can uniformly dissipate heat, the distance between the isolation through hole 23 and the two chip units 3 is equal. Preferably, the width of the isolation via 23 is not more than 50% of the distance between two chip units 3.
The first copper layer 21 where the isolated via 23 is located serves to conduct heat, and the larger its area, the smaller the current density, and the higher its heat conduction efficiency. The provision of the isolation via 23 is equivalent to reducing the heat conducting area of the first copper layer 21, and therefore, the width and length of the isolation via 23 are correspondingly limited, so that the isolation via 23 does not reduce the heat conducting efficiency of the power semiconductor device while reducing the thermal coupling between chips.
As shown in fig. 1 and 5, the power semiconductor device further includes a lead frame 4, the lead frame 4 including a first connection plate 41, a second connection plate 42, and a third connection plate 43; the first top surface 11 of the substrate 1 is connected to a second copper layer 22 and the first bottom surface 12 is connected to a third copper layer 24. A first connection plate 41 is connected to the first copper layer 21 and a second connection plate 42 is connected to the second top surface of the chip unit 3 via a second sintered silver layer.
Correspondingly, the second top surface of the chip unit 3 is further provided with a gate, the second bottom surface of the chip unit 3 is provided with a drain, the first connection board 41 is connected with the drain of the chip unit 3 through the first copper layer 21, the second connection board 42 is connected with the source 33 on the second top surface of the chip unit 3 through the second sintered silver layer, the gate of the chip unit 3 is connected to the second copper layer 22 through the first bonding wire 31, and the second copper layer 22 is connected to the third connection board 43 through the second bonding wire 32.
It should be noted that, in fig. 1, 2 and 5, the first connecting plate 41, the second connecting plate 42 and the third connecting plate 43 of the lead frame 4 are connected together, and after the power semiconductor device package of the present invention is completed, the connection portions between the first connecting plate 41, the second connecting plate 42 and the third connecting plate 43 are not included.
The chip unit 3 generates a large amount of heat in the application process, and the difference between the thermal expansion coefficients of the copper material of the lead frame 4 and the material of the chip is large, so that the reliability of the chip unit 3 and the lead frame 4 is failed due to thermal stress. Therefore, in a preferred embodiment, as shown in fig. 5, a cushion block 5 is connected to the second top surface of the chip unit 3, the cushion block 5 has a third top surface and a third bottom surface which are oppositely arranged, and the third bottom surface is connected to the source electrode 33 through the first sintered silver layer for leading out the source electrode 33 of the chip unit 3. Preferably, the material of the cushion block 5 may be copper-molybdenum alloy, and the thermal expansion coefficient of the cushion block is between copper metal and silicon carbide, so that the thermal stress of the lead frame 4 and the chip can be effectively relaxed.
In a specific embodiment, the length of the buffer pad is equal to the length of the source 33. The cushion block 5 is connected to the source 33 of the chip unit 3, so that the cushion block 5 only needs to cover the source 33, and the heat dissipation of the chip is affected by the too large area, and the stress of the chip is uneven.
In a specific embodiment, the drain electrode of the chip unit 3 is also connected to the first copper layer 21 by a third sintered silver layer. The heat conduction and electric conduction effects of the sintered silver layer are far stronger than those of the conventional tin-silver-copper alloy. The voidage control effect of the silver-copper alloy is better than that of a tin-silver-copper alloy, the sintered silver layer after molding is pure silver, the melting point is as high as 961 ℃, and the silver-silver alloy has extremely strong shear strength. The welding effect greatly improves the reliability of the power semiconductor device.
Preferably, the lead frame 4 of the embodiment of the present invention may be copper metal.
The utility model provides a power semiconductor device, it is provided with the isolation through-hole between the chip that sets up side by side, has reduced the thermal coupling of each chip from the spaced angle to further reduce the junction temperature of each chip; the utility model further limits the length and width of the isolation through hole to ensure that the heat radiation is not reduced in heat conduction efficiency; the utility model also effectively avoids the problem of reliability failure caused by the difference of larger thermal expansion coefficients between the lead frame and the chip by arranging the buffer cushion block between the chip and the lead frame, wherein the thermal expansion coefficient of the buffer cushion block is between the lead frame and the chip; finally, the utility model discloses still connect chip and copper layer, chip and cushion block respectively through the sintering silver layer, cushion block and lead frame have improved the overall stability of device, and then have improved power semiconductor device's life.
The above examples only represent preferred embodiments of the present invention, which are described in more detail and detail, but not to be construed as limiting the scope of the invention. It should be noted that, to those skilled in the art, changes and modifications may be made without departing from the spirit of the invention, and it is intended that the invention also encompass such changes and modifications.
Claims (10)
1. A power semiconductor device, comprising:
a substrate having a first top surface;
the first copper layer is connected to the first top surface, and an isolation through hole is formed in the first copper layer;
and the two chip units are arranged on the first copper layer side by side, and the isolation through hole is positioned between the two chip units.
2. The power semiconductor device of claim 1, wherein: the two chip units are arranged on the first copper layer side by side along the length direction of the substrate.
3. The power semiconductor device of claim 2, wherein: the length direction of the chip unit is the same as the width direction of the substrate, and the length of the isolation through hole is smaller than that of the chip unit.
4. The power semiconductor device of claim 3, wherein: the chip unit is provided with a second top surface, the second top surface is provided with a source electrode of the chip unit, the length direction of the source electrode is the same as that of the chip unit, and the length of the isolation through hole is not larger than that of the source electrode.
5. The power semiconductor device according to any one of claims 1 to 4, characterized in that: the distance between the isolation through hole and the two chip units is equal.
6. The power semiconductor device according to any one of claims 1 to 4, characterized in that: the width of the isolation through hole is not more than 50% of the distance between the two chip units.
7. The power semiconductor device of claim 4, wherein: the second top surface is connected with a cushion block, the cushion block is provided with a third top surface and a third bottom surface which are oppositely arranged, and the third bottom surface is connected to the source electrode through a first sintered silver layer.
8. The power semiconductor device of claim 7, wherein: the cushion block is made of copper-molybdenum alloy.
9. The power semiconductor device of claim 7, wherein: the length of the buffer cushion block is equal to that of the source electrode.
10. The power semiconductor device of claim 7, wherein: the lead frame comprises a first connecting plate and a second connecting plate; the substrate is provided with a first bottom surface opposite to the first top surface, the first top surface is also connected with a second copper layer, and the first bottom surface is connected with a third copper layer;
the first connecting plate is connected with the first copper layer, and the second connecting plate is connected to the third top surface through a second sintered silver layer;
the second top surface of the chip unit is also provided with a grid electrode of the chip unit, and the grid electrode of the chip unit is connected with the second copper layer through a first bonding lead;
the chip unit is provided with a second bottom surface, the second bottom surface is provided with a drain electrode of the chip unit, and the drain electrode of the chip unit is connected to the first copper layer through a third sintered silver layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222314158.9U CN218769501U (en) | 2022-08-31 | 2022-08-31 | Power semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222314158.9U CN218769501U (en) | 2022-08-31 | 2022-08-31 | Power semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218769501U true CN218769501U (en) | 2023-03-28 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222314158.9U Active CN218769501U (en) | 2022-08-31 | 2022-08-31 | Power semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN218769501U (en) |
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2022
- 2022-08-31 CN CN202222314158.9U patent/CN218769501U/en active Active
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