CN218587186U

CN218587186U - Multiplexing circuit of Ethernet interface and serial interface, electronic equipment

Info

Publication number: CN218587186U
Application number: CN202223103416.5U
Authority: CN
Inventors: 温沛涛
Original assignee: Guangzhou Haige Communication Group Inc Co
Current assignee: Guangzhou Haige Communication Group Inc Co
Priority date: 2022-11-22
Filing date: 2022-11-22
Publication date: 2023-03-07
Anticipated expiration: 2032-11-22

Abstract

The utility model provides a multiplexing circuit, electronic equipment of ethernet interface and serial interface belongs to communication interface circuit technical field. Wherein, this ethernet interface and serial interface's multiplexing circuit includes: the system comprises an RJ45 socket, an Ethernet interface chip, a serial interface chip and a selection circuit; pins 1 and 2 of the RJ45 socket are connected with the Ethernet interface chip; pins 3 and 6 of the RJ45 socket are connected with a first input end of the selection circuit; pins 4 and 5 of the RJ45 socket are connected with the second input end of the selection circuit; the first output end of the selection circuit is connected with the Ethernet interface chip; the second output end of the selection circuit is connected with the serial interface chip. The utility model provides a multiplexing circuit, the electronic equipment of ethernet interface and serial interface can realize multiplexing the RJ45 socket for ethernet interface and serial interface, can save a RJ45 socket, can save the resource-saving, can save the panel area, and the cost is lower.

Description

Multiplexing circuit of Ethernet interface and serial interface, electronic equipment

Technical Field

The utility model relates to a communication interface circuit technical field especially relates to a multiplexing circuit, electronic equipment of ethernet interface and serial interface.

Background

The electronic device may have various communication interfaces, such as an ethernet Interface (i.e., RJ45 Interface), a Serial Interface (e.g., RS232 Interface or RS485 Interface), a Universal Serial Bus (USB) Interface, a High Definition Multimedia Interface (HDMI), a Digital Video Interface (DVI), or the like.

However, with the function enrichment or miniaturization of the electronic device, the space available for setting the communication interface of the electronic device is limited, and meanwhile, the RS232 interface and the RJ45 interface are reserved, which causes the waste of resources such as cost, interface, space area and circuit board.

SUMMERY OF THE UTILITY MODEL

The utility model provides a multiplexing circuit, electronic equipment of ethernet interface and serial interface for there is the defect of wasting of resources among the solution prior art, realize resources are saved.

The utility model provides a multiplexing circuit of ethernet interface and serial interface, include: the system comprises an RJ45 socket, an Ethernet interface chip, a serial interface chip and a selection circuit;

pins

1 and 2 of the RJ45 socket are connected with the Ethernet interface chip;

pins

3 and 6 of the RJ45 socket are connected with the first input end of the selection circuit;

pins

4 and 5 of the RJ45 socket are connected with the second input end of the selection circuit; the first output end of the selection circuit is connected with the Ethernet interface chip; and the second output end of the selection circuit is connected with the serial interface chip.

According to the utility model provides a pair of ethernet interface and serial interface's multiplex circuit 4 pins and 5 pins of RJ45 socket to under the condition that the input of selection circuit's second input is first level, selection circuit's first input with switch on between selection circuit's the first output.

According to the utility model provides a pair of ethernet interface and serial interface's multiplex circuit 4 pins and 5 pins of RJ45 socket to under the condition that the input of selection circuit's second input is the second level, selection circuit's first input with switch on between selection circuit's the second output.

According to the utility model provides a multiplexing circuit of ethernet interface and serial interface, the selection circuit includes reverse circuit and switch chip;

the input end of the reverse circuit is a second input end of the selection circuit; the output end of the reverse circuit is connected with the second input end of the switch chip; the first input end of the switch chip is the first input end of the selection circuit; the first output end of the switch chip is the first output end of the selection circuit; and the second output end of the switch chip is the second output end of the selection circuit.

According to the utility model provides a pair of ethernet interface and serial interface's multiplexing circuit, the reverse circuit includes triode or field effect transistor.

According to the utility model provides a multiplexing circuit of ethernet interface and serial interface, the reversal circuit includes first triode; the first triode is an NPN triode;

the base electrode of the first triode is the input end of the reverse circuit; the collector of the first triode is the output end of the reverse circuit; the base electrode of the first triode is connected with a first power supply through a first resistor; the emitting electrode of the first triode is grounded; and the collector of the first triode is connected with the first power supply through a second resistor.

According to the utility model provides a multiplexing circuit of ethernet interface and serial interface, the first input of switch chip includes first terminal and second terminal;

the first terminal is connected with a pin3 of the RJ45 socket; the second terminal is connected with a 6 pin of the RJ45 jack.

According to the utility model provides a multiplexing circuit of ethernet interface and serial interface, the first output of switch chip includes third terminal and fourth terminal;

and when the input of the 4 pin and the 5 pin of the RJ45 socket to the second input end of the selection circuit is at the first level, the first terminal and the third terminal are conducted, and the second terminal and the fourth terminal are conducted.

According to the utility model provides a multiplexing circuit of ethernet interface and serial interface, the second output of switch chip includes fifth terminal and sixth terminal;

and under the condition that the input of the 4 pins and the 5 pins of the RJ45 socket to the second input end of the selection circuit is of a second level, the first terminal is conducted with the fifth terminal, and the second terminal is conducted with the sixth terminal.

The utility model also provides an electronic equipment, include as above-mentioned any one the multiplex circuit of ethernet interface and serial interface.

The utility model provides an ethernet interface and serial interface's multiplex circuit, electronic equipment, through 1 pin and 2 pins and the ethernet interface chip with the RJ45 socket be connected, 3 pins and 6 pins of RJ45 socket are connected with selection circuit's first input, 4 pins and 5 pins of RJ45 socket are connected with selection circuit's second input, selection circuit's first output and ethernet interface chip are connected, selection circuit's second output and serial interface chip are connected, can realize multiplexing to ethernet interface and serial interface with the RJ45 socket, can save a RJ45 socket, can resources are saved, can save the panel area, and the cost is lower.

Drawings

In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is one of schematic structural diagrams of a multiplexing circuit of an ethernet interface and a serial interface provided by the present invention;

fig. 2 is a schematic diagram illustrating pin definitions of RJ45 sockets in a multiplexing circuit of an ethernet interface and a serial interface provided by the present invention;

fig. 3 is a schematic diagram illustrating pin definitions of RJ45 to RS232 in a multiplexing circuit of an ethernet interface and a serial interface according to the present invention;

fig. 4 is a second schematic structural diagram of the multiplexing circuit of the ethernet interface and the serial interface provided by the present invention;

fig. 5 is a schematic diagram of an internal circuit of a switch chip in the multiplexing circuit of the ethernet interface and the serial interface provided by the present invention.

Reference numerals:

101: an RJ45 jack; 102: an Ethernet interface chip; 103: a serial interface chip; 104: a selection circuit; 401: an inverter circuit; n1: a switch chip; v1: a first triode; r1: a first resistor; r2: a second resistor; VCC: a first power supply.

Detailed Description

To make the objects, technical solutions and advantages of the present invention clearer, the drawings of the present invention are combined to clearly and completely describe the technical solutions of the present invention, and obviously, the described embodiments are some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

In the description of the embodiments of the present invention, it should be noted that the terms "center", "length", "width", "height", "upper", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are only for convenience of describing the embodiments of the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance, and not order.

In the description of the embodiments of the present invention, it should be noted that unless explicitly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the embodiments of the present invention can be understood as specific cases to those of ordinary skill in the art.

The present invention provides a multiplexing circuit and an electronic device for ethernet interface and serial interface, which are described below with reference to fig. 1 to 5.

Fig. 1 is one of the schematic structural diagrams of the multiplexing circuit of the ethernet interface and the serial interface provided in the present invention. As shown in fig. 1, the multiplexing circuit of the ethernet interface and the serial interface includes: RJ45 jack 101, ethernet interface chip 102, serial interface chip 103, and selection circuit 104.

Specifically, different from the mode that ethernet interface chip and serial interface chip used an independent RJ45 socket respectively in traditional electronic equipment, the embodiment of the utility model provides an in, ethernet interface chip 102 and serial interface chip 103 share an RJ45 socket, this RJ45 socket is RJ45 socket 101.

The RJ45 jack 101 includes 8 pins (pins), which are 1, 2, 3, 4, 5, 6, 7, and 8 pins (i.e., pin1, pin2, pin3, pin4, pin5, pin6, pin7, and pin 8).

The ethernet interface chip 102 is configured to perform communication based on an ethernet interface, so as to implement data transceiving. An ethernet interface, which may be connected to a network (e.g., the internet or a local area network, etc.).

The ethernet interface Chip 102 may be a System on Chip (SoC), a Central Processing Unit (CPU), or a Micro Control Unit (MCU).

And the serial interface chip 103 is used for performing communication based on a serial communication interface to realize data transceiving. The serial communication interface can be used as a debugging port and used for debugging equipment and the like.

Optionally, the serial interface chip 103 may be used for communication based on RS232 protocol.

Alternatively, the Ethernet interface chip 102 and the serial interface chip 103 may be implemented by the same chip.

The selection circuit 104 is electrically connected to the RJ45 jack 101, the ethernet interface chip 102, and the serial interface chip 103, respectively. And the selection circuit 104 is used for selecting the RJ45 socket 101 to be conducted with the Ethernet interface chip 102 or the serial interface chip 103.

It can be understood that, in the case that the RJ45 jack 101 is connected to the ethernet interface chip 102, the RJ45 jack 101 implements the function of the ethernet interface; when the RJ45 jack 101 is electrically connected to the serial interface chip 103, the RJ45 jack 101 functions as a serial interface.

Pins

1 and 2 of the RJ45 socket 101 are connected to an ethernet interface chip 102;

pins

3 and 6 of the RJ45 jack 101 are connected to a first input of the selection circuit 104;

pins

4 and 5 of the RJ45 jack 101 are connected to a second input of the selection circuit 104; a first output terminal of the selection circuit 104 is connected to the ethernet interface chip 102; a second output terminal of the selection circuit 104 is connected to the serial interface chip 103.

Specifically, fig. 2 is a schematic diagram illustrating pin definitions of RJ45 sockets in the multiplexing circuit of the ethernet interface and the serial interface provided by the present invention. As shown in fig. 2, the definition of each pin of the RJ45 socket 101 is the same as that of the RJ45 protocol, i.e. the

pins

1, 2, 3, 4, 5, 6, 7, and 8 are a positive data transmission pin (TxData + or TX +), a negative data transmission pin (TxData-or TX-), a positive data reception pin (RxData + or RX +), an empty pin NC1, an empty pin NC2, a negative data reception pin (RxData-or RX-), an empty pin NC3, and an empty pin NC4, respectively.

It is understood that the RJ45 jack 101 further includes two pins EP1 and EP2, which are formed in a standardized manner, and are respectively connected to pads G1 and G2 of a PCB (Printed circuit board).

Fig. 3 is a schematic diagram illustrating pin definitions of RJ45 to RS232 in the multiplexing circuit of the ethernet interface and the serial interface according to the present invention. As shown in fig. 3, in order to realize the conversion between the RJ45 protocol and the RS232 protocol,

pins

2, 3, and 5 of the 9-pin RS232 interface respectively correspond to

pins

3, 6, and 4-5 of the RJ45 interface, and respectively serve as a data transmission pin (TX), a data reception pin (DX), and a ground pin. I.e., 3 pins and 6 pins of the RJ45 jack 101, are multiplexed for data transmission based on the RS232 protocol.

In the embodiment of the present invention, the 4-5 pins of the RJ45 jack 101 are connected to the same network, defined as detecting (Detect) pins, and used for detecting whether the data transmitted by the RJ45 jack is based on the RJ45 protocol or the RS232 protocol. Therefore, as shown in fig. 2, the signals transmitted by pins 1-6 of the RJ45 jack 101 may be denoted as TXD _ P, TXD _ N, RXD _ P/TX, detect, RXD _ N/RX, respectively.

The 1 pin and the 2 pin of the RJ45 jack 101 are connected to the ethernet interface chip 102, and specifically may be connected to two pins (i.e., the TXD _ P pin and the TXD _ N pin) of a set of transmit-receive signal pins of the ethernet interface chip 102, respectively.

Optionally, pin1 of the RJ45 jack 101 may be connected to pin TXD _ P of the ethernet interface chip 102, and pin2 of the RJ45 jack 101 may be connected to pin TXD _ N of the ethernet interface chip 102; alternatively, pin1 of the RJ45 jack 101 may be connected to pin TXD _ N of the Ethernet interface chip 102, and pin2 of the RJ45 jack 101 may be connected to pin TXD _ P of the Ethernet interface chip 102.

Pins

3 and 6 of the RJ45 jack 101 are connected to a first input of the selection circuit 104 for transmitting data. The first output terminal of the selection circuit 104 is connected to the ethernet interface chip 102, and specifically, may be connected to two pins (i.e., RXD _ P pin and RXD _ N pin) of another set of transceiving signal pins of the ethernet interface chip 102, respectively.

The second output terminal of the selection circuit 104 is connected to the serial interface chip 103, and specifically may be connected to two pins (i.e., the TX pin and the RX pin) of a group of transceiving signal pins of the serial interface chip 103, respectively.

Both pins 4 and 5 of the RJ45 jack 101 are connected to a second input of the selection circuit 104. The selection circuit 104 may select to connect the first input terminal of the selection circuit 104 with the first output terminal of the selection circuit 104 or to connect the second output terminal of the selection circuit 104 based on a signal input to the second input terminal of the RJ45 jack selection circuit 104, so as to correspondingly connect the RJ45 jack 101 with the ethernet interface chip 102 or the serial interface chip 103.

The Ethernet function and the serial port function of the RJ45 socket 101 are different in the level condition of a pin4-5 (namely a pin 4-5), the Ethernet function is suspended when the Ethernet function is realized, and the Ethernet function is low level when the Ethernet function is used as a serial port to connect an external RS232 wire, so that the Ethernet function or the serial port function can be determined by using different levels of the pin4-5 when the wire is inserted into the RJ45 socket 101.

Under the condition that the first input end of the selection circuit 104 is conducted with the first output end of the selection circuit 104, the RJ45 socket 101 is conducted with the ethernet interface chip 102 to perform data transmission based on the ethernet interface; when the first input terminal of the selection circuit 104 is electrically connected to the second output terminal of the selection circuit 104, the RJ45 jack 101 is electrically connected to the serial interface chip 103, and data transmission is performed through the RS232 interface.

The embodiment of the utility model provides a be connected with ethernet interface chip through 1 pin and 2 pins with the RJ45 socket, 3 pins and 6 pins of RJ45 socket are connected with selection circuit's first input, 4 pins and 5 pins of RJ45 socket are connected with selection circuit's second input, selection circuit's first output and ethernet interface chip are connected, selection circuit's second output and serial interface chip are connected, can realize multiplexing the RJ45 socket into ethernet interface and serial interface, can save a RJ45 socket, can resources are saved, can save the panel area, and the cost is lower.

Based on the content of any of the above embodiments, when the input of the 4 pin and the 5 pin of the RJ45 jack 101 to the second input terminal of the selection circuit 104 is at the first level, conduction is conducted between the first input terminal of the selection circuit 104 and the first output terminal of the selection circuit 104.

Specifically, the first level may be a low level, and the second level may be a high level, that is, the first level is lower than the second level; alternatively, the first level may be a high level and the second level may be a low level, i.e., the first level is higher than the second level.

When the level input to the second input terminal of the selection circuit 104 by the 4 pins and the 5 pins of the RJ45 socket 101 is the first level, it indicates that the 4 pins and the 5 pins of the RJ45 socket 101 are floating or in a high impedance state, which conforms to the RJ45 protocol, and the selection circuit 104 may select to connect the first input terminal of the selection circuit 104 and the first output terminal of the selection circuit 104.

The embodiment of the utility model provides a through 4 pins and 5 pins at the RJ45 socket under the condition that the input of second input to the select circuit is first level, switch on between the first input of select circuit and the first output of select circuit, utilize the level of 4 pins and 5 pins of RJ45 socket to carry out the logic judgement, the logic judgement is simpler, design cost is lower.

Based on the content of any of the above embodiments, when the input of the 4 pin and the 5 pin of the RJ45 jack 101 to the second input terminal of the selection circuit 104 is at the second level, conduction is conducted between the first input terminal of the selection circuit 104 and the second output terminal of the selection circuit 104.

Specifically, when the level input to the second input terminal of the selection circuit 104 by the pin4 and the pin5 of the RJ45 socket 101 is the second level, it is described that the pin4 and the pin5 of the RJ45 socket 101 are ground pins (GND) and conform to the RS232 protocol, and the selection circuit 104 may select to conduct between the first input terminal of the selection circuit 104 and the second output terminal of the selection circuit 104.

The embodiment of the utility model provides a be under the condition of second level through 4 pins and 5 pins at the RJ45 socket to the input of selection circuit's second input, switch on between selection circuit's the first input and the second output of selection circuit, utilize the level of 4 pins and 5 pins of RJ45 socket to carry out logic judgement, the logic judgement is simpler, and design cost is lower.

Fig. 4 is a second schematic structural diagram of the multiplexing circuit of the ethernet interface and the serial interface according to the present invention. Based on the content of any of the above embodiments, as shown in fig. 4, the selection circuit 104 includes the inverter circuit 401 and the switch chip N1.

Specifically, the selection circuit 104 may include an inverter circuit 401 and a switch chip N1. The inverter circuit 401 is connected to the switch chip N1.

An inverting circuit 401 inverts the input level. That is, when the level input to the inverter circuit 401 is high, the level output from the inverter circuit 401 is low, and when the level input to the inverter circuit 401 is low, the level output from the inverter circuit 401 is high.

The switch chip N1 is used as an analog switch to selectively connect the first input terminal of the selection circuit 104 to the first output terminal of the selection circuit 104 or connect the second output terminal of the selection circuit 104. Namely, the switch chip N1, can switch two pairs of signals RXD _ P/RXD _ N and TX/RX.

The input terminal of the inverting circuit 401 is the second input terminal of the selection circuit 104; the output end of the reverse circuit 401 is connected with the second input end of the switch chip N1; the first input terminal of the switch chip N1 is the first input terminal of the selection circuit 104; a first output end of the switch chip N1 is a first output end of the selection circuit 104; a second output terminal of the switch chip N1 is a second output terminal of the selection circuit 104.

Specifically, an input terminal of the inverting circuit 401 serves as a second input terminal of the selection circuit 104, and is connected to the 4 pins and 5 pins of the RJ45 jack 101.

The output end of the inverting circuit 401 is connected to the second input end of the switch chip N1, so as to enable the switch chip N1 to select to switch on the first input end of the switch chip N1 with the first output end of the switch chip N1 or switch on the second output end of the switch chip N1 based on the signal input by the second input end of the switch chip N1, thereby correspondingly implementing to switch on the first input end of the selection circuit 104 with the first output end of the selection circuit 104 or switch on the second output end of the selection circuit 104.

A first input end of the switch chip N1 is used as a first input end of the selection circuit 104, and is connected with

pins

3 and 6 of the RJ45 socket 101; a first output end of the switch chip N1 is used as a first output end of the selection circuit 104, and is connected to the ethernet interface chip 102; a second output terminal of the switch chip N1 is connected to the serial interface chip 103 as a second output terminal of the selection circuit 104.

The embodiment of the utility model provides a through reverse circuit and switch chip, can realize utilizing 4 pins of RJ45 socket and the level of 5 pins to carry out the logic and judge, be ethernet interface and serial interface with the multiplexing of RJ45 socket, can save a RJ45 socket, can resources are saved, can save the panel area, the cost is lower.

Based on the content of any of the above embodiments, the inverting circuit 401 includes a triode or a field effect transistor.

Specifically, the inverter circuit 401 may be implemented based on a transistor or a field effect transistor, and thus the inverter circuit 401 may include at least one transistor or at least one field effect transistor.

The embodiment of the utility model provides a realize through triode or field effect transistor that the level is reverse, can confirm the level of 4 pins and 5 pins of RJ45 socket to selection circuit's second input more accurately to the selection realizes ethernet function or serial ports function, can multiplex the RJ45 socket into ethernet interface and serial interface more accurately, can save a RJ45 socket, can resources are saved, can save the panel area, and the cost is lower.

Based on the content of any of the above embodiments, as shown in fig. 4, the inverting circuit 401 includes a first transistor V1; the first transistor V1 is an NPN transistor.

In particular, the inverting circuit 401 may comprise a first transistor V1, implementing level inversion in the form of a classical transistor inverting circuit.

Alternatively, the first transistor V1 may be an NPN transistor.

The base of the first triode V1 is the input of the inverting circuit 401; the collector of the first triode V1 is the output of the inverter circuit 401; the base electrode of the first triode V1 is connected with a first power supply VCC through a first resistor R1; the emitting electrode of the first triode V1 is grounded; the collector of the first triode V1 is connected to the first power VCC through a second resistor R2.

Specifically, the first power source VCC is connected to the base of the first transistor V1 through a first resistor R1. The base of the first transistor V1 also serves as an input of the inverting circuit 401, and is connected to

pins

4 and 5 of the RJ45 jack. The first power VCC is also connected to the collector of the first transistor V1 via a second resistor R2. The emitter of the first triode V1 is grounded.

A classic triode inverter circuit can be formed by the above-described connection of the base, emitter and collector of the first triode V1.

When no external signal is inserted, the Detect pin is suspended, the B pole (base) of the V1 is pulled high through the R1, at the moment, the V1 is conducted, and the reverse circuit 401 outputs a first level which can represent 0; when the Detect pin is at a low level, V1 is not turned on, and the inverter circuit 401 outputs a second level, which may represent a 1.

To the resistance of the first resistor R1, the embodiment of the present invention is not limited specifically. Illustratively, the first resistor R1 may be 1k ohms.

To the resistance of second resistance R2, the embodiment of the present invention is not specifically limited. The resistance of the second resistor R2 may be the same as or different from the resistance of the first resistor R1. Illustratively, the second resistor R2 may be 1k ohms.

The embodiment of the utility model provides a realize the reverse circuit through first triode, circuit structure is simpler, and design cost is lower.

Fig. 5 is a schematic diagram of an internal circuit of a switch chip in the multiplexing circuit of the ethernet interface and the serial interface provided by the present invention. Based on the content of any of the above embodiments, as shown in fig. 5, the first input terminal of the switch chip N1 includes a first terminal and a second terminal.

Specifically, the switch chip N1 may be a SW chip.

The switch chip N1 may include a plurality of terminals. Alternatively, the switch chip N1 may include the following terminals: a plurality of input terminals (DA, DB, DC, DD, IN), a plurality of input terminals (S1A, S2A, S1B, S2B, S1C, S2C, S1D, S2D), an enable terminal

A ground terminal GND and a terminal V +. Wherein the terminals DA, DB, DC, DD, IN, S1A, S2A, S1B, S2B, S1C, S2C, S1D, S2D,

The pin numbers of GND and V + are respectively 4, 7, 9, 12, 1, 2, 3, 5, 6, 11, 10 and 14. 13, 15, 8 and 16. The terminal DA is connected to the terminal S1A through a first switch, and is connected to the terminal S2A through a second switch; the terminal DB is connected to the terminal S1B through a third switch and to the terminal S2B through a fourth switch; the terminal DC is connected to the terminal S1C through the fifth switch and to the terminal S2C through the sixth switch; the terminal DD is connected to the terminal S1D through the seventh switch and to the terminal S2D through the eighth switch; the driver (or decoder) may be based on the terminals IN and

the input signal controls the open and close states of the first to eighth switches; terminal with a terminal body

And is grounded.

The function table of the switch chip N1 may be as shown in table 1.

TABLE 1 function table of switch chip N1

The terminal DA and the terminal DB are a first terminal and a second terminal, respectively. The terminal DA and the terminal DB may serve as a first input terminal of the switch chip N1; the terminal IN may be connected to the output terminal of the inverter circuit 401 as a second input terminal of the switch chip N1.

The first terminal is connected with a pin3 of the RJ45 socket 101; the second terminal is connected to 6 pins of the RJ45 jack 101.

Specifically, 3 pins of the RJ45 jack 101 may be connected to a terminal DA of the switch chip N1, and 6 pins of the RJ45 jack 101 may be connected to a terminal DB of the switch chip N1, so as to perform a group of signal transceiving of the RJ45 interface or perform signal transceiving of the RS232 interface.

Based on the content of any of the above embodiments, as shown in fig. 5, the first output terminal of the switch chip N1 includes a third terminal and a fourth terminal.

Specifically, the terminal S1A and the terminal S1B are a third terminal and a fourth terminal, respectively. The terminal S1A and the terminal S1B may serve as a first output terminal of the switch chip N1.

When the input to the second input terminal of the selection circuit 104 is at the first level, the 4 pin and the 5 pin of the RJ45 jack 101 are turned on between the first terminal and the third terminal, and between the second terminal and the fourth terminal.

Specifically, when the 4 pin and the 5 pin of the RJ45 jack 101 input the first level to the terminal IN of the switch chip N1, the first switch between the terminal DA and the terminal S1A is closed, the second switch between the terminal DA and the terminal S2A is opened, the third switch between the terminal DB and the terminal S1B is closed, and the fourth switch between the terminal DB and the terminal S2B is opened, so that the first input terminal of the selection circuit 104 is turned on with the first output terminal of the selection circuit 104.

Based on the content of any one of the above embodiments, the second output terminal of the switch chip includes a fifth terminal and a sixth terminal.

Specifically, the terminal S2A and the terminal S2B are a fifth terminal and a sixth terminal, respectively. The terminal S2A and the terminal S2B may serve as a second output terminal of the switch chip N1.

When the input to the second input terminal of the selection circuit 104 from the 4 pin and the 5 pin of the RJ45 jack 101 is at the second level, the first terminal and the fifth terminal are connected to each other, and the second terminal and the sixth terminal are connected to each other.

Specifically, when the second level is input to the terminal IN of the switch chip N1 through the 4 pin and the 5 pin of the RJ45 jack 101, the first switch between the terminal DA and the terminal S1A is opened, the second switch between the terminal DA and the terminal S2A is closed, the third switch between the terminal DB and the terminal S1B is opened, and the fourth switch between the terminal DB and the terminal S2B is closed, so that the first input terminal of the selection circuit 104 is turned on with the second output terminal of the selection circuit 104.

It can be understood that when no external signal is inserted, the Detect pin is suspended, the B pole (base) of V1 is pulled high through R1, at this time, V1 is turned on, the inverter circuit 401 outputs a first level, and the terminal IN is pulled low, which may represent 0; when the Detect pin is at a low level, V1 is not turned on, the inverter circuit 401 outputs a second level, the terminal IN is pulled high,may represent 1. The switch chip N1 performs one of two operations on the incoming signal. By enabling the terminal

Pulled low and the channel is selected by control terminal IN. Control of the terminal IN pin may be achieved by the level of the Detect pin. When an ethernet signal is connected into the RJ45 socket 101 or no external signal is connected into the RJ45 socket 101, a Detect pin of the RJ45 socket 101 is suspended or IN a high impedance state, at this time, the Detect pin is pulled high by VCC, V1 is conducted, a terminal IN is pulled low, N1 is connected with terminals S1A and S1B, and the RJ45 socket 101 realizes the ethernet function; when a serial port signal is connected into the RJ45 socket 101, the Detect pin is GND, V1 is not conducted, the terminal IN is pulled high, N1 is connected to S2A and S2B, and the RJ45 socket 101 realizes a serial port function.

Based on the content of any one of the above embodiments, an electronic device includes the multiplexing circuit of the ethernet interface and the serial interface as in any one of the above embodiments.

Specifically, the multiplexing circuit of the ethernet interface and the serial interface according to any of the foregoing embodiments may be disposed on the electronic device, so that the RJ45 socket can be multiplexed into the ethernet interface and the serial interface, one RJ45 socket can be omitted, resources can be saved, a board area can be saved, and the cost is lower.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.

Claims

1. A multiplexing circuit for an ethernet interface and a serial interface, comprising: the system comprises an RJ45 socket, an Ethernet interface chip, a serial interface chip and a selection circuit;

pins 1 and 2 of the RJ45 socket are connected with the Ethernet interface chip; pins 3 and 6 of the RJ45 socket are connected with a first input end of the selection circuit; pins 4 and 5 of the RJ45 socket are connected with the second input end of the selection circuit; the first output end of the selection circuit is connected with the Ethernet interface chip; and the second output end of the selection circuit is connected with the serial interface chip.

2. The multiplexing circuit of an ethernet interface and a serial interface according to claim 1, wherein when the input of the 4 pins and 5 pins of the RJ45 jack to the second input of the selection circuit is at the first level, conduction is conducted between the first input of the selection circuit and the first output of the selection circuit.

3. The multiplexing circuit for an ethernet interface and a serial interface according to claim 1, wherein when the input of the 4 pins and the 5 pins of the RJ45 jack to the second input of the selection circuit is at the second level, conduction is performed between the first input of the selection circuit and the second output of the selection circuit.

4. The multiplexing circuit of an ethernet interface and a serial interface according to claim 1, wherein said selection circuit comprises an inverting circuit and a switch chip;

5. The multiplexing circuit of an ethernet interface and a serial interface of claim 4 wherein said inverting circuit comprises a triode or a field effect transistor.

6. The multiplexing circuit of an ethernet interface and a serial interface of claim 5 wherein the inverting circuit comprises a first transistor; the first triode is an NPN triode;

7. The multiplexing circuit of an ethernet interface and a serial interface according to any one of claims 4 to 6, wherein the first input terminal of the switch chip comprises a first terminal and a second terminal;

the first terminal is connected with a 3 pin of the RJ45 socket; the second terminal is connected with a 6 pin of the RJ45 jack.

8. The multiplexing circuit of an ethernet interface and a serial interface of claim 7 wherein the first output of the switch chip comprises a third terminal and a fourth terminal;

9. The multiplexing circuit of an ethernet interface and a serial interface of claim 7, wherein the second output of the switch chip comprises a fifth terminal and a sixth terminal;

10. An electronic device characterized by comprising a multiplexing circuit of the ethernet interface and the serial interface according to any one of claims 1 to 9.