CN218585323U

CN218585323U - High-efficiency acquisition gateway and system based on heterogeneous multi-core processor

Info

Publication number: CN218585323U
Application number: CN202222362629.3U
Authority: CN
Inventors: 苏晋殿; 周鹤; 严占想; 陈约适
Original assignee: Tan Kah Kee Innovation Laboratory
Current assignee: Tan Kah Kee Innovation Laboratory
Priority date: 2022-09-06
Filing date: 2022-09-06
Publication date: 2023-03-07
Anticipated expiration: 2032-09-06

Abstract

The utility model relates to a gateway technical field, in particular to gateway and system are gathered to high efficiency based on different structure multicore processor, the high efficiency gather the gateway including be used for with host computer communication connection's net gape for with application equipment end communication connection's bus port, different structure multicore processor and the data storage unit of being connected with different structure multicore processor electricity that is connected with net gape, bus port electricity respectively. The heterogeneous multi-core processor is loaded with a Li nux system and a freeRTOS system. The utility model provides a gateway system is gathered to high efficiency, through the application of heterogeneous multicore processor, the advantage of the two kinds of operating system of performance Li nux and freeRTOS can use complex functions such as Li nux system's database, network, can realize the high-efficient utilization of RS485 bus through the real-time of freeRTOS system again, has alleviateed the CPU rate of utilization of Li nux system simultaneously, effectively promotes communication efficiency.

Description

High-efficiency acquisition gateway and system based on heterogeneous multi-core processor

Technical Field

The utility model relates to a gateway technical field, in particular to gateway and system are gathered to high efficiency based on heterogeneous multicore processor.

Background

In the field of industrial test, a test system consists of a gateway and a plurality of terminals, wherein the gateway and the terminals are connected through a bus (such as RS 485). The gateway needs to read the data of the terminal through polling, and simultaneously performs data storage and is responsible for communication with the upper computer. The gateway needs to use a database and network functions, and a Linux system is generally adopted.

At present, the existing intelligent gateway has two types, wherein the first type adopts a Linux system to realize the functions of RS485 receiving and transmitting, database storage and upper computer communication. The RS485 bus of the test system adopting the gateway has low utilization rate and overhigh CPU utilization rate. The second type is that two chips are adopted, and one chip runs a Linux system to realize database storage and upper computer communication; the other one runs bare computer or FreeRTOS program to realize RS485 receiving and transmitting. The test system adopting the gateway needs to use two chips, occupies more board distribution space, cannot use on-chip communication between the chips, has higher CPU operation time ratio, and cannot ensure the operation reliability of the test system.

SUMMERY OF THE UTILITY MODEL

In order to solve the defects of overhigh idle rate of an RS485 bus and overhigh CPU utilization rate in the prior art, the utility model provides a high-efficiency acquisition gateway based on a heterogeneous multi-core processor, which comprises a network port used for being in communication connection with an upper computer; the bus port is used for being in communication connection with the application equipment end; the heterogeneous multi-core processor is respectively and electrically connected with the network port and the bus port; and the data storage unit is electrically connected with the heterogeneous multi-core processor.

The heterogeneous multi-core processor is provided with a Linux system and a freeRTOS system; the freeRTOS system is in communication connection with the bus port and is used for acquiring data information of the application equipment end; the Linux system is in communication connection with the freeRTOS system and is used for receiving data information of the freeRTOS system and storing the data information to the data storage unit; the Linux system is also in communication connection with the internet access and used for receiving a data query command of the upper computer and uploading data information in the data storage unit to the upper computer.

In one embodiment, the freeRTOS system comprises a polling thread unit and a receiving and sending thread unit with priority higher than that of the polling thread unit, wherein the polling thread unit is used for issuing a polling command to the application equipment terminal and acquiring data information of the application equipment terminal; the receiving and sending thread unit is used for receiving the command issued by the Linux system and sending the collected data information to the Linux system.

In one embodiment, the thread receiving and sending unit is provided with a sleep module, and the sleep module is used for controlling the thread receiving and sending unit to enter thread sleep after sending the acquired data information to the Linux system.

In one embodiment, the Linux system and the freeRTOS system are communicatively coupled via an RPMsg interface.

In one embodiment, the heterogeneous multi-core processor comprises heterogeneous multi-core chips, wherein the heterogeneous multi-core chips comprise a Cotex-A53 and a Cotex-M4, the Cotex-A53 carries a Linux system, and the Cotex-M4 carries a freeRTOS system.

In one embodiment, there are 4 Cotex-A53 and 1 Cotex-M4.

In one embodiment, the bus port is configured as a uart serial port.

In one embodiment, the data storage unit is configured as an eMMC memory.

The utility model also provides a gateway system is gathered to high efficiency adopts as above arbitrary embodiment the high-efficient gateway of gathering based on heterogeneous multicore processor still include host computer, at least one application device end and data transmission bus, host computer, application device end are respectively through data transmission bus and high-efficient gateway communication connection of gathering.

In one embodiment, the data transmission bus is configured as an RS485 bus.

Based on the above, compare with prior art, the utility model provides a pair of high-efficient collection gateway based on heterogeneous multicore processor, through heterogeneous multicore processor's application, the advantage of two kinds of operating system of performance Linux and freeRTOS can use complex function such as Linux system's database, network, can realize the high-efficient utilization of RS485 bus through freeRTOS system's real-time again, has alleviateed Linux system's CPU rate of utilization simultaneously, effectively promotes communication efficiency.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts; in the following description, the drawings are illustrated in a schematic view, and the drawings are not intended to limit the present invention.

Fig. 1 is a schematic structural diagram of an efficient acquisition gateway provided by the present invention;

fig. 2 is a timing diagram illustrating the testing of the RS485 interface level by the high-efficiency acquisition gateway in the data acquisition process according to the present invention;

fig. 3 is the utility model provides a gateway system's schematic structure diagram is gathered to high efficiency.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention; the technical features designed in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other; based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

In the description of the present invention, it should be noted that all terms (including technical terms and scientific terms) used in the present invention have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs, and cannot be construed as limiting the present invention; it will be further understood that terms, as used herein, should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In order to solve the idle rate that adopts single system RS485 bus among the prior art too high, and single system carries out frequent storage and reading and writing and causes the CPU rate of utilization too high, and then lead to the system card to break down even rushing to crash easily, dual system needs more cloth board spaces, can't use the on-chip communication between the chip, CPU operating duration is higher, the problem that the operational reliability of test system can't be guaranteed, the application provides a high-efficient collection gateway based on heterogeneous multicore processor.

Referring to fig. 1, fig. 1 is a schematic structural diagram of an efficient acquisition gateway based on a heterogeneous multi-core processor according to an embodiment of the present application, where the gateway includes: the network port is used for being in communication connection with an upper computer; the bus port is used for being in communication connection with the application equipment end; the heterogeneous multi-core processor is electrically connected with the network port and the bus port respectively; and the data storage unit is electrically connected with the heterogeneous multi-core processor. In the gateway, a network port is in communication connection with the heterogeneous multi-core processor, and the upper computer is in communication connection with the gateway through the network port and directly controls the heterogeneous multi-core processor to execute corresponding work.

In the embodiment, the heterogeneous multi-core processor is provided with a Linux system and a freeRTOS system, and the freeRTOS system is in communication connection with the bus port and is used for acquiring data information of an application equipment end; the Linux system is in communication connection with the freeRTOS system and used for receiving data information of the freeRTOS system and storing the data information to the data storage unit; the Linux system is also in communication connection with the internet access and used for receiving a data query command of the upper computer and uploading data information in the data storage unit to the upper computer.

Through the setting mode of the division of labor and cooperation of the two systems, the advantages of the two systems can be effectively utilized, the Linux system is responsible for communicating with the upper computer and executing the storage command of the data, and the freeRTOS system is responsible for sending the polling command to acquire the data of the application equipment, so that the burden of a single Linux system and a single chip in the traditional method is reduced, the utilization rate of a CPU is effectively reduced, and the communication efficiency is improved.

Specifically, the chip of the heterogeneous multi-core processor is preferably an i.mx8 chip. In some preferred embodiments, the chip is composed of 4 Cotex-A53 and 1 Cotex-M4 and respectively mounted on different cores, wherein the Cotex-A53 is mounted with a Linux system, and the Cotex-M4 is mounted with a freeRTOS system. It should be noted that, those skilled in the art may also select chip types and chip numbers of other heterogeneous multi-core processors capable of loading the Linux system and the freeRTOS system according to the functional requirements, which is not limited herein.

Furthermore, the Linux system has the functions of a database, a file system and a network, and the functional characteristics enable the Linux system to be used for receiving commands of the upper computer and executing related tasks, the Linux system can also generate the commands to be executed by the lower computer, and the database of the Linux system can well receive corresponding data information and safely store the data information. Therefore, in specific implementation, when the upper computer sends a data query command to the acquisition gateway, the Linux system receives the command through communication with the internet access, executes corresponding data information acquired from the data storage unit, and uploads the data information to the upper computer through a TCP (transmission control protocol). Meanwhile, the Linux system is also in communication connection with the freeRTOS system so as to receive the data information of the freeRTOS system and store the data information to the data storage unit.

Furthermore, the freeRTOS system has the characteristics of real-time performance, small occupied resource and support of preemptive scheduling, cooperative scheduling and time slice scheduling, and the characteristics enable the freeRTOS system to rapidly acquire data of a lower end application device end in real time and support multi-thread operation, and meanwhile, less CPU memory can be occupied in the running process. Therefore, in the embodiment, the freeRTOS system is in communication connection with the Linux system, and can receive commands of the Linux system and transmit data information to the Linux system. Meanwhile, the freeRTOS system sends a polling command to the application equipment end through communication of the bus port so as to acquire data information of the application equipment end.

Preferably, the Linux system and the freeRTOS system are in communication connection through an RPMsg interface shared inside the heterogeneous multi-core chip, and the RPMsg interface adopts an open-source component. The working principle is as follows: when the Linux system needs to receive data information collected by the freeRTOS system, the Linux system issues a data query command to the freeRTOS system through the RPmsg interface, the Linux system drives and generates a/dev/ttyRPMSG 30 node, and an application program can perform read-write operation according to the RPmsg interface method so as to communicate with the freeRTOS system. And the freeRTOS system executes corresponding operation, uploads the data information to the Linux system through the RPMsg interface, and the Linux system calls the database interface after receiving the data and stores the data to the data storage unit. By the communication connection mode shared in the chip, the running time of the on-chip communication occupying the CPU memory is greatly reduced, and the communication is more efficient and reliable.

Preferably, the freeRTOS system comprises a polling thread unit and a receiving and sending thread unit, after receiving a data query command of the Linux system, the freeRTOS system starts to execute work by the polling thread unit, starts to acquire data information of the application equipment end, caches the data information acquired by the polling thread unit in ram, and waits for a reading command of the Linux system; when the thread receiving and sending unit starts to work, the Linux system sends a data information reading command to the freeRTOS system through the RPmsg interface, and after the freeRTOS system receives the command, the data cached in the ram are sent out through the RPmsg interface. The thread receiving and sending unit is provided with a dormancy module, when the freeRTOS system sends out data cached in ram, the dormancy module starts to work, and the thread receiving and sending unit enters thread dormancy subsequently.

Furthermore, the priority of the transceiving thread unit is higher than that of the polling thread unit, and the polling thread unit does not have a sleep module, so that the polling thread can continuously collect the data information of the application equipment after the transceiving thread is executed. The utilization rate of the CPU is improved, and real-time monitoring can be carried out on the application equipment side. Through the setting mode, the problems that the bus utilization rate is low and the communication efficiency is reduced due to the fact that the bus cannot be polled within a certain idle time in the traditional Linux system can be solved. In addition, the RPMsg interface occupies a very short time of the freeRTOS system in the thread receiving and sending unit, and cannot influence the time sequence of the polling thread unit. Referring to fig. 2, fig. 2 is a timing chart of testing the level of the RS485 interface during data acquisition by the high-efficiency acquisition gateway provided in this embodiment, as can be seen from the timing chart, the working cycle of a polling thread unit is 4.46ms, the idle time of the RS485 bus is only 159.48 μ s, and the polling efficiency can reach over 95%, which is close to the theoretical value. Therefore, it is further shown that the utilization rate of the bus can be greatly improved by adopting the efficient acquisition gateway provided by the embodiment, and the communication efficiency of data is further improved.

Preferably, the gateway is in communication connection with the application device end through a bus port, and the bus port is preferably a uart serial port, is suitable for remote communication, and can be better adapted to an RS485 bus. Of course, the bus port may also be selected from other ports such as usb and spi according to actual working requirements, which is not limited herein.

Preferably, the data storage unit is an eMMC memory, which has a small size, low power consumption, and a large capacity, and is suitable for a storage medium of a consumer electronic device such as a mobile internet device such as a gateway. Of course, other non-physical form circuits with storage function, such as RAM or FIFO, or practical form storage devices or chips, such as Nandflash, norflash, UFS, SD card, usb disk, etc., may also be selected according to actual working requirements.

Referring to fig. 3, an embodiment of the present application further provides an efficient collection gateway system, which is applied to a gateway to poll and read data information of an application device, and the system includes: the system comprises an upper computer, an efficient acquisition gateway in any embodiment, at least one application device end and a data transmission bus. The upper computer and the application equipment end are respectively in communication connection with the high-efficiency acquisition gateway through a data transmission bus.

The upper computer controls the high-efficiency acquisition gateway to acquire data of the application equipment end through the data transmission bus. When the data is needed, the upper computer sends out a data query command to control the high-efficiency acquisition gateway to upload the data of the application equipment end to the upper computer. The high-efficiency acquisition gateway acquires the data of the application equipment end through the data transmission bus and stores the data of the application equipment end into a database of the gateway.

It should be noted that the application device side may be any device that can transmit or collect data through the gateway, and in this embodiment, is an industrial application device terminal, where at least one of the device terminals is provided.

The data transmission bus is preferably an RS485 bus, has multipoint two-way communication, can be connected with a plurality of application terminal devices, and has the advantages of strong anti-interference capability, large transmission distance, high transmission speed and the like.

In summary, compared with the prior art, the utility model provides a high-efficient collection gateway and system based on heterogeneous multicore processor, through heterogeneous multicore processor's application, exert the advantage of two kinds of operating systems of Linux and freeRTOS, can use complicated functions such as Linux system's database, network, can realize the high-efficient utilization of RS485 bus through freeRTOS system's real-time again, alleviateed Linux system's CPU rate of utilization simultaneously, reduced transmission bus idle rate, improved communication efficiency; in addition, the communication connection mode shared in the chip greatly reduces the time of the on-chip communication occupying the CPU memory and has high efficiency and reliability in the communication process.

In addition, it will be appreciated by those skilled in the art that although a number of problems exist in the prior art, each embodiment or aspect of the present invention may be improved only in one or a few aspects, without necessarily simultaneously solving all the technical problems listed in the prior art or in the background. It will be understood by those skilled in the art that nothing in a claim should be taken as a limitation on that claim.

Although terms such as heterogeneous multi-core processors, data storage units, bus ports, application side, polling thread units, transceiving thread units, and sleep modules are used more often herein, the possibility of using other terms is not excluded. These terms are used merely to more conveniently describe and explain the nature of the present invention; they are to be construed as being without limitation to any additional limitations of the present invention; the terms "first," "second," and the like in the description and in the claims, and in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.

Claims

1. The utility model provides a high-efficient gateway of gathering based on heterogeneous multicore processor which characterized in that: comprises that

The network port is used for being in communication connection with an upper computer;

the bus port is used for being in communication connection with the application equipment end;

the heterogeneous multi-core processor is electrically connected with the network port and the bus port respectively;

the data storage unit is electrically connected with the heterogeneous multi-core processor;

the heterogeneous multi-core processor is provided with a Linux system and a freeRTOS system; the freeRTOS system is in communication connection with the bus port and is used for collecting data information of the application equipment end; the Linux system is in communication connection with the freeRTOS system and is used for receiving data information of the freeRTOS system and storing the data information to the data storage unit; the Linux system is also in communication connection with the internet access and is used for receiving a data query command of the upper computer and uploading data information in the data storage unit to the upper computer.

2. The efficient collection gateway based on heterogeneous multi-core processors of claim 1, wherein: the freeRTOS system comprises a polling thread unit and a receiving and sending thread unit with the priority higher than that of the polling thread unit, wherein the polling thread unit is used for issuing a polling command to the application equipment end and acquiring data information of the application equipment end; the receiving and sending thread unit is used for receiving the command issued by the Linux system and sending the collected data information to the Linux system.

3. The efficient collection gateway based on heterogeneous multi-core processors of claim 2, wherein: the thread receiving and sending unit is provided with a dormancy module, and the dormancy module is used for controlling the thread receiving and sending unit to enter thread dormancy after sending the collected data information to the Linux system.

4. The efficient acquisition gateway based on heterogeneous multi-core processors of claim 1, wherein: the Linux system and the freeRTOS system are in communication connection through an RPMsg interface.

5. The efficient collection gateway based on heterogeneous multi-core processors of claim 1, wherein: the heterogeneous multi-core processor comprises a heterogeneous multi-core chip, the heterogeneous multi-core chip comprises a Cotex-A53 and a Cotex-M4, the Cotex-A53 carries the Linux system, and the Cotex-M4 carries the freeRTOS system.

6. The efficient collection gateway based on heterogeneous multi-core processors of claim 5, wherein: there are 4 Cotex-a53 and 1 Cotex-M4.

7. The efficient acquisition gateway based on heterogeneous multi-core processors of claim 1, wherein: the bus port is set as a uart serial port.

8. The efficient acquisition gateway based on heterogeneous multi-core processors of claim 1, wherein: the data storage unit is set as an eMMC memory.

9. An efficient acquisition gateway system, characterized in that: employing a heterogeneous multi-core processor based high efficiency acquisition gateway as claimed in any of claims 1-8; the system further comprises an upper computer, at least one application equipment end and a data transmission bus, wherein the upper computer and the application equipment end are in communication connection with the high-efficiency acquisition gateway through the data transmission bus respectively.

10. The efficient acquisition gateway system of claim 9, wherein: the data transmission bus is set to be an RS485 bus.