CN218570208U

CN218570208U - Peak detector and differential peak detector

Info

Publication number: CN218570208U
Application number: CN202221663198.8U
Authority: CN
Inventors: 张�浩; 姜亚伟
Original assignee: Nanjing Magnichip Microelectronics Co ltd
Current assignee: Nanjing Magnichip Microelectronics Co ltd
Priority date: 2022-06-29
Filing date: 2022-06-29
Publication date: 2023-03-03
Anticipated expiration: 2032-06-29

Abstract

The utility model discloses a peak detector, which comprises a signal input end, a signal output end, a first triode, a sampling capacitor and a bias current control circuit; the base electrode of the first triode is connected with the signal input end; the collector of the first triode is connected with power voltage, the emitter of the first triode is respectively connected with the bias current control circuit, the sampling capacitor and the signal output end, the terminal of the sampling capacitor, which is not connected with the emitter of the first triode, is grounded, and the bias current control circuit is connected with the first bias circuit; when the input signal is in the peak value time period to be detected, the bias current control circuit is communicated with the first bias circuit, the bias current is connected to an emitting electrode of the first triode, and the signal output end outputs a detection signal; when the input signal is in the non-to-be-measured peak value time period, the bias current control circuit simultaneously disconnects the first bias circuit and the first triode. The utility model discloses a peak detector has higher detection precision when high-speed inspection.

Description

Peak detector and differential peak detector

Technical Field

The utility model belongs to the technical field of the peak detector, concretely relates to peak detector.

Background

High performance peak detectors are widely used as sub-circuit units in various communication systems. The peak detector in the communication system can be used to assist in determining whether the communication channel is normal, and if the peak detector monitors that the signal amplitude is lower than a certain set amplitude, the signal is considered to be interrupted or the user is disconnected. The high-speed high-precision peak detector can greatly reduce the diagnosis time of the existence of signals of a communication system and improve the network efficiency.

Fig. 1 (a) is a schematic diagram of a circuit of a conventional detector, and the monitoring speed and the monitoring precision of the conventional detector are mutually restricted. When the signal rises or is in a peak time period, the detector Q1 quickly charges the output capacitor Cpk to a peak value; when the signal is in the off-peak period, the detected peak voltage is maintained from Cpk, but due to the discharging action of the bias current IB, the detected voltage on the capacitor Cpk continues to drop until the next peak arrives. The operating principle of the conventional detector results in unavoidable ripple on the detector output voltage Vout. In order to increase the operating speed, the bias current IB needs to be increased appropriately, and the increase in IB causes the output ripple to increase.

SUMMERY OF THE UTILITY MODEL

The technical problem to be solved is as follows: based on the technical problem, the utility model discloses a peak detector has higher detection precision when high-speed inspection.

The technical scheme is as follows:

a peak detector comprises a signal input end, a signal output end, a first triode (Q1), a sampling capacitor (Cpk) and a bias current control circuit (block 1);

the base electrode of the first triode (Q1) is connected with the signal input end and used for receiving an input signal (Vin); the collector of the first triode (Q1) is connected with power supply voltage, the emitter of the first triode (Q1) is respectively connected with the bias current control circuit (block 1), the sampling capacitor (Cpk) and the signal output end, the terminal of the sampling capacitor (Cpk) which is not connected with the emitter of the first triode (Q1) is grounded, and the bias current control circuit (block 1) is connected with the first bias circuit;

when the input signal (Vin) is in a peak value period to be detected, the bias current control circuit (block 1) is communicated with the first bias circuit, the bias current (IB) is connected to an emitter of the first triode (Q1), and the signal output end outputs a detection signal (Vout); when the input signal (Vin) is in a non-to-be-measured peak value period, the bias current control circuit (block 1) simultaneously disconnects the first bias circuit and the first triode (Q1).

Further, the bias current control circuit (block 1) comprises a second triode (Q2), a third triode (Q3), a fourth triode (Q4) and a second bias circuit;

the base electrode of the second triode (Q2) is connected with the signal input end, the emitting electrode of the second triode (Q2) is respectively connected with the base electrodes of the second biasing circuit and the third triode (Q3), and the collecting electrode of the second triode (Q2) is connected with the power supply voltage;

the collector electrode of the third triode (Q3) and the base electrode of the fourth triode (Q4) are both connected with the emitter electrode of the first triode (Q1), and the emitter electrode of the third triode (Q3) and the emitter electrode of the fourth triode (Q4) are both connected with the first biasing circuit; the collector of the fourth triode (Q4) is connected with the power supply voltage;

when the input signal (Vin) is in the peak value period to be measured, the third triode (Q3) and the fourth triode (Q4) are in the opening state, and the first triode (Q1) is used for charging the sampling capacitor (Cpk); when the input signal (Vin) is in the non-to-be-measured peak value time period, the first triode (Q1) and the third triode (Q3) are in a closed state, the fourth triode (Q4) is in an open state, and the voltage of the sampling capacitor (Cpk) is kept.

Further, the bias current control circuit (block 1) comprises a resistor, a filter capacitor, a third triode (Q3), a fourth triode (Q4) and a second bias circuit;

two ends of the filter capacitor are respectively connected with the signal input end and the base electrode of the third triode (Q3); one end of the resistor is connected with the base electrode of the third triode (Q3), and the other end of the resistor is connected with bias voltage;

Further, the triode used in the peak detector is one of an NPN type triode, a PNP type triode, a PMOS type triode, an NMOS type triode, and an insulated gate bipolar transistor.

A differential peak detector comprises two symmetrically arranged peak detectors;

the peak detector adopts the peak detector as described above, and the two peak detectors share the same sampling capacitor (Cpk).

Has the advantages that:

firstly, the utility model discloses a peak detector introduces bias current control circuit block1 on traditional detector basis, keeps detection circuitry Q1 bias current unchangeable thereby realizes high-speed detection in no signal and peak detection stage; the bias current is closed at the stage that the non-signal enters the valley bottom or the negative peak value, and no discharge current exists on the sampling capacitor Cpk, so that the detection signal is kept unchanged; the introduction of the bias current control circuit block1 greatly improves the detection precision of the high-speed detector.

Second, the utility model discloses a conflict problem between traditional wave detector high-speed detection and the high accuracy can be solved to the peak detector, adopts the utility model discloses a wave detector technique keeps the high accuracy when can realize high-speed detection.

Thirdly, the peak detector of the present invention has wide applications, for example, it can be used in PON system to monitor whether the burst user data packet is valid; it can also be used for detecting signal amplitude in a high-speed AGC (automatic gain control) loop, etc.

Drawings

FIG. 1 (a) is a schematic diagram of a conventional peak detector;

fig. 1 (b) is a schematic structural diagram of a peak detector of the present embodiment;

FIG. 2 is a schematic diagram of a bias current control circuit;

FIG. 3 is a diagram showing a comparison between simulation results of a conventional detector and the detector of the present embodiment;

fig. 4 (a) to 4 (d) are schematic diagrams of a part of detection examples of the peak detector of the present embodiment; fig. 4 (a) is a schematic diagram of a differential positive peak detector based on an NPN-type triode; FIG. 4 (b) is a schematic diagram of a differential positive peak detector based on an NMOS transistor; fig. 4 (c) is a schematic diagram of a single-ended positive peak detector based on an AC-coupled NPN-type triode; fig. 4 (d) is a schematic diagram of a single-ended positive peak detector based on an AC-coupled NMOS type triode.

Detailed Description

The following examples are presented to enable one of ordinary skill in the art to more fully understand the present invention, but are not intended to limit the invention in any manner.

Fig. 1 (b) is a schematic structural diagram of the peak detector of the present embodiment. Referring to fig. 1 (b), the peak detector includes a signal input terminal, a signal output terminal, a first transistor Q1, a sampling capacitor Cpk, and a bias current control circuit block1.

The base electrode of the first triode Q1 is connected with the signal input end and used for receiving an input signal Vin; the collector of the first triode Q1 is connected with power supply voltage, the emitter of the first triode Q1 is respectively connected with a bias current control circuit block1, a sampling capacitor Cpk and a signal output end, the terminal of the sampling capacitor Cpk which is not connected with the emitter of the first triode Q1 is grounded, and the bias current control circuit block1 is connected with the first bias circuit.

When the input signal Vin is in the peak time period to be detected, the bias current control circuit block1 is communicated with the first bias circuit, the bias current IB is connected to an emitter of the first triode Q1, and the signal output end outputs a detection signal Vout; when the input signal Vin is in a non-to-be-measured peak value period, the bias current control circuit block1 simultaneously disconnects the first bias circuit and the first triode Q1.

In this embodiment, the basic functions of the bias current control circuit block1 include: 1) When the signal Vin is in a peak value period to be measured, the bias current IB is connected to an emitting electrode of the first triode Q1, the working speed of the detector is improved, and the voltage on the sampling capacitor Cpk is the same as that of the input signal Vin; 2) When the signal Vin is in a non-to-be-measured peak value period, the bias current IB and the first triode Q1 are disconnected or bypassed, and the sampling capacitor does not have a discharge path and accurately maintains a sampling peak value. Therefore, the peak detector of the embodiment can realize high-speed detection and maintain high detection precision after introducing the bolck1 functional module.

Fig. 2 is a schematic diagram of a structure of one of the bias current control circuits. The base stage of the second triode Q2 is connected with the input signal Vin, the emitter stage is connected with the base electrode of the third triode Q3 and a second biasing circuit, and the second biasing circuit provides a biasing current IB2 for the second triode Q2; the collector of the third triode Q3 is connected with the signal output end, and the emitter is connected with the emitter of the third triode Q3; the base of the fourth triode Q4 is connected with the signal output end Vout, and the collector is connected with the power voltage VCC or other.

On the basis of the structure, the working principle of the peak detector is as follows: 1) When the input signal Vin is in the peak period to be detected, the third triode Q3 and the fourth triode Q4 are simultaneously turned on, half of the bias current IB flows through the first triode Q1, the first triode Q1 works in the high waiting state, meanwhile, the first triode Q1 charges the sampling capacitor Cpk, and the peak detector output signal Vout quickly follows the input signal Vin to rise. 2) When the input signal Vin is in the non-peak period, the first transistor Q1 and the third transistor Q3 are turned off, the fourth transistor Q4 is turned on to bypass the bias current IB, and the peak detector output voltage Vout is held by the sampling capacitor Cpk.

Fig. 3 is a simulated comparison graph of the detection characteristics of the conventional peak detector and the peak detector of the present embodiment under the same input conditions: in fig. 3, the black square wave is the input signal Vin, the light gray waveform is the conventional peak detector output, and the dark gray waveform is the peak detector output of this embodiment. As can be seen from fig. 3, the peak detector of the present embodiment has higher detection accuracy at the time of high-speed detection.

Fig. 2 is only one embodiment of the peak detector of the present embodiment, and fig. 4 (a) to 4 (b) further show other exemplary embodiments of the peak detector.

It should be understood that the embodiments of the peak detector of the present example include, but are not limited to, the positive peak detectors listed in fig. 2, 4 (a) through 4 (b). The peak detector embodiments of fig. 2, 4 (a) to 4 (b) may simply be replaced with corresponding negative peak detectors and difference detectors with PNP or PMOS devices due to device replaceability and complementarity; when PNP triode or PMOS device is used, the connection between ground terminal and power supply voltage terminal is changed, e.g. with the figure

4 (c), the collector of the first triode Q1 and the collector of the fourth triode Q4 are grounded, the terminal of the first biasing circuit far away from the third triode Q3 and the terminal of the sampling capacitor far away from the signal output end are connected with the power supply voltage. The peak detector of the present embodiment can be further optimized to be a corresponding positive peak detector, a negative peak detector, and a peak-peak detector (positive peak minus negative peak) constructed therefrom, and so on.

Claims

1. A peak detector is characterized by comprising a signal input end, a signal output end, a first triode (Q1), a sampling capacitor (Cpk) and a bias current control circuit (block 1);

2. Peak detector according to claim 1, characterized in that the bias current control circuit (block 1) comprises a second transistor (Q2), a third transistor (Q3), a fourth transistor (Q4), a second bias circuit;

the collector electrode of the third triode (Q3) and the base electrode of the fourth triode (Q4) are both connected with the emitter electrode of the first triode (Q1), and the emitter electrode of the third triode (Q3) and the emitter electrode of the fourth triode (Q4) are both connected with the first bias circuit; the collector of the fourth triode (Q4) is connected with the power supply voltage;

3. Peak detector according to claim 1, characterized in that the bias current control circuit (block 1) comprises a resistor, a filter capacitor, a third transistor (Q3), a fourth transistor (Q4), a second bias circuit;

when the input signal (Vin) is in the peak value period to be measured, the third triode (Q3) and the fourth triode (Q4) are in the opening state, and the sampling capacitor (Cpk) is charged by the first triode (Q1); when the input signal (Vin) is in the non-to-be-measured peak value time period, the first triode (Q1) and the third triode (Q3) are in a closed state, the fourth triode (Q4) is in an open state, and the voltage of the sampling capacitor (Cpk) is kept.

4. The peak detector according to any of claims 1 to 3, wherein the transistor used in the peak detector is one of an NPN transistor, a PNP transistor, a PMOS transistor, an NMOS transistor, and an insulated gate bipolar transistor.

5. A differential peak detector is characterized by comprising two peak detectors which are symmetrically arranged;

the peak detector employs a peak detector as claimed in any of claims 1-3, and both peak detectors share the same sampling capacitance (Cpk).