CN218449460U - Output circuit with prevent short-circuit protection circuit - Google Patents
Output circuit with prevent short-circuit protection circuit Download PDFInfo
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- CN218449460U CN218449460U CN202221894742.XU CN202221894742U CN218449460U CN 218449460 U CN218449460 U CN 218449460U CN 202221894742 U CN202221894742 U CN 202221894742U CN 218449460 U CN218449460 U CN 218449460U
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- 230000005669 field effect Effects 0.000 claims abstract description 77
- 230000002265 prevention Effects 0.000 claims abstract description 19
- 230000001052 transient effect Effects 0.000 claims description 5
- 239000003990 capacitor Substances 0.000 claims description 4
- 230000001629 suppression Effects 0.000 claims description 4
- 208000033999 Device damage Diseases 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000007664 blowing Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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Abstract
The utility model discloses an output circuit with prevent short-circuit protection circuit, include body circuit and prevent short-circuit protection circuit. A first field effect transistor and a first triode. The source electrode and the drain electrode of the first field effect transistor are respectively connected with the input end and the output end. The grid electrode of the first field effect tube is connected with the control end through the first triode, so that the control end can control the grid electrode voltage of the first field effect tube through the base electrode of the first triode to control the on-off between the source electrode and the drain electrode of the first field effect tube. The short-circuit prevention protection circuit comprises a second field effect transistor and a second triode. The source electrode and the drain electrode of the second field effect transistor are respectively connected with the power supply end and the base electrode of the second triode. The grid of the second field effect transistor is connected with the output end. The emitter and the collector of the second triode are respectively connected with the base and the grounding terminal of the first triode. When the output end is grounded and short-circuited, the base electrode of the first triode is controlled through the second field effect transistor and the second triode, and then the source electrode and the drain electrode of the first field effect transistor are controlled to be disconnected.
Description
Technical Field
The utility model relates to a power output circuit.
Background
Digital electronic devices are typically provided with various output interfaces. These output interfaces typically have a power output. The output interface is easy to have short circuit problems, especially the power output and grounding short circuit problems. When the power output and the grounding are short-circuited, if no protective measures are taken, the problem of electronic device damage caused by short circuit easily occurs to the digital electronic equipment.
Patent document CN 209001578U discloses an LVDS interface anti-insertion short-circuit prevention protection circuit, which is configured with a diode at the control terminal and the output terminal, so that when the output terminal is short-circuited with the ground terminal, the diode conducts the control terminal and the ground terminal, thereby pulling down the level of the control terminal and cutting off the enable output of the control terminal, thereby avoiding the short circuit between the power supply and the ground. However, this circuit has two drawbacks: a first drawback is that, when the output terminal is short-circuited with the ground terminal, the control terminal and the ground terminal are turned on by the diode, thereby causing a short-circuit of the control terminal and the ground terminal; a second drawback is that the diodes risk to burn-through in the reverse direction.
In the prior art, a comparator is used to compare the voltage at the output terminal with the voltage at the ground terminal to detect whether the power output and the ground are short-circuited, and when the short-circuit occurs, the output is cut off by the output of the comparator.
Disclosure of Invention
The utility model discloses the problem that will solve: the problem of electronic device damage caused by power output grounding short circuit is prevented.
In order to solve the above problem, the utility model discloses a scheme as follows:
the output circuit with the short-circuit prevention protection circuit comprises a body circuit and the short-circuit prevention protection circuit; the body circuit comprises a first field effect transistor and a first triode; the source electrode and the drain electrode of the first field effect transistor are respectively connected with the input end and the output end; the grid electrode of the first field effect tube is connected with the control end through the first triode, so that the control end can control the current between the emitter and the collector of the first triode through the base electrode of the first triode so as to control the grid voltage of the first field effect tube, and the on-off between the source electrode and the drain electrode of the first field effect tube is controlled; the short-circuit prevention protection circuit comprises a second field effect transistor and a second triode; the source electrode and the drain electrode of the second field effect transistor are respectively connected with a power supply end and the base electrode of the second triode; the grid electrode of the second field effect transistor is connected with the output end; and the collector and the emitter of the second triode are respectively connected with the base and the grounding end of the first triode.
Further, the grid electrode of the first field effect transistor is connected with the input end; the collector electrode of the first triode is connected with the grid electrode of the first field effect transistor, and the emitter electrode of the first triode is connected with the grounding terminal.
Further, a resistor R11 is connected between the grid electrode and the input end of the first field effect transistor.
Further, a resistor R12 is connected between the base electrode of the first triode and the control end, and a resistor R13 is connected between the base electrode of the first triode and the ground end.
Further, a resistor R22 is connected between the base electrode of the second triode and the grounding end.
Further, a resistor R23 is connected between the source electrode and the power supply end of the second field effect transistor, a resistor R24 is connected between the source electrode and the grid electrode, and a resistor R25 is connected between the grid electrode and the output end.
Further, a capacitor is connected between the output end and the ground end.
Further, a transient voltage suppression diode is connected between the output end and the ground end.
Further, a resistor R21 is connected between the emitter of the second triode and the base of the first triode.
Furthermore, a cross-over resistor R29 is connected between the drain electrode and the output end of the first field effect transistor.
The technical effects of the utility model are as follows: the technical scheme of the utility model under, when output ground connection short circuit, through the base of the first triode of second field effect transistor and second triode control, and then the disconnection of the first field effect transistor source electrode of control and drain electrode prevents output voltage. Furthermore, the utility model discloses an output has still set up condenser, transient voltage suppression diode, cross-over resistance, can avoid destroying interior device when output static high pressure or surge invade at to a great extent.
Drawings
Fig. 1 is an overall circuit diagram of an embodiment of the present invention.
Fig. 2 is a circuit diagram of a body circuit portion of an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
As shown in fig. 1, an output circuit with a short-circuit prevention protection circuit includes a body circuit and a short-circuit prevention protection circuit 2.
The bulk circuit, referring to fig. 2, includes an input terminal VCC _12V, an OUTPUT terminal OUTPUT, a control terminal CTRL, and a first field effect transistor QA and a first triode Q1 connected between the input terminal VCC _12V, the OUTPUT terminal OUTPUT, and the control terminal CTRL. The source S and the drain D of the first field effect transistor QA are respectively connected with the input end VCC _12V and the OUTPUT end OUTPUT. The grid G of the first field-effect tube QA is connected with the control end CTRL through the first triode Q1, so that the control end CTRL can control the current between the emitter and the collector of the first triode Q1 through the base of the first triode Q1 to further control the grid G voltage of the first field-effect tube QA, and therefore the on-off between the source S and the drain D of the first field-effect tube QA is controlled. Specifically, the grid G of the first field effect transistor QA is connected with the input end VCC _12V and is connected with the collector of the first triode Q1; the emitter of the first triode Q1 is connected with the ground terminal GND, and the base is connected with the control terminal CTRL.
In this embodiment, the input terminal VCC _12V is a power input for inputting 12V voltage. The control terminal CTRL is usually connected to the microprocessor, and inputs 5V high or 0V low. The ground GND is also a ground line. When the control terminal CTRL inputs a 5V high level, the collector and the emitter of the first triode Q1 are turned on, the gate G of the first field-effect tube QA to which the collector of the first triode Q1 is connected exhibits a low level, a voltage difference between the source S and the gate G of the first field-effect tube QA is higher than a 2V turn-on voltage of the first field-effect tube QA, the source S and the drain D of the first field-effect tube QA are turned on, and at this time, the OUTPUT terminal OUTPUT OUTPUTs a 12V voltage. When the control terminal CTRL inputs a high level of 0V, the collector and the emitter of the first triode Q1 are cut off, the gate G of the first field-effect tube QA connected to the collector of the first triode Q1 exhibits a high level of 12V, the voltage difference between the source S and the gate G of the first field-effect tube QA is 0, which is smaller than the 2V turn-on voltage of the first field-effect tube QA, at this time, the source S and the drain D of the first field-effect tube QA are cut off, and the OUTPUT terminal OUTPUT does not OUTPUT.
Further, the body circuit is further connected with a plurality of resistors for current limiting and voltage dividing, including a resistor R11 connected between the gate G of the first field effect transistor QA and the input terminal VCC _12V, a resistor R12 connected between the base of the first triode Q1 and the control terminal CTRL, and a resistor R13 connected between the base of the first triode Q1 and the ground terminal GND. Wherein the resistance value of the resistor R11 is preferably 100K ohm; the resistance value of the resistor R12 is preferably 47K ohms; the resistance of the resistor R13 is preferably 100K ohms. When the control terminal CTRL inputs a 5V high level, the base voltage of the first triode Q1 is 5v × 100k/(100k + 47k) =3.4V.
The short-circuit prevention protection circuit 2 includes a second field effect transistor QB and a second transistor Q2. And a source S and a drain D of the second field effect transistor QB are respectively connected with a power supply terminal VCC _5V and a base of the second triode Q2. The grid G of the second field effect transistor QB is connected with the OUTPUT end OUTPUT, and the emitting electrode and the collector electrode of the second triode Q2 are respectively connected with the base electrode of the first triode Q1 and the grounding end GND. When the OUTPUT end OUTPUT is not in short circuit with the ground, the voltage between the source S and the grid G of the second field-effect tube QB is smaller than the 2V starting voltage of the second field-effect tube QB, the source S and the drain D of the second field-effect tube QB are not conducted, at the moment, the base of the second triode Q2 is in a low level, the emitter and the collector of the second triode Q2 are not conducted, and the base voltage of the first triode Q1 is completely controlled by the control end CTRL. When the OUTPUT end OUTPUT is short-circuited with the ground, the voltage between the source S and the grid G of the second field-effect tube QB is greater than the 2V starting voltage of the second field-effect tube QB, the source S and the drain D of the second field-effect tube QB are conducted, so that the base of the second triode Q2 is at a high level, the emitter and the collector of the second triode Q2 are conducted, so that the base of the first triode Q1 is at a low level, the collector and the emitter of the first triode Q1 are cut off, the grid G of the first field-effect tube QA connected with the collector of the first triode Q1 is at a high level of 12V, the voltage difference between the source S and the grid G of the first field-effect tube QA is 0 and less than the 2V starting voltage of the first field-effect tube QA, at the moment, the source S and the drain D of the first field-effect tube QA are cut off, and the OUTPUT end OUTPUT is not OUTPUT. That is, in the above circuit, if the OUTPUT terminal OUTPUT is short-circuited to the ground, the OUTPUT of the OUTPUT terminal OUTPUT is cut off.
In this embodiment, the power supply terminal VCC _5V is a power supply input to which a voltage of 5V is input.
Further, the short-circuit prevention protection circuit 2 is further connected with a plurality of resistors for current limiting and voltage dividing, including: a resistor R21 between the emitter of the second triode Q2 and the base of the first triode Q1, a resistor R22 between the base of the second triode Q2 and the ground terminal GND, a resistor R23 between the source S of the second field-effect tube QB and the power supply terminal VCC _5V, a resistor R24 between the source S and the gate G of the second field-effect tube QB, and a resistor R25 between the gate G and the OUTPUT terminal OUTPUT of the second field-effect tube QB. Wherein, the resistance value of the resistor R21 is preferably 1K ohm; the resistance value of the resistor R22 is preferably 100K ohms; the resistance value of the resistor R23 is preferably 10K ohms; the resistance of the resistor R24 is preferably 100K ohms; the resistance of the resistor R25 is preferably 10K ohms. When OUTPUT terminal OUTPUT is not short-circuited with ground, OUTPUT terminal OUTPUT OUTPUTs 12V, source S voltage =5V + (12V-5V) × 10K/(10k +100k + 10k) =5.6V of second field-effect tube QB, gate G voltage =5V + (12V-5V) (10k + 100k)/(10k +100k + 10k) =11.4V of second field-effect tube QB, voltage =5.6V-11.4V = -5.8V between source S and gate G of second field-effect tube QB, and source S and drain D of second field-effect tube QB are not conducted. When the OUTPUT end OUTPUT is not short-circuited with the ground and the OUTPUT end OUTPUT has no OUTPUT voltage, the voltage of the source electrode S and the voltage of the grid electrode G of the second field-effect tube QB are both 5V, the voltage between the source electrode S and the grid electrode G of the second field-effect tube QB is 0V, and the source electrode S and the drain electrode D of the second field-effect tube QB are not conducted. When OUTPUT terminal OUTPUT and ground are short-circuited, source S voltage =5V = (10k + 100k)/(10k +100k + 10k) =4.6V of second field-effect tube QB, gate G voltage =5v + 10k/(10k +100k + 10k) =0.4V of second field-effect tube QB, voltage = 4.6V-0.v =4.2v between source S and gate G of second field-effect tube QB, which is higher than 2V turn-on voltage, source S and drain D of second field-effect tube QB are turned on, at this time, base voltage =5v 100k/(0k 100k) =4.5V of second triode Q2 is larger than turn-on voltage of second triode Q2, emitter electrode of second triode Q2 is turned on, and base voltage =5v + 10k/(10k) and +100k + 4.5V of first triode Q1 is smaller than turn-on voltage of second triode Q2, and at this time, base voltage =5v = 10k = 1k/(10k). The turn-on voltages of the first triode Q1 and the second triode Q2 are both 1.2V.
Further, in the present embodiment, the short-circuit prevention protection circuit 2 further includes a capacitor C1, a transient voltage suppression diode D1, and a bridge resistor R29. The capacitor C1 is used for filtering and is connected between the OUTPUT terminal OUTPUT and the ground terminal GND. The transient voltage suppressing diode D1, that is, the TVS tube, for preventing the electrostatic or surge intrusion of the OUTPUT terminal OUTPUT, is connected between the OUTPUT terminal OUTPUT and the ground terminal GND. A bridge resistor R29, i.e., a 0 ohm resistor familiar to those skilled in the art, is connected between the drain D of the first fet QA and the OUTPUT terminal OUTPUT for bridge connection and high current blowing. In this embodiment, the current 2A is limited by the bridge resistor R29, and when the current exceeds 2A by the bridge resistor R29, the bridge resistor R29 blows.
Claims (10)
1. An output circuit with a short-circuit prevention protection circuit is characterized by comprising a body circuit and the short-circuit prevention protection circuit; the body circuit comprises a first field effect transistor and a first triode; the source electrode and the drain electrode of the first field effect transistor are respectively connected with the input end and the output end; the grid electrode of the first field effect tube is connected with the control end through the first triode, so that the control end can control the current between the emitter and the collector of the first triode through the base electrode of the first triode so as to control the grid electrode voltage of the first field effect tube, and therefore the on-off between the source electrode and the drain electrode of the first field effect tube is controlled; the short-circuit prevention protection circuit comprises a second field effect transistor and a second triode; the source electrode and the drain electrode of the second field effect transistor are respectively connected with a power supply end and the base electrode of the second triode; the grid electrode of the second field effect transistor is connected with the output end; and the collector and the emitter of the second triode are respectively connected with the base and the grounding end of the first triode.
2. The output circuit with the short-circuit prevention protection circuit as claimed in claim 1, wherein a gate of the first field effect transistor is connected to the input terminal; the collector of the first triode is connected with the grid of the first field effect transistor, and the emitter of the first triode is connected with the grounding terminal.
3. An output circuit with a short-circuit prevention protection circuit as claimed in claim 2, characterized in that a resistor R11 is connected between the gate and the input terminal of the first fet.
4. An output circuit with a short-circuit protection circuit as claimed in claim 2, wherein a resistor R12 is connected between the base and the control terminal of the first triode, and a resistor R13 is connected between the base and the ground terminal.
5. The output circuit with the short-circuit prevention protection circuit as claimed in claim 1, wherein a resistor R22 is connected between the base of the second transistor and a ground terminal.
6. An output circuit with a short-circuit prevention protection circuit as claimed in claim 1, characterized in that a resistor R23 is connected between the source and the power supply terminal of the second fet, a resistor R24 is connected between the source and the gate, and a resistor R25 is connected between the gate and the output terminal.
7. An output circuit with an anti-short circuit protection circuit as claimed in claim 1, characterized in that a capacitor is connected between said output terminal and ground terminal.
8. An output circuit with an anti-short circuit protection circuit as claimed in claim 1, characterized in that a transient voltage suppression diode is connected between said output terminal and ground terminal.
9. An output circuit with a short-circuit prevention protection circuit as claimed in claim 1, wherein a resistor R21 is connected between the emitter of the second transistor and the base of the first transistor.
10. An output circuit with a short-circuit prevention protection circuit as claimed in claim 1, characterized in that a cross-over resistor R29 is connected between the drain of the first fet and the output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221894742.XU CN218449460U (en) | 2022-07-21 | 2022-07-21 | Output circuit with prevent short-circuit protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221894742.XU CN218449460U (en) | 2022-07-21 | 2022-07-21 | Output circuit with prevent short-circuit protection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218449460U true CN218449460U (en) | 2023-02-03 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221894742.XU Active CN218449460U (en) | 2022-07-21 | 2022-07-21 | Output circuit with prevent short-circuit protection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN218449460U (en) |
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2022
- 2022-07-21 CN CN202221894742.XU patent/CN218449460U/en active Active
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