CN218333089U - Shift register, grid drive circuit and display panel - Google Patents

Abstract

The utility model discloses a shift register, grid drive circuit and display panel, include first the control unit through setting up second output control module, first the control unit includes first the control subunit and second the control subunit, even consequently transistor threshold voltage in the first the control subunit is just partially to lead to its self to leak current great, because the existence of second the control subunit, second the control subunit plays certain truncation effect to between second node and the first the control subunit, the electric potential that reduces the second node passes through first the control subunit electric leakage, make the electric potential of second node can remain stable, and then guarantee shift register output signal's stability, be favorable to improving display quality.

Description

Shift register, grid drive circuit and display panel

Technical Field

The embodiment of the utility model provides a relate to and show technical field, especially relate to a shift register, gate drive circuit and display panel.

Background

With the development of display technology, people have higher and higher requirements on display quality.

In the conventional display panel, a gate driving circuit is usually included, but the signal output of the gate driving circuit in the conventional display panel is unstable, which results in poor display quality.

SUMMERY OF THE UTILITY MODEL

The utility model provides a shift register, gate drive circuit and display panel to improve shift register output signal's stability, improve display quality.

In a first aspect, an embodiment of the present invention provides a shift register, including: the device comprises a first output module, a second output module, a first output control module and a second output control module;

the first output control module is used for controlling the transmission of the initial signal to the first node according to the first clock signal and controlling the transmission of the first potential signal to the first node according to the second clock signal and the potential of the set node; the first output module is used for being switched on or switched off at least according to the potential of the first node and transmitting a second clock signal to the output end of the shift register when the first output module is switched on;

the second output control module comprises a first control unit and a second control unit, the first control unit comprises a first control subunit and a second control subunit, and the first control subunit is used for controlling the transmission of the first clock signal to the middle node according to the potential of the first node; the second control subunit is used for controlling the connection state of the intermediate node and the second node according to a second clock signal; the second control unit is used for controlling the transmission of the second potential signal to the second node according to the first clock signal;

the second output module is used for switching on or off according to the potential of the second node and transmitting the first potential signal to the output end of the shift register when the second output module is switched on;

and setting the node as a second node or an intermediate node.

Optionally, a control end of the first control subunit is electrically connected to the first node, a first end of the first control subunit is electrically connected to the first clock signal end, a second end of the first control subunit is electrically connected to a first end of the second control subunit, a second end of the second control subunit is electrically connected to the second node, and a control end of the second control subunit is electrically connected to the second clock signal end; the first clock signal end is used for inputting a first clock signal, and the second clock signal end is used for inputting a second clock signal;

the second end of the first control subunit serves as an intermediate node.

Optionally, the first control subunit includes a first transistor, a gate of the first transistor is used as a control end of the first control subunit, a first pole of the first transistor is used as a first end of the first control subunit, and a second pole of the first transistor is used as a second end of the first control subunit;

the second control subunit comprises a second transistor, a gate of the second transistor is used as a control terminal of the second control subunit, a first pole of the second transistor is used as a first terminal of the second control subunit, and a second pole of the second transistor is used as a second terminal of the second control subunit.

Optionally, the first output control module includes a third control unit and a fourth control unit, a control end of the third control unit is connected to the first clock signal, a first end of the third control unit is connected to the start signal, and a second end of the third control unit is electrically connected to the first node;

a first control end of the fourth control unit is electrically connected with the set node, a second control end of the fourth control unit is connected with the second clock signal, a first end of the fourth control unit is connected with the first potential signal, and a second end of the fourth control unit is electrically connected with the first node.

Optionally, the third control unit includes a third transistor, a gate of the third transistor is connected to the first clock signal, a first pole of the third transistor is connected to the start signal, and a second pole of the third transistor is electrically connected to the first node;

the fourth control unit comprises a fourth transistor and a fifth transistor, wherein the grid electrode of the fourth transistor is used as a first control end, the first pole of the fourth transistor is used as a first end of the fourth control unit, the second pole of the fourth transistor is electrically connected with the first pole of the fifth transistor, the second pole of the fifth transistor is used as a second end of the fourth control unit, and the grid electrode of the fifth transistor is used as a second control end;

alternatively, a gate of the fourth transistor serves as the second control terminal, a first pole of the fourth transistor serves as the first terminal of the fourth control unit, a second pole of the fourth transistor is electrically connected to a first pole of the fifth transistor, a second pole of the fifth transistor serves as the second terminal of the fourth control unit, and a gate of the fifth transistor serves as the first control terminal.

Optionally, the second control unit includes a sixth transistor, a gate of the sixth transistor is connected to the first clock signal, a first pole of the sixth transistor is connected to the second potential signal, and a second pole of the sixth transistor is electrically connected to the second node.

Optionally, the first output module includes a seventh transistor and a first capacitor, a gate of the seventh transistor is electrically connected to the first node, a first pole of the seventh transistor is connected to the second clock signal, and a second pole of the seventh transistor is electrically connected to the output terminal of the shift register; the first end of the first capacitor is electrically connected with the grid electrode of the seventh transistor, and the second end of the first capacitor is electrically connected with the second pole of the seventh transistor; the second output module comprises an eighth transistor and a second capacitor, the grid electrode of the eighth transistor is electrically connected with the second node, the first pole of the eighth transistor is connected with the first potential signal, and the second pole of the eighth transistor is electrically connected with the output end of the shift register; a first terminal of the second capacitor is electrically connected to the gate of the eighth transistor, and a second terminal of the second capacitor is electrically connected to the first pole of the eighth transistor.

Optionally, the shift register further includes a ninth transistor, a gate of the ninth transistor is connected to the second potential signal, a first pole of the ninth transistor is electrically connected to the first node, and a second pole of the ninth transistor is electrically connected to the first output module;

the first output module is used for switching on or switching off according to the electric potential of the first node and the second electric potential signal.

In a second aspect, the present invention further provides a gate driving circuit, which includes a plurality of shift registers of the first aspect, and each shift register is connected in cascade.

In a third aspect, the embodiment of the present invention further provides a display panel, including the gate driving circuit provided in the second aspect.

The utility model provides a shift register, gate drive circuit and display panel, include first the control unit through setting up second output control module, first the control unit includes first control subunit and second control subunit, even consequently transistor threshold voltage among the first control subunit is just partially to lead to its self to leak current great, because the existence of second control subunit, second control subunit plays certain truncation effect between second node and the first control subunit, the electric potential that can reduce the second node passes through first control subunit electric leakage, make the electric potential of second node can remain stable. In the control signals and the potential signals of the nodes, when the low potential signal is an effective potential signal, the first potential signal is a high potential signal, and the second potential signal is a low potential signal, in a working stage where the potential of the second node is low potential (the second output module is turned on, and the shift register outputs the high potential signal), the low potential of the second node can be well maintained due to the existence of the second control subunit. The first output control module is used for controlling transmission of the first potential signal to the first node according to the second clock signal and the potential of the set node, and the set node is a second node or an intermediate node, because when the second control subunit is switched on, the potential of the intermediate node is equal to that of the second node, and the low potential of the second node is well maintained, the low potential of the intermediate node can also be well maintained, so that the first output control module can be completely switched on according to the effective potential signal of the second clock signal and the low potential signal well maintained by the set node, and the high potential signal of the first potential signal end is completely transmitted to the first node by the first output control module, so that the first output module is completely switched off according to the high potential signal, and further, when the shift register outputs the high potential signal, the second clock signal accessed by the first output module does not influence output of the shift register, the stability of the output signal of the shift register is ensured, and the display quality is favorably improved.

Drawings

FIG. 1 is a schematic diagram of a shift register in a gate driving circuit commonly used in the prior art;

FIG. 2 is a diagram illustrating a shift register output signal according to the prior art;

fig. 3 is a schematic structural diagram of a shift register according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of another shift register provided in an embodiment of the present invention;

fig. 5 is a schematic structural diagram of another shift register according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of another shift register according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of another shift register according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of another shift register according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of another shift register according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of another shift register provided in an embodiment of the present invention;

fig. 11 is a timing diagram of driving a shift register according to an embodiment of the present invention;

fig. 12 is a schematic structural diagram of another shift register according to an embodiment of the present invention;

fig. 13 is a schematic diagram of an output signal of a shift register according to an embodiment of the present invention;

fig. 14 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention;

fig. 15 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 16 is a schematic structural diagram of another display panel according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

As described in the background art, the signal output of the gate driving circuit in the conventional display panel is unstable, resulting in poor display quality. As a result of research, the inventors found that the above problems occur because the conventional gate driving circuit generally includes a plurality of cascaded shift registers, and each shift register generally includes two output transistors, hereinafter referred to as a first output transistor and a second output transistor, wherein the first output transistor is used for outputting a high-level driving signal, and the second output transistor is used for outputting a low-level driving signal, and the driving signal may be a scanning signal or a light emission control signal. The driving signal is output to a pixel circuit of the display panel, wherein a gate potential of the first output transistor and a gate potential of the second output transistor are controlled by other transistors, respectively. Fig. 1 is a schematic structural diagram of a shift register in a gate driving circuit commonly used in the prior art, wherein fig. 1 only shows a partial structure of the shift register, and when a first output transistor T01 is turned on, a high level signal of a first potential signal terminal VGH can be transmitted to an output terminal; when the second output transistor T02 is turned on and the second clock signal terminal SCK2 inputs a low level signal, the low level signal of the second clock signal terminal SCK2 is output through the second output transistor T02. The gate potential of the first output transistor T01, i.e., the potential of the second node N2, is controlled by the control transistor T03, and the on state of the control transistor T03 is determined by the potential of the first node N1. In the conventional shift register, a low level signal is output only in a short time within one frame, and the shift register outputs a high level signal in other times. With reference to fig. 1, in most of the time period when the high level signal is output by the shift, the second node N2 is at a low level, the first node N1 is at a high level, that is, the gate potential of the control transistor T03 is at a high level, when the first clock signal input by the first clock signal terminal SCK1 is at a low level, the gate-source voltage difference of the control transistor T03 is greater than 0, that is, the control transistor T03 is stressed by the positive bias voltage. As described above, the time during which the shift register outputs the high level within one frame is long, so that the time during which the control transistor T03 is subjected to the positive bias stress is long. The control transistor T03 is subjected to a positive bias stress for a long time, so that the leakage current is increased, the second node N2 is directly connected to the drain of the control transistor T03, so that the potential of the second node N2 is increased due to the leakage current of the control transistor T03, the first node potential control module 01 includes a transistor controlled by the second node N2, the potential of the second node N2 is increased, so that the transistor controlled by the second node N2 in the first node potential control module 01 cannot be completely turned on, and therefore, a high potential signal of the first potential signal terminal sch cannot be completely transmitted to the first node N1, so that the potential of the first node N1 is low, and the second output transistor T02 cannot be completely turned off in a stage of the second node N2, so that when the first output transistor T01 is turned on to output a high level, a signal input by the second clock signal terminal SCK2 affects the output of a high level signal, fig. 2 is a schematic diagram of a shift register output signal shift in the prior art, and a high level signal output by a register output from a vgk 2 can be seen, so that the output of a shift gate of a display panel is affected by poor working quality of a display panel.

Based on the above reason, the embodiment of the utility model provides a shift register is provided. Before introducing the specific implementation of the embodiments of the present invention, the signals used by the shift register of the embodiments of the present invention are briefly introduced.

In one frame, the first clock signal is a signal comprising a plurality of high potential pulses and a plurality of low potential pulses, and the high potential pulses and the low potential pulses are alternately changed; in one frame, the second clock signal is also a signal comprising a plurality of high potential pulses and a plurality of low potential pulses, and the high potential pulses and the low potential pulses are alternately changed; the high potential pulse of the first clock signal is overlapped with the low potential pulse of the second clock signal, and the low potential pulse of the first clock signal is overlapped with the high potential pulse of the second clock signal. Optionally, the high potential pulse width of the first clock signal is equal to the high potential pulse width of the second clock signal; the low potential pulse width of the first clock signal is equal to the low potential pulse width of the second clock signal.

In one frame, the start signal is a signal including a high potential pulse and a low potential pulse, in which the high potential pulse and the low potential pulse alternate.

The first clock signal, the second clock signal, and the start signal are collectively referred to as a control signal. For any control signal, the effective potential signal in the control signal is determined by the device type of the module in the shift register controlled by the control signal, and specifically, the effective potential signal of the control signal is a signal capable of controlling the conduction of the device. For example, when the control signal is used to control the P-type transistor, the active potential signal is a low potential signal, and when the control signal is used to control the N-type transistor, the active potential signal is a high potential signal.

The first potential signal and the second potential signal can be both fixed and unchangeable signals, the potentials of the first potential signal and the second potential signal are opposite, optionally, the first potential signal is a high potential signal, and the second potential signal is a low potential signal; the first potential signal may be a low potential signal, and the second potential signal may be a high potential signal.

Optionally, for each of the control signal, the first potential signal, and the second potential signal, the voltage of the high potential signal may be equal, for example, may be +7V, and the voltage of the low potential signal may also be equal, for example, may be-7V.

Fig. 3 is a schematic structural diagram of a shift register according to an embodiment of the present invention, and referring to fig. 3, the shift register includes: a first output control module 110, a second output control module 120, a first output module 130, and a second output module 140;

the first output control module 110 is configured to control transmission of the start signal to the first node N1 according to the first clock signal, and to control transmission of the first potential signal to the first node N1 according to the second clock signal and the potential of the setting node; the first output module 130 is configured to be turned on or off according to a potential of at least the first node N1, and transmit a second clock signal to the output terminal OUT of the shift register when the first output module is turned on;

the second output control module 120 includes a first control unit 121 and a second control unit 122, the first control unit 121 includes a first control subunit 1211 and a second control subunit 1212, the first control subunit 1211 is used to control transmission of the first clock signal to the intermediate node N0 according to the potential of the first node N1; the second control subunit 1212 is configured to control a connection state of the intermediate node N0 and the second node N2 according to the second clock signal; the second control unit 122 is configured to control transmission of the second potential signal to the second node N2 according to the first clock signal;

the second output module 140 is configured to turn on or off according to a potential of the second node N2, and transmit a first potential signal to the output terminal OUT of the shift register when the second output module is turned on;

wherein, the set node is the second node N2 or the intermediate node N0.

Referring to fig. 3, the shift register includes a first clock signal terminal SCK1, a second clock signal terminal SCK2, a first potential signal terminal VGH, and a second potential signal terminal VGL, wherein the first clock signal terminal SCK1 is used for inputting a first clock signal, the second clock signal terminal SCK2 is used for inputting a second clock signal, the first potential signal terminal VGH is used for inputting a first potential signal, and the second potential signal terminal VGL is used for inputting a second potential signal. Optionally, the first potential signal is a high potential signal, and the second potential signal is a low potential signal. The shift register further includes an initial signal terminal SIN electrically connected to the first output control module 110, and the initial signal terminal SIN is used for inputting an initial signal.

The first output control module 110 is configured to control transmission of the start signal to the first node N1 according to a first clock signal, where the first output control module 110 transmits the start signal to the first node N1 when the first clock signal is an active potential signal; when the first clock signal is the inactive signal, the first output control module 110 controls the start signal not to be transmitted to the first node N1. The first output control module 110 is configured to control transmission of the first potential signal to the first node N1 according to the second clock signal and the potential of the set node, where when the second clock signal is an effective potential signal and the potential of the set node is an effective potential signal, the first output control module 110 transmits the first potential signal to the first node N1; when any one of the second clock signal and the potential of the set node is an invalid potential signal, the first output control module 110 does not transmit the first potential signal to the first node N1. Wherein, the set node is the second node N2 or the intermediate node N0.

The first output module 130 is configured to turn on or off according to at least the potential of the first node N1, and transmit the second clock signal to the output terminal OUT of the shift register when the first output module 130 is turned on, which means that the first output module 130 is turned on at least when the potential of the first node N1 is an effective potential signal, and transmits the second potential signal to the output terminal OUT of the shift register; at least when the potential of the first node N1 is the inactive potential signal, the first output module 130 is turned off, so that the second potential signal is not transmitted to the output terminal OUT of the shift register. The first output module 130 is configured to turn on or off according to at least the potential of the first node N1, and the turning on or off of the first output module 130 may be controlled by only the potential of the first node N1, or may be controlled by the potential of the first node N1 and other signals (or potentials of other nodes).

The second output control module 120 includes a first control unit 121 and a second control unit 122, the first control subunit 1211 of the first control unit 121 is configured to control the transmission of the first clock signal to the intermediate node N0 according to the potential of the first node N1, and the first control subunit 1211 transmits the potential of the first node N1 to the intermediate node N0 when the potential of the first node N1 is the active potential signal; the first control subunit 1211 controls the potential of the first node N1 not to be transmitted to the intermediate node N0 when the potential of the first node N1 is the invalid potential signal. The second control subunit 1212 of the first control unit 121 is configured to control a connection state between the intermediate node N0 and the second node N2 according to the second clock signal, where the second control subunit 1212 controls conduction between the intermediate node N0 and the second node N2 when the second clock signal is an active potential signal, so as to implement connection therebetween; and when the second clock signal is an invalid potential signal, the intermediate node N0 and the second node N2 are controlled to be disconnected. The second control unit 122 is configured to control transmission of the second potential signal to the second node N2 according to the first clock signal, which may mean that the second control unit 122 transmits the second potential signal to the second node N2 when the second clock signal is an active potential signal; the second control unit 122 controls the second potential signal not to be transmitted to the second node N2 when the second clock signal is the inactive potential signal.

The second output module 140 is configured to turn on or off according to a potential of the second node N2, and transmit the first potential signal to the output terminal OUT of the shift register when the second output module 140 is turned on, which may mean that the second output module 140 is turned on when the potential of the second node N2 is an effective potential signal, and transmits the second potential signal to the output terminal OUT of the shift register; when the potential of the second node N2 is the inactive potential signal, the second output module 140 is turned off, so that the second potential signal cannot be transmitted to the output terminal OUT of the shift register.

In this embodiment, the first control unit 121 includes a first control subunit 1211 and a second control subunit 1212, wherein the first control subunit 1211 may include a transistor, the function of the first control subunit 1211 in the shift register of this embodiment is equivalent to the function of the control transistor T03 in the shift register in the prior art shown in fig. 1, compared to the prior art, in this embodiment, a second control subunit 1212 is further disposed between the first control subunit 1211 and the second node N2, the second control subunit 1212 is controlled by the second clock signal, and since the second clock signal is a signal in which a high potential signal and a low potential signal periodically change, the second control subunit 1212 is turned on only when the second clock signal is an active potential signal, and therefore the second control subunit 1212 includes a stage in an off state, even if the threshold voltage of the transistor in the first control subunit 1211 is biased positively, which causes the transistor to have a larger self, due to the existence of the second control subunit 1212, the second control subunit 1211 acts between the second node N2 and the first control subunit 1211 to a certain value, so that the leakage current of the second control subunit N2 can be cut off, and the leakage current of the second control subunit N2 can be stabilized. Taking the example that the low potential signal is the effective potential signal, the first potential signal is the high potential signal, and the second potential signal is the low potential signal in the control signals and the potential signals of the nodes as an example, the working stage that the potential of the second node N2 is the low potential (the second output module 140 transmits the high potential signal of the first potential signal terminal VGH to the output terminal OUT of the shift register) will be described, because of the existence of the second control subunit 1212, the leakage of the second node N2 through the first control subunit 1211 will be reduced, and the low potential of the second node N2 can be well maintained. In this embodiment, the first output control module 110 is configured to control transmission of the first potential signal to the first node N1 according to the second clock signal and a potential of the setting node, where the setting node is the second node N2 or the intermediate node N0, and when the second control subunit 1212 is turned on, the potential of the intermediate node N0 is equal to the potential of the second node N2, and the low potential of the second node N2 is well maintained, so that the low potential of the intermediate node N0 can also be well maintained, and further, the first output control module 110 can be fully turned on according to the effective potential signal of the second clock signal and the low potential signal well maintained by the setting node, so that the high potential signal of the first potential signal terminal VGH is fully transmitted to the first node N1 by the first output control module 110, so that the first output module 130 is completely turned off according to the high potential signal, and further, when the shift register outputs the high potential signal, the second clock signal connected to the first output module 130 does not affect output to the output of the shift register, thereby ensuring stability of the output signal and being beneficial to improving display quality.

With reference to fig. 3, based on the foregoing technical solution, optionally, a control end of the first control subunit 1211 is electrically connected to the first node N1, a first end of the first control subunit 1211 is electrically connected to the first clock signal end SCK1, a second end of the first control subunit 1211 is electrically connected to a first end of the second control subunit 1212, a second end of the second control subunit 1212 is electrically connected to the second node N2, and a control end of the second control subunit 1212 is electrically connected to the second clock signal end SCK 2; the first clock signal terminal SCK1 is used for inputting a first clock signal, and the second clock signal terminal SCK2 is used for inputting a second clock signal; a second terminal of the first control subunit 1211 serves as an intermediate node N0.

Fig. 4 is a schematic structural diagram of another shift register according to an embodiment of the present invention, referring to fig. 4, optionally, the first control subunit 1211 includes a first transistor T1, a gate of the first transistor T1 is used as a control end of the first control subunit 1211, a first pole of the first transistor T1 is used as a first end of the first control subunit 1211, and a second pole of the first transistor T1 is used as a second end of the first control subunit 1211;

the second control subunit 1212 includes a second transistor T2, a gate of the second transistor T2 is used as a control terminal of the second control subunit 1212, a first pole of the second transistor T2 is used as a first terminal of the second control subunit 1212, and a second pole of the second transistor T2 is used as a second terminal of the second control subunit 1212.

In this embodiment, the second transistor T2 may play a certain role in blocking the leakage of the first transistor T1, and specifically, when the second transistor T2 is turned off, the second node N2 and the first transistor T1 may be blocked, which is favorable to ensure the stability of the potential of the second node N2 and is favorable to improve the output stability of the shift register.

On the basis of the above technical solution, optionally, the first transistor T1 and/or the second transistor T2 are double-gate transistors; further, the leakage of the first transistor T1 and/or the second transistor T2 can be further reduced, the stability of the potential of the second node N2 is further ensured, and the output reliability of the shift register is further improved

Fig. 5 is a schematic structural diagram of another shift register provided in an embodiment of the present invention, referring to fig. 5, optionally, the first output control module 110 includes a third control unit 111 and a fourth control unit 112, a control end of the third control unit 111 accesses the first clock signal, a first end of the third control unit 111 accesses the start signal, and a second end of the third control unit 111 is electrically connected to the first node N1;

a first control end A1 of the fourth control unit 112 is electrically connected to the set node, a second control end A2 of the fourth control unit 112 is connected to the second clock signal, a first end of the fourth control unit 112 is connected to the first potential signal, and a second end of the fourth control unit 112 is electrically connected to the first node N1.

Specifically, when the first clock signal is an active potential signal, the third control unit 111 is turned on to transmit the start signal to the first node N1; when the first clock signal is an inactive-potential signal, the third control unit 111 is turned off, and the start signal cannot be transmitted to the first node N1. When both the node and the second clock signal are set to be the effective potential signal, the fourth control unit 112 is turned on to transmit the first potential signal to the first node N1; when either one of the set node and the second clock signal is the inactive potential signal, the fourth control unit 112 is turned off, and the first potential signal cannot be transmitted to the first node N1.

Fig. 6 is a schematic structural diagram of another shift register according to an embodiment of the present invention, referring to fig. 6, optionally, the third control unit 111 includes a third transistor T3, a gate of the third transistor T3 is connected to the first clock signal, a first pole of the third transistor T3 is connected to the start signal, and a second pole of the third transistor T3 is electrically connected to the first node N1;

the fourth control unit 112 includes a fourth transistor T4 and a fifth transistor T5, a gate of the fourth transistor T4 is used as the first control terminal A1, a first pole of the fourth transistor T4 is used as the first terminal of the fourth control unit 112, a second pole of the fourth transistor T4 is electrically connected to a first pole of the fifth transistor T5, a second pole of the fifth transistor T5 is used as the second terminal of the fourth control unit 112, and a gate of the fifth transistor T5 is used as the second control terminal A2.

The third transistor T3 is turned on or off according to the first clock signal, and when the first clock signal is an active potential signal, the third transistor T3 transmits the start signal to the first node N1. The fourth transistor T4 is turned on or off according to the potential of the set node, and when the set node is an active potential signal, the fourth transistor T4 is turned on to transmit the first potential signal to the first pole of the fifth transistor T5; the fifth transistor T5 is turned on or off according to the second clock signal, and when the second clock signal is an active potential signal, the fifth transistor T5 is turned on to transmit the potential of the first electrode thereof to the first node N1. When the node is set and the second clock signal is an active potential signal, the fourth transistor T4 and the fifth transistor T5 are both turned on, and the first potential signal is transmitted to the first node N1.

Fig. 7 is a schematic structural diagram of another shift register according to an embodiment of the present invention, and referring to fig. 7, optionally, the third control unit 111 includes a third transistor T3, a gate of the third transistor T3 is connected to the first clock signal, a first pole of the third transistor T3 is connected to the start signal, and a second pole of the third transistor T3 is electrically connected to the first node N1; the fourth control unit 112 includes a fourth transistor T4 and a fifth transistor T5, a gate of the fourth transistor T4 is used as the second control terminal A2, a first pole of the fourth transistor T4 is used as the first terminal of the fourth control unit 112, a second pole of the fourth transistor T4 is electrically connected to a first pole of the fifth transistor T5, a second pole of the fifth transistor T5 is used as the second terminal of the fourth control unit 112, and a gate of the fifth transistor T5 is used as the first control terminal A1.

The fourth transistor T4 is turned on or off according to the second clock signal, and when the second clock signal is an active potential signal, the fourth transistor T4 is turned on to transmit the first potential signal to the first pole of the fifth transistor T5; the fifth transistor T5 is turned on or off according to the potential of the set node, and when the potential of the set node is the active potential signal, the fifth transistor T5 is turned on to transmit the potential of the first electrode thereof to the first node N1. When the node is set and the second clock signal is an active potential signal, the fourth transistor T4 and the fifth transistor T5 are both turned on, and the first potential signal is transmitted to the first node N1.

Fig. 8 is a schematic structural diagram of another shift register according to an embodiment of the present invention, referring to fig. 8, optionally, the second control unit 122 includes a sixth transistor T6, a gate of the sixth transistor T6 is connected to the first clock signal, a first pole of the sixth transistor T6 is connected to the second potential signal, and a second pole of the sixth transistor T6 is electrically connected to the second node N2.

Specifically, the sixth transistor T6 is turned on or off under the control of the first clock signal. When the first clock signal is an active potential signal, the sixth transistor T6 is turned on, and transmits the second potential signal to the second node N2; when the second clock signal is the inactive level signal, the sixth transistor T6 is turned off, and the second level signal cannot be transmitted to the second node N2.

Fig. 9 is a schematic structural diagram of another shift register provided in an embodiment of the present invention, referring to fig. 9, optionally, the first output module 130 includes a seventh transistor T7 and a first capacitor C1, a gate of the seventh transistor T7 is electrically connected to the first node N1, a first pole of the seventh transistor T7 is connected to the second clock signal, and a second pole of the seventh transistor T7 is electrically connected to the output end OUT of the shift register; a first end of the first capacitor C1 is electrically connected to the gate of the seventh transistor T7, and a second end of the first capacitor C1 is electrically connected to the second pole of the seventh transistor T7; the second output module 140 includes an eighth transistor T8 and a second capacitor C2, a gate of the eighth transistor T8 is electrically connected to the second node N2, a first pole of the eighth transistor T8 is connected to the first potential signal, and a second pole of the eighth transistor T8 is electrically connected to the output end OUT of the shift register; a first end of the second capacitor C2 is electrically connected to the gate of the eighth transistor T8, and a second end of the second capacitor C2 is electrically connected to the first pole of the eighth transistor T8.

Specifically, the seventh transistor T7 is turned on or off according to the potential of the first node N1. When the potential of the first node N1 is an effective potential signal, the seventh transistor T7 is turned on, and transmits the second clock signal to the output terminal OUT of the shift register; when the potential of the first node N1 is the invalid potential signal, the seventh transistor T7 is turned off. The first capacitor C1 can store and hold the potential of the first node N1.

The eighth transistor T8 is turned on or off according to the potential of the second node N2. When the potential of the second node N2 is the effective potential signal, the eighth transistor T8 is turned on, and transmits the first potential signal to the output terminal OUT of the shift register; when the potential of the second node N2 is the inactive potential signal, the eighth transistor T8 is turned off. The second capacitor C2 may store and hold the potential of the second node N2.

Fig. 10 is a schematic structural diagram of another shift register provided in an embodiment of the present invention, referring to fig. 10, optionally, the first control subunit 1211 includes a first transistor T1, the second control subunit 1212 includes a second transistor T2, the first output control module 110 includes a third control unit 111 and a fourth control unit 112, the third control unit 111 includes a third transistor T3, the fourth control unit 112 includes a fourth transistor T4 and a fifth transistor T5, a gate of the fourth transistor T4 is connected to the second node N2, the second control unit 122 includes a sixth transistor T6, the first output module 130 includes a seventh transistor T7 and a first capacitor C1, and the second output module 140 includes an eighth transistor T8 and a second capacitor C2. Each transistor in the shift register may be a P-type transistor or an N-type transistor, which is not limited herein in this embodiment, and fig. 10 schematically illustrates a case where each transistor is a P-type transistor. Fig. 11 is a timing diagram of driving a shift register according to an embodiment of the present invention, where the timing diagram can be used to drive the shift register according to any of the above embodiments of the present invention. The operation of the shift register shown in fig. 10 will be described below. Optionally, the first potential signal is a high potential signal, and the second potential signal is a low potential signal. Referring to fig. 10 and 11, the operation of the shift register includes the following stages.

In the first stage t1, the start signal is at a low potential, the first clock signal is at a low potential, and the second clock signal is at a high potential. The third transistor T3 is turned on in response to a first clock signal having a low potential, the start signal having the low potential is transmitted to the first node N1 through the third transistor T3, and the seventh transistor T7 is turned on in response to a low potential signal of the first node N1, and transmits a second clock signal having the high potential to the output terminal OUT of the shift register. The sixth transistor T6 is turned on in response to the first clock signal having a low potential, the second potential signal (low potential signal) is transmitted to the second node N2 through the sixth transistor T6, and the eighth transistor T8 is turned on in response to the low potential signal of the second node N2, and the first potential signal (high potential signal) is transmitted to the output terminal OUT of the shift register through the eighth transistor T8.

In the second stage t2, the start signal is at a high level, the first clock signal is at a high level, and the second clock signal is at a low level. The third transistor T3 and the sixth transistor T6 are turned off in response to the first clock signal of a high potential. Due to the storage and holding function of the first capacitor C1, the first node N1 holds the low potential of the previous stage, the seventh transistor T7 is kept turned on according to the low potential of the first node N1, and the second clock signal of the low potential is transmitted to the output terminal OUT of the shift register. The first transistor T1 is turned on in response to a low potential of the first node N1, the second transistor T2 is turned on in response to a second clock signal of a low potential, the first clock signal of a high potential is transmitted to the second node N2 through the first transistor T1 and the second transistor T2, and the eighth transistor T8 is turned off in response to a high potential of the second node N2.

In the third stage t3, the start signal is at a high level, the first clock signal is at a low level, and the second clock signal is at a high level. The third transistor T3 is turned on in response to the first clock signal of the low potential, the start signal of the high potential is transmitted to the first node N1 through the third transistor T3, and the seventh transistor T7 is turned off in response to the high potential signal of the first node N1. The sixth transistor T6 is turned on in response to the first clock signal having a low potential, the second potential signal (low potential signal) is transmitted to the second node N2 through the sixth transistor T6, and the eighth transistor T8 is turned on in response to the low potential signal of the second node N2, and the first potential signal (high potential signal) is transmitted to the output terminal OUT of the shift register through the eighth transistor T8.

In the fourth stage t4, the start signal is at a high level, the first clock signal is at a high level, and the second clock signal is at a low level. The third transistor T3 and the sixth transistor T6 are turned off in response to the first clock signal of a high potential. Due to the storage and holding function of the second capacitor C2, the second node N2 maintains the low potential of the previous stage, the eighth transistor T8 remains turned on according to the low potential of the second node N2, the first potential signal is transmitted to the output terminal OUT of the shift register, and thus the output terminal OUT of the shift register outputs a high potential signal. The fourth transistor T4 is turned on in response to the low potential of the second node N2, the fifth transistor T5 is turned on in response to the second clock signal having the low potential, the first potential signal is transmitted to the first node N1 through the fourth transistor T4 and the fifth transistor T5, the seventh transistor T7 is turned off in response to the high potential of the first node N1 (when the connection relationship of the fourth transistor T4 and the fifth transistor T5 is the same as that shown in the drawing, the fourth transistor T4 is turned on in response to the second clock signal having the low potential, the fifth transistor T5 is turned on in response to the low potential of the second node N2, the first potential signal is transmitted to the first node N1 through the fourth transistor T4 and the fifth transistor T5, and the seventh transistor T7 is turned off in response to the high potential of the first node N1).

The working process of the fifth stage t5 is the same as the working process of the third stage t3, and the working process of the sixth stage t6 is the same as the working process of the fourth stage t 4. In one frame, after the fourth stage t4, the working processes of the third stage t3 and the fourth stage t4 are continuously repeated, which is not described herein again.

With continued reference to fig. 10, optionally, the shift register further includes a ninth transistor T9, a gate of the ninth transistor T9 is connected to the second potential signal, a first pole of the ninth transistor T9 is electrically connected to the first node N1, and a second pole of the ninth transistor T9 is electrically connected to the first output module 130;

the first output module 130 is configured to turn on or off according to the potential of the first node N1 and the second potential signal.

The ninth transistor T9 is always controlled to be in a conducting state by the second potential signal input from the second potential signal terminal VGL, for example, when the ninth transistor T9 is a P-type transistor, the second potential signal input from the second potential signal input terminal is a low potential signal. The ninth transistor T9 is disposed between the first output module 130 (i.e., the seventh transistor T7) and the first node N1, and at this time, the gates of the first output module 130 and the seventh transistor T7 are indirectly connected, so that the ninth transistor T9 can bear a certain voltage drop, thereby reducing the risk of breakdown of the seventh transistor T7 and improving the reliability of the shift register. When the shift register further includes a ninth transistor T9, the first output module 130 is turned on or off according to the potential of the first node N1 and the second potential signal, specifically, the second potential signal is an effective potential signal for controlling the ninth transistor T9 to be turned on, and when the potential of the first node N1 is also an effective potential signal, the effective potential signal of the first node N1 is transmitted to the first output module 130, so that the first output module 130 is turned on.

Note that fig. 1 to 10 each illustrate an example in which the set node is the second node N2. Fig. 12 is a schematic structural diagram of another shift register according to an embodiment of the present invention, and fig. 12 shows a case where the set node is the intermediate node N0. Referring to fig. 12, optionally, the first control subunit 1211 includes a first transistor T1, the second control subunit 1212 includes a second transistor T2, the first output control module 110 includes a third control unit 111 and a fourth control unit 112, the third control unit 111 includes a third transistor T3, the fourth control unit 112 includes a fourth transistor T4 and a fifth transistor T5, a gate of the fourth transistor T4 is connected to the intermediate node N0, the second control unit 122 includes a sixth transistor T6, the first output module 130 includes a seventh transistor T7 and a first capacitor C1, and the second output module 140 includes an eighth transistor T8 and a second capacitor C2. Each transistor in the shift register may be a P-type transistor or an N-type transistor, which is not limited herein in this embodiment, and fig. 12 schematically illustrates a case where each transistor is a P-type transistor. The driving timing shown in fig. 11 is also applicable to driving the shift register shown in fig. 12. Optionally, the first potential signal is a high potential signal, and the second potential signal is a low potential signal. Referring to fig. 11 and 12, the operation of the shift register includes the following stages.

The operation process at the first stage t1 is the same as the operation process at the first stage t1 of the shift register shown in fig. 10, and is not described herein again.

The operation process in the second stage t2 is the same as the operation process in the first stage t1 of the shift register shown in fig. 10, and is not described herein again. Since the first transistor T1 is turned on, the high-level first clock signal is also transmitted to the intermediate node N0 through the first transistor T1, and the fourth transistor T4 is turned off according to the potential of the intermediate node N0.

The operation process in the third stage t3 is the same as the operation process in the third stage t3 of the shift register shown in fig. 10, and is not described herein again.

In the fourth period t4, the start signal is at a high level, the first clock signal is at a high level, and the second clock signal is at a low level. The third transistor T3 and the sixth transistor T6 are turned off in response to the first clock signal of a high potential. Due to the storage and holding function of the second capacitor C2, the second node N2 maintains the low potential of the previous stage, the eighth transistor T8 is kept turned on according to the low potential of the second node N2, the first potential signal is transmitted to the output terminal OUT of the shift register, and thus the output terminal OUT of the shift register outputs a high potential signal. The second transistor T2 is turned on in response to a low potential of the second node N2, the fourth transistor T4 is turned on in response to a low potential of the intermediate node N0, the fifth transistor T5 is turned on in response to a second clock signal of a low potential, the first potential signal is transmitted to the first node N1 through the fourth transistor T4 and the fifth transistor T5, and the seventh transistor T7 is turned off in response to a high potential of the first node N1.

As can be seen from the above-mentioned operation of the shift register shown in fig. 10 and 12, in the third stage t3, the second node N2 is at a low potential. In addition, in the third stage T3, the second transistor T2 is turned off in response to the second clock signal with a high voltage level, so that the second node N2 and the first transistor T1 can be turned off, that is, the second node N2 and the first transistor T1 cannot be connected, and thus the voltage loss of the second node N2 due to the leakage of the first transistor T1 can be reduced, so that the voltage level of the second node N2 can be kept stable, and the eighth transistor T8 can be completely turned on according to the low voltage level of the stable setting node (the second node N2 or the fixed node). In addition, because the low potential of the second node N2 can be stably maintained, the fourth transistor T4 controlled by the set node can be completely turned on, and the first potential signal can be completely transmitted to the second pole of the fourth transistor T4 (i.e., the first pole of the fifth transistor T5), so that after the second clock signal jumps to the low potential in the fourth stage T4 to turn on the fifth transistor T5, the first potential signal can be completely transmitted to the first node N1, and it is ensured that the seventh transistor T7 is completely turned off, so that the shift register can stably output the high potential signal without being affected by the jump of the second clock signal, and the stability of the output signal of the shift register is ensured.

Fig. 13 is a schematic diagram of an output signal of a shift register according to an embodiment of the present invention. It can be known from fig. 13 and fig. 2 that the shift register according to the embodiment of the present invention has almost no fluctuation when outputting high potential signals, and the output signals are stable, thereby being favorable for improving the display quality.

The embodiment of the present invention further provides a gate driving circuit, and fig. 14 is a schematic structural diagram of a gate driving circuit provided by the embodiment of the present invention, referring to fig. 14, the gate driving circuit includes a plurality of shift registers 100 in any of the above embodiments, and a plurality of shift registers 100 are cascade-connected.

The embodiment of the present invention further provides a display panel, fig. 15 is a schematic structural diagram of a display panel provided by the embodiment of the present invention, referring to fig. 15, the display panel 200 includes the gate driving circuit provided by the above embodiment, and further includes a first clock signal line 210, a second clock signal line 220, a first potential signal line 230, and a second potential signal line 240;

the shift register 100 includes a first clock signal terminal SCK1 and a second clock signal terminal SCK2, the first clock signal line 210 is electrically connected to the first clock signal terminal SCK1, and the second clock signal line 220 is electrically connected to the second clock signal terminal SCK 2;

the first potential signal line 230 is electrically connected to a first potential signal terminal VGH, and the second potential signal line 240 is electrically connected to a second potential signal terminal VGL.

The display panel may be, for example, an organic light emitting diode display panel, a liquid crystal display panel, or an electronic paper display panel. The output terminal OUT of each stage of the shift register is electrically connected to the gate driving signal line 260 on the display panel, and transmits a gate driving signal to each gate driving signal line 260. Referring to fig. 9, the display panel further includes a start signal line 250, and the start signal terminal SIN of the first stage shift register is electrically connected to the start signal line 250, shifts the start signal on the start signal line 250, and outputs the shifted start signal through the output terminal of the shift register. In the adjacent two stages of shift registers, the next stage shift register shifts and outputs the signal output by the previous stage shift register. Therefore, the embodiment of the present invention provides a display panel that realizes the function of outputting signals (for example, scanning signals) line by line, and the signal stability output by each stage of shift register is good.

Fig. 16 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and referring to fig. 16, optionally, the gate driving circuit is disposed on two sides of the display panel. Because the gate driving signal lines 260 have certain impedance and capacitive reactance, the gate driving circuits are arranged on two sides of the display panel, and in the gate driving circuits on two sides, the same gate driving signal lines 260 can be connected to the same level shift register, namely, the gate driving signals are provided for the gate driving signal lines 260 from two sides, so that the influence of the impedance and capacitive reactance on the gate driving signal lines 260 on the display effect can be reduced, the display in the display panel is more uniform, and the display effect is improved.

It should be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles applied thereto. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the scope of the present invention.

Claims (10)

1. A shift register, comprising: the device comprises a first output control module, a second output control module, a first output module and a second output module;

the first output control module is used for controlling the transmission of the initial signal to the first node according to the first clock signal and controlling the transmission of the first potential signal to the first node according to the second clock signal and the potential of the set node; the first output module is used for being switched on or switched off at least according to the potential of the first node and transmitting a second clock signal to the output end of the shift register when the first output module is switched on;

the second output control module comprises a first control unit and a second control unit, the first control unit comprises a first control subunit and a second control subunit, and the first control subunit is used for controlling the transmission of the first clock signal to the middle node according to the potential of the first node; the second control subunit is used for controlling the connection state of the intermediate node and the second node according to a second clock signal; the second control unit is used for controlling the transmission of a second potential signal to the second node according to the first clock signal;

the second output module is used for being switched on or switched off according to the potential of the second node and transmitting a first potential signal to the output end of the shift register when the second output module is switched on;

wherein the setting node is the second node or the intermediate node.

2. The shift register according to claim 1, wherein a control terminal of the first control subunit is electrically connected to the first node, a first terminal of the first control subunit is electrically connected to a first clock signal terminal, a second terminal of the first control subunit is electrically connected to a first terminal of the second control subunit, a second terminal of the second control subunit is electrically connected to the second node, and a control terminal of the second control subunit is electrically connected to a second clock signal terminal; the first clock signal terminal is used for inputting the first clock signal, and the second clock signal terminal is used for inputting the second clock signal;

and the second end of the first control subunit is used as the intermediate node.

3. The shift register according to claim 1, wherein the first control subunit comprises a first transistor, a gate of the first transistor is used as a control terminal of the first control subunit, a first pole of the first transistor is used as a first terminal of the first control subunit, and a second pole of the first transistor is used as a second terminal of the first control subunit;

the second control subunit comprises a second transistor, a gate of the second transistor is used as a control end of the second control subunit, a first pole of the second transistor is used as a first end of the second control subunit, and a second pole of the second transistor is used as a second end of the second control subunit.

4. The shift register according to claim 1 or 2, wherein the first output control module comprises a third control unit and a fourth control unit, a control terminal of the third control unit is connected to the first clock signal, a first terminal of the third control unit is connected to a start signal, and a second terminal of the third control unit is electrically connected to the first node;

the first control end of the fourth control unit is electrically connected with the set node, the second control end of the fourth control unit is connected to the second clock signal, the first end of the fourth control unit is connected to the first potential signal, and the second end of the fourth control unit is electrically connected with the first node.

5. The shift register according to claim 4, wherein the third control unit comprises a third transistor, a gate of the third transistor is connected to the first clock signal, a first pole of the third transistor is connected to the start signal, and a second pole of the third transistor is electrically connected to the first node;

the fourth control unit comprises a fourth transistor and a fifth transistor, a gate of the fourth transistor is used as the first control terminal, a first pole of the fourth transistor is used as the first terminal of the fourth control unit, a second pole of the fourth transistor is electrically connected with a first pole of the fifth transistor, a second pole of the fifth transistor is used as the second terminal of the fourth control unit, and a gate of the fifth transistor is used as the second control terminal;

alternatively, a gate of the fourth transistor is used as the second control terminal, a first pole of the fourth transistor is used as the first terminal of the fourth control unit, a second pole of the fourth transistor is electrically connected to a first pole of the fifth transistor, a second pole of the fifth transistor is used as the second terminal of the fourth control unit, and a gate of the fifth transistor is used as the first control terminal.

6. The shift register according to claim 1, wherein the second control unit comprises a sixth transistor, a gate of the sixth transistor is connected to the first clock signal, a first pole of the sixth transistor is connected to the second potential signal, and a second pole of the sixth transistor is electrically connected to the second node.

7. The shift register according to claim 1, wherein the first output module comprises a seventh transistor and a first capacitor, a gate of the seventh transistor is electrically connected to the first node, a first pole of the seventh transistor is connected to the second clock signal, and a second pole of the seventh transistor is electrically connected to the output terminal of the shift register; a first end of the first capacitor is electrically connected with a grid electrode of the seventh transistor, and a second end of the first capacitor is electrically connected with a second pole of the seventh transistor; the second output module comprises an eighth transistor and a second capacitor, the grid electrode of the eighth transistor is electrically connected with the second node, the first electrode of the eighth transistor is connected to the first potential signal, and the second electrode of the eighth transistor is electrically connected with the output end of the shift register; a first end of the second capacitor is electrically connected to the gate of the eighth transistor, and a second end of the second capacitor is electrically connected to the first pole of the eighth transistor.

8. The shift register of claim 1, further comprising a ninth transistor, a gate of the ninth transistor being connected to the second potential signal, a first pole of the ninth transistor being electrically connected to the first node, and a second pole of the ninth transistor being electrically connected to the first output module;

the first output module is used for being switched on or switched off according to the potential of the first node and the second potential signal.

9. A gate driver circuit comprising a plurality of shift registers according to any one of claims 1 to 8, each of the shift registers being connected in cascade.

10. A display panel comprising the gate driver circuit according to claim 9.

Images