CN218301373U - Jitter regulating circuit of phase interpolator - Google Patents

Abstract

The utility model discloses a phase interpolator's shake regulating circuit, include: the phase interpolation controller, the rate converter, the phase accumulator, the phase interpolator, the first frequency divider and the second frequency divider, wherein the input end of the rate converter is connected with the output end of the phase interpolation controller, and the output end of the rate converter is connected with the input end of the phase accumulator; the output end of the phase accumulator is connected with the input end of the phase interpolator; the phase interpolator is arranged to receive a phase locked loop clock signal and an output signal of the phase accumulator and to output a clock signal; the output end of the phase interpolator is respectively connected with the input end of the phase accumulator and the input end of the rate converter through a first frequency divider, and is connected with the input end of the phase interpolation controller through a second frequency divider. The jitter adjusting circuit of the phase interpolator provided by the embodiment of the disclosure adds a new frequency divider and a new rate converter, so that the phase interpolator and the phase interpolation controller can adopt clock signals with different frequencies, and the precision is increased.

Description

Jitter regulating circuit of phase interpolator

Technical Field

The embodiment of the disclosure relates to the technical field of circuit design, in particular to a jitter adjusting circuit of a phase interpolator.

Background

In the prior art, in order to effectively reduce Electromagnetic Interference (EMI), a signal transmitting end usually adopts a spread spectrum technique, and a data frequency of the transmitting end is slightly changed based on a vicinity of a center frequency due to a spread spectrum function. Meanwhile, in order to accurately sample the received data, the phase interpolator is usually used to obtain the optimal sampling phase at the receiving end, and therefore, the phase interpolator is often used in a clock recovery circuit and a frequency adjustment circuit.

In the related art, a phase interpolation controller circuit includes: phase difference value controller, phase difference value ware, phase accumulator, rate converter, first frequency divider and second frequency divider, wherein: the speed converter is respectively connected with the phase difference value controller and the phase accumulator, the phase difference value device is connected with the phase difference value controller through the first frequency divider, and the phase difference value device is respectively connected with the speed converter and the phase accumulator through the second frequency divider.

SUMMERY OF THE UTILITY MODEL

The embodiment of the disclosure provides a novel jitter adjusting circuit of a phase interpolator, which adds a novel frequency divider and a novel rate converter, so that the phase interpolator and a phase interpolation controller can adopt clock signals with different frequencies, and the precision is improved.

In one aspect, an embodiment of the present disclosure provides a jitter adjusting circuit for a phase interpolator, including: the method comprises the following steps: phase interpolation controller, rate converter, phase accumulator, phase interpolator, first frequency divider and second frequency divider, wherein:

the input end of the speed converter is connected with the output end of the phase interpolation controller, and the output end of the speed converter is connected with the input end of the phase accumulator;

the output end of the phase accumulator is connected with the input end of the phase interpolator;

the phase interpolator is arranged to receive a phase locked loop clock signal and an output signal of the phase accumulator and to output a clock signal; the output end of the phase interpolator is respectively connected with the input end of the phase accumulator and the input end of the rate converter through a first frequency divider, and is connected with the input end of the phase interpolation controller through a second frequency divider.

Compared with the related art, the novel jitter adjusting circuit of the phase interpolator, which is provided by the embodiment of the disclosure, is additionally provided with the novel frequency divider and the novel rate converter, so that the phase interpolator and the phase interpolation controller can adopt clock signals with different frequencies, and the precision is increased.

Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the disclosure. Other advantages of the disclosure may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification and the drawings.

Drawings

The accompanying drawings are included to provide an understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.

FIG. 1 is a schematic diagram of a conventional phase interpolator circuit according to an embodiment of the present disclosure;

FIG. 2 is a diagram illustrating a jitter adjustment circuit of a phase interpolator according to an embodiment of the disclosure;

fig. 3 is a schematic structural diagram of a rate converter in a jitter adjusting circuit of a phase interpolator according to an embodiment of the disclosure;

fig. 4 is a schematic structural diagram of a phase accumulator in a jitter adjusting circuit of a phase interpolator according to an embodiment of the disclosure;

fig. 5 is a schematic structural diagram of a phase interpolator in a jitter adjusting circuit of the phase interpolator according to an embodiment of the disclosure;

FIG. 6 is a schematic diagram illustrating a structure of a phase interpolation controller in a jitter adjusting circuit of a phase interpolator according to an embodiment of the disclosure;

FIG. 7 is a schematic diagram of a jitter adjustment circuit for another phase interpolator in accordance with an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a circuit signal waveform of a conventional phase interpolator circuit according to an embodiment of the present disclosure;

FIG. 9 is a schematic diagram of a circuit signal waveform of a jitter adjusting circuit of a phase interpolator according to an embodiment of the disclosure;

FIG. 10 is an eye diagram of a prior art phase interpolator circuit according to an embodiment of the present disclosure;

fig. 11 is an eye diagram of a jitter adjusting circuit of a phase interpolator according to an embodiment of the disclosure.

Detailed Description

The present disclosure describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible that are within the scope of the embodiments described in this disclosure. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.

The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements of the present disclosure that have been disclosed may also be combined with any conventional features or elements to form unique aspects as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other aspects to form yet another unique aspect as defined by the claims. Thus, it should be understood that any features shown and/or discussed in this disclosure may be implemented alone or in any suitable combination. Accordingly, the embodiments are not limited except as by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

Further, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other orders of steps are possible as will be understood by those of ordinary skill in the art. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Further, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present disclosure.

The output clock jitter of the phase interpolator of the prior art is relatively large, and a design circuit generally adopted by the prior art is shown in fig. 1 and comprises:

phase interpolation controller 11, phase accumulator 12, phase interpolator 13 and frequency divider 14 (assuming an n-divider), where:

the phase interpolation controller 11 is configured to determine, according to the clock signal, an offset step increment of a current offset step update period when the clock signal divided by the frequency divider 14 is received, and send the offset step increment to the phase accumulator 12;

the phase accumulator 12 is configured to perform cumulative calculation on the offset step increment of the current offset step update period sent by the phase interpolation controller 11 and the offset step of the historical offset step update period to obtain a new offset step of the current offset step update period; and is further configured to send the offset step of the current offset step update period to the phase interpolator 13 each time the clock signal divided by the frequency divider 14 is received;

the phase interpolator 13 is configured to receive a phase-locked loop clock signal, perform step offset on the phase-locked loop clock signal according to an offset step of the current offset step update cycle sent by the phase accumulator 12, and output the clock signal.

The phase interpolator is usually a common module of a clock recovery circuit and a frequency adjustment circuit, and if the period of an input clock signal is T, the phase interpolator can output a clock signal with a phase of T × SEL/N, where SEL is a phase control signal, N is an adjustable phase number of the phase interpolator, SEL = phase _ SEL [7:0], N =256, and the phase interpolator selects and outputs a clock (CLK _ PI) with a corresponding phase according to a value of phase _ SEL [7:0] based on a phase locked loop clock (CLK _ SRC) sent by a phase locked loop. Generally, the operation logic of the phase interpolation controller is complex, which greatly limits the operation speed, and on the other hand, in order to follow the phase locked loop clock (CLK _ SRC) in time, the update step size phase _ add _ tmp1 of the phase interpolator is set to be large, and the large update step size causes the jitter of the phase interpolator clock (CLK _ PI) to be large.

The embodiment of the present disclosure provides a jitter adjusting circuit of a phase interpolator, as shown in fig. 2, including: phase interpolation controller 21, rate converter 22, phase accumulator 23, phase interpolator 24, first frequency divider 25, and second frequency divider 26, wherein:

the input end of the rate converter 22 is connected with the output end of the phase interpolation controller 24, and the output end is connected with the input end of the phase accumulator 23;

the output end of the phase accumulator 23 is connected with the input end of the phase interpolator 24;

said phase interpolator 24 is arranged to receive a phase locked loop clock signal and an output signal of said phase accumulator 23 and to output a clock signal; the output of the phase interpolator 24 is connected via a first frequency divider 25 to the input of the phase accumulator 23 and to the input of the rate converter 22, respectively, and via a second frequency divider 26 to the input of the phase interpolation controller 24.

The jitter adjusting circuit of the phase interpolator provided by the embodiment of the application is additionally provided with the new frequency divider and the new rate converter, so that the phase interpolator and the phase interpolation controller can adopt clock signals with different frequencies, and the precision is increased.

As shown in fig. 3, the rate converter 22 includes:

a storage unit 221 configured to store the number of cycles of offset step update, the number of sub-cycles of offset step update specified in advance, and the offset sub-step increment p of each offset step update sub-cycle calculated by the calculation unit 223;

a receiving unit 222, serving as an input terminal of the rate converter 22, configured to receive, from the phase interpolation controller, an offset step increment P of a current offset step update period and a clock signal divided by a first frequency divider;

a calculating unit 223 configured to calculate an offset sub-step increment P of each offset step update sub-period according to the received offset step increment P of the current offset step update period, the number of offset step update periods stored in the storage unit 221, and the number of pre-specified offset step update sub-periods;

a sending unit 224, which is an output terminal of the rate converter, is configured to send the offset sub-step increment of the current offset step update sub-cycle stored by the storage unit 221 to the phase accumulator 23 each time the receiving unit 222 receives the clock signal divided by the first frequency divider.

As shown in fig. 4, the phase accumulator includes 23:

an accumulator 231 configured to perform accumulation calculation on the offset sub-step increment of the current offset step update sub-period sent by the rate converter 22 and the offset sub-step of the historical offset step update sub-period stored in the buffer unit 232 to obtain a new offset sub-step of the current offset step update sub-period;

a buffer unit 232 configured to store the offset sub-step of the new current offset step update sub-period;

a receiving unit 233, which is an input terminal of the phase accumulator 23 and is configured to receive the offset sub-step increment p of the current offset step updating sub-period sent by the rate converter and the clock signal divided by the first frequency divider;

a transmitting unit 234, which is an output of the phase accumulator 23, is arranged to transmit the offset sub-step of the new current offset step update sub-period in the buffer unit 232 to the phase interpolator 24 each time the receiving unit 233 receives the clock signal divided by the first frequency divider 25.

The offset sub-step of the historical offset step update sub-period refers to the offset sub-step of the previous offset step update sub-period.

As shown in fig. 5, the phase interpolator 24 includes:

a receiving unit 241, which is an input terminal of the phase interpolator 24 and is configured to receive a phase-locked loop clock signal and an offset sub-step of the current offset step update sub-period sent by the phase accumulator 23;

an offset unit 242, configured to offset the phase-locked loop clock signal according to the offset sub-step of the current offset step update sub-period received by the receiving unit;

an output unit 243, as an output of the phase interpolator 24, is arranged to output the clock signal shifted by the shifting unit.

The embodiment of the present disclosure further provides a jitter adjustment circuit of a phase interpolator, as shown in fig. 6, the phase interpolation controller 21 includes:

a receiving unit 211, as an input of the phase interpolation controller 21, configured to receive the clock signal frequency-divided by the second frequency divider 26;

a calculation unit 212 arranged to determine an offset step increment P of a current offset step update period each time the reception unit 211 receives the clock signal divided by the second frequency divider 26;

a transmitting unit 213, which is an output terminal of the phase interpolation controller 21, is configured to transmit the offset step increment P of the current offset step update period determined by the calculating unit 212 to the rate converter 22 every time the receiving unit 211 receives the clock signal divided by the second frequency divider 26.

The second frequency divider is an n-frequency divider, and n = number of cycles of offset step update;

the first divider is an m divider, m = number of sub-periods of offset step update.

Illustratively, n is an integer multiple of m.

Wherein, the number of cycles of the offset step update refers to: the offset step is updated at intervals of clock cycles, namely, the offset step is updated at intervals of clock cycles; the number of cycles of offset sub-step update refers to: the number of clock cycles between which the offset sub-step is updated, i.e. how many clock cycles the offset sub-step is updated.

Compared with the prior art, the jitter adjusting circuit of the phase interpolator provided by the embodiment of the application improves the updating speed of the control word by adding the rate converter, thereby reducing the updating step length and achieving the purpose of reducing the jitter of the clock signal (CLK _ PI) of the phase interpolator.

Illustratively, the offset sub-step increment P of each offset step update sub-period is P m/n when P m can be divided by n.

Illustratively, when P m cannot be divided by n, the offset sub-step increment P of each offset step update sub-period is

Or

And the sum of the increment of the offset sub-step of all the offset step updating sub-periods in one offset step updating period is P.

The disclosed embodiment further provides a jitter adjusting circuit of a Phase interpolator, as shown in fig. 7, assuming that the Phase interpolation controller updates the offset Step size every 8 clock cycles, assuming that the Phase offset Step size is expected to be P (corresponding to Phase _ add _ x4[7:0] in fig. 7) every time, and assuming that the rate converter needs to update the offset Step sub-Step size (Step) every 2 clock cycles, each Phase offset Step size (Step 0, step1, step2, step 3) is P/4 (corresponding to Phase _ add _ x1[7:0] M + N/4 in fig. 7), where M is a quotient, N is a remainder, and N = 0-3, and the accuracy before and after rate conversion can be kept unchanged by selecting each Phase offset Step size through table 1.

Compared with the circuit signal waveform schematic diagram of the prior phase interpolator circuit shown in fig. 8 (assuming that the circuit phase interpolation controller updates the offset step size every 8 clock cycles), the circuit signal waveform schematic diagram of the jitter adjusting circuit of the phase interpolator corresponding to fig. 7 is shown in fig. 8, where phase _ add _ x4 in fig. 8 is the offset step increment of each current offset step update cycle, and phase _ add _ sel is the offset step of each offset step update cycle; phase _ add _ x4 in fig. 9 is an offset step increment per current offset step update period, phase _ add _ x1 is an offset sub-step increment per current offset sub-step update period, and phase _ add _ sel is an offset sub-step per offset sub-step update period. CLK _ PI is phase-changed and output according to phase _ add _ sel based on the received CLK _ SRC.

As can be seen from a comparison of fig. 10 and 11, in the conventional phase interpolator circuit, at the update of the offset step update period, i.e., the circled position, the waveform of the clock signal CLK _ PI output from the phase interpolator varies greatly, and therefore jitter is large; in the jitter adjusting circuit of the phase interpolator provided by the embodiment of the disclosure, at the update position of the offset step update period, the waveform of the clock signal CLK _ PI output by the phase interpolator has little change, and hardly sees any change, so that the jitter is very small.

The clock signal CLK _ PI eye diagram of the conventional phase interpolator circuit is shown in fig. 10, the clock signal CLK _ PI eye diagram of the jitter adjusting circuit of the phase interpolator provided by the embodiment of the present disclosure is shown in fig. 11, and comparing fig. 10 and 11, it can be seen that the jitter of the clock signal eye diagram of the jitter adjusting circuit (the circuit structure of which is shown in fig. 7) is reduced by 68% compared with the clock signal jitter of the conventional phase interpolator circuit (the circuit structure of which is shown in fig. 1) (the jitter is reduced from 17.3ps to 5.6 ps)

Although the embodiments of the present invention have been described above, the description is only for the convenience of understanding the present invention, and the present invention is not limited thereto. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (9)

1. A jitter adjustment circuit for a phase interpolator, comprising: phase interpolation controller, rate converter, phase accumulator, phase interpolator, first frequency divider and second frequency divider, wherein:

the input end of the speed converter is connected with the output end of the phase interpolation controller, and the output end of the speed converter is connected with the input end of the phase accumulator;

the output end of the phase accumulator is connected with the input end of the phase interpolator;

the phase interpolator is arranged to receive a phase locked loop clock signal and an output signal of the phase accumulator and to output a clock signal; the output end of the phase interpolator is respectively connected with the input end of the phase accumulator and the input end of the speed converter through a first frequency divider, and is connected with the input end of the phase interpolation controller through a second frequency divider.

2. The jitter adjustment circuit of a phase interpolator of claim 1, wherein the rate converter comprises:

the storage unit is set to store the number of cycles of updating the offset step, the number of sub-cycles of updating the pre-specified offset step and the offset sub-step increment p of each offset step updating sub-cycle calculated by the calculation unit;

a receiving unit, as an input terminal of the rate converter, configured to receive, from the phase interpolation controller, an offset step increment P of a current offset step update period, and a clock signal divided by a first frequency divider;

the calculating unit is set to calculate the offset step increment P of each offset step updating sub-period according to the received offset step increment P of the current offset step updating period, the number of offset step updating periods stored in the storage unit and the number of pre-specified offset step updating sub-periods;

and the sending unit is used as the output end of the rate converter and is arranged to send the offset sub-step increment of the current offset step updating sub-period stored by the storage unit to the phase accumulator every time the receiving unit receives the clock signal which is divided by the first frequency divider.

3. The phase interpolator jitter adjustment circuit of claim 1, wherein the phase accumulator comprises:

the accumulator is set to carry out accumulation calculation on the offset sub-step increment of the current offset step updating sub-period sent by the rate converter and the offset sub-step of the historical offset step updating sub-period stored by the cache unit to obtain a new offset sub-step of the current offset step updating sub-period;

a buffer unit configured to store a new offset sub-step of the current offset step update sub-period;

a receiving unit, as an input end of the phase accumulator, configured to receive an offset sub-step increment p of a current offset step updating sub-period sent by the rate converter, and a clock signal divided by a first frequency divider;

and the transmitting unit is used as the output end of the phase accumulator and is arranged to transmit the offset sub-step of the new current offset step updating sub-period in the buffer unit to the phase interpolator every time the receiving unit receives the clock signal which is divided by the first frequency divider.

4. The jitter adjusting circuit of a phase interpolator of claim 1, wherein the phase interpolator comprises:

a receiving unit, as an input end of the phase interpolator, configured to receive a phase-locked loop clock signal and an offset sub-step of a current offset step update sub-cycle sent by the phase accumulator;

the offset unit is arranged to offset the phase-locked loop clock signal according to the offset sub-step of the current offset step updating sub-period received by the receiving unit;

an output unit, as an output end of the phase interpolator, configured to output the clock signal shifted by the shift unit.

5. The jitter adjusting circuit of a phase interpolator of claim 1, wherein the phase interpolation controller comprises:

a receiving unit, as an input terminal of the phase interpolation controller, configured to receive the clock signal divided by the second frequency divider;

a calculation unit configured to determine an offset step increment P of a current offset step update period each time the reception unit receives the clock signal frequency-divided by the second frequency divider;

and the sending unit is used as the output end of the phase interpolation controller and is arranged to send the offset step increment P of the current offset step updating period determined by the calculating unit to the rate converter every time the receiving unit receives the clock signal subjected to frequency division by the second frequency divider.

6. The jitter adjustment circuit of a phase interpolator of claim 1, wherein the second frequency divider is an n-frequency divider, n = the number of cycles of offset step update;

the first divider is an m divider, m = number of sub-periods of offset step update.

7. The phase interpolator dither adjustment circuit of claim 6, wherein n is an integer multiple of m.

8. The jitter adjustment circuit of claim 7, wherein the offset sub-step increment P for each offset step update sub-period is P m/n when P m is divisible by n.

9. The jitter adjustment circuit of claim 7, wherein the offset sub-step increment P for each offset step update sub-period is equal to P when P x m cannot be divided by n

Or

And the sum of the increment of the offset sub-step of all the offset step updating sub-periods in one offset step updating period is P.

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