CN218215314U

CN218215314U - IGBT device structure

Info

Publication number: CN218215314U
Application number: CN202222518360.3U
Authority: CN
Inventors: 姜维宾; 李圣国; 姜志浩; 金涛
Original assignee: Yantai Taixin Electronics Technology Co ltd
Current assignee: Yantai Taixin Electronics Technology Co ltd
Priority date: 2022-09-22
Filing date: 2022-09-22
Publication date: 2023-01-03
Anticipated expiration: 2032-09-22

Abstract

The utility model relates to a semiconductor device field especially relates to a IGBT device structure. The IGBT device structure comprises: n is a radical of ^‑ Base region of type P ⁺ Type collector region and basic cell, N ^‑ A basic unit is arranged above the type base region, the basic unit comprises a groove type gate region and a P type base region, the groove type gate region comprises a gate oxide layer and a polycrystalline layer, and the polycrystalline layer is positioned inside the gate oxide layer; a plurality of periodic groove type gate regions are inserted into the P type base region, and N (N is more than or equal to 3) groove type gate regions are arranged in the middleThe crystal layer is connected to the grid electrode, and the polycrystalline layers in the rest groove type grid electrode region are connected to the emitter electrode; n is a radical of hydrogen ^‑ The lower surface of the base region is provided with P ⁺ Type collector region, P ⁺ And the lower surface of the type collector region is provided with a collector. The utility model discloses N (N is greater than or equal to 3) polycrystal layer of being connected with the grid has obviously increased the grid-collecting electrode electric capacity of device, has increased the coupling effect of grid and collecting electrode promptly.

Description

IGBT device structure

Technical Field

The utility model relates to a semiconductor device field especially relates to a IGBT device structure.

Background

An existing IGBT (Insulated Gate Bipolar Transistor) usually adopts a trench Gate structure, and a carrier injection enhancement technology is mostly adopted, that is, a floating region of a device is increased, as shown in fig. 1. In the starting process of the device, the grid voltage is gradually increased, and when the threshold voltage of the device is close to the threshold voltage of the device, the device is gradually conducted. Holes accumulate in the floating region of the device, causing the potential of this region to rise gradually. The floating region is coupled with the grid electrode of the device through an oxide layer parasitic capacitor on the side wall of the groove, and then the floating region can charge the grid electrode in the opening process, so that the grid electrode voltage is increased and is not controlled by a grid electrode power supply and a resistor. Then, the device is turned on rapidly, the current rises rapidly, and the voltage across the device falls rapidly, resulting in a large rate of current change (di/dt) and voltage change (dv/dt). In addition, in the turn-off process of the IGBT device with the conventional structure, the voltage across the device will rise rapidly, resulting in a large voltage change rate. The current change rate and the voltage change rate in the switching process are coupled with parasitic inductance and capacitance of a peripheral circuit, uncontrolled voltage and current can be generated, oscillation occurs, serious electromagnetic interference (EMI) problems are generated, and the phenomenon of parasitic turn-on of an IGBT often occurs, so that the whole circuit system is unstable in work. This greatly limits the application scenarios of IGBTs, especially in systems with high power and high smoothness of the voltage and current waveforms.

In order to solve the problem that the floating region of the IGBT device cell charges the grid in the opening process in the prior art, and further causes great di/dt and dv/dt, the IGBT device cell structure is shown in FIG. 2. The structure of fig. 2 simply separates the device float region from the trench by a distance. The structure shown in FIG. 2 has no effect of reducing di/dt and dv/dt of the IGBT turn-on process. For this reason, a new IGBT device structure is urgently needed to solve the above problems.

SUMMERY OF THE UTILITY MODEL

To the technical problem, the utility model provides a IGBT device structure.

The utility model provides an above-mentioned technical problem's technical scheme as follows:

an IGBT device structure, comprising: n is a radical of hydrogen ^- Base region of type P ⁺ Type collector region and basic cell, N ^- A basic unit is arranged above the base region, the basic unit comprises a groove-type gate region and a P-type base region, the groove-type gate region comprises a gate oxide layer and a polycrystalline layer, and the polycrystalline layer is positioned inside the gate oxide layer;

a periodic groove-type gate region is inserted into the P-type base region, N (N is more than or equal to 3) groove-type gate regions are arranged in the middle of the basic unit, a polycrystalline layer in the middle groove-type gate region is connected to the gate, and polycrystalline layers in the rest groove-type gate regions are connected to the emitter;

N ^- the lower surface of the base region is provided with P ⁺ Type collector region, P ⁺ And the lower surface of the type collector region is provided with a collector.

Further, three trench-type gate regions are arranged in the middle of the basic unit.

Furthermore, a P-type heavily doped region and two N-type heavily doped regions are arranged at the upper part of a second P-type base region which is respectively arranged leftwards and rightwards by taking the central axis of the basic unit as a starting point, the P-type heavily doped region is arranged between the two N-type heavily doped regions, and the parts of the N-type heavily doped regions, which are positioned in the P-type heavily doped regions, are separated by an etching process.

Furthermore, only half of the trench type gate regions at the leftmost end and the rightmost end of the basic unit belong to the device structure.

Further, said N ^- And a middle dielectric layer is arranged on the upper layer of the base region, and the parts of the middle dielectric layer, which are positioned in the P-type heavily doped region and the N-type heavily doped region, are divided by an etching process.

Furthermore, the surface of the middle dielectric layer is covered with a metal layer, and the metal layer is in contact with the N-type heavily doped region and the P-type heavily doped region.

Further, an emitter is arranged on the upper surface of the metal layer and connected with the metal layer.

Further, P ⁺ The upper layer of the collector region is provided with N ⁺ A type field stop layer.

Compared with the prior art, the utility model discloses following technological effect has:

the utility model discloses in, constitute a basic unit by ditch groove type gate region and the P type base region that corresponds, polycrystal layer and device gate electrode in N (N is more than or equal to 3) ditch groove type gate region carry out electric connection, polycrystal layer and device projecting pole in the ditch groove type gate region carry out electric connection in addition to with this repeated arrangement; in the basic repeating unit, N (N is more than or equal to 3) polycrystalline layers connected with the gate electrode of the device increase the gate-collector capacitance of the device, namely the coupling effect of the gate electrode and the collector is increased, and the problems of poor softness, serious electromagnetic interference and easy parasitic turn-on of the traditional IGBT switching process can be effectively solved.

Drawings

Fig. 1 is a structure diagram of a first IGBT device in the prior art;

fig. 2 is a structure diagram of a second IGBT device in the prior art;

fig. 3 is a structural diagram of a semiconductor device according to the present invention.

In the drawings, the component names indicated by the respective reference numerals are listed below:

101、N ^- a base region; 102. a P-type base region; 103. a P-type heavily doped region; 104. an N-type heavily doped region; 105. a polycrystalline layer; 106. a gate oxide layer; 107. an intermediate dielectric layer; 108. a metal layer; 109. n is a radical of hydrogen ⁺ A type field stop layer; 110. p ⁺ A type collector region; G. a gate electrode; E. an emitter electrode; C. and a collector.

Detailed Description

The principles and features of the present invention are described below in conjunction with the following drawings, the examples given are only intended to illustrate the present invention and are not intended to limit the scope of the present invention.

Referring to fig. 3, an IGBT device structure includes: n is a radical of ^- Base region 101, P ⁺ Type collector region 110 and basic cell, N ^- The basic unit is arranged above the base region 101The basic unit comprises a groove-type gate region and a P-type base region 102, the groove-type gate region comprises a gate oxide layer 106 and a polycrystalline layer 105, and the polycrystalline layer 105 is positioned inside the gate oxide layer 106; a periodic groove-type gate region is inserted into the P-type base region 102, N (N is more than or equal to 3) groove-type gate regions are arranged in the middle of the P-type base region, a polycrystalline layer 105 in the middle groove-type gate region is connected to a gate G, and polycrystalline layers 105 in the rest groove-type gate regions are connected to an emitter E; n is a radical of hydrogen ^- The lower surface of the base region 101 is provided with P ⁺ Type collector region 110, P ⁺ The lower surface of the type collector region 110 is provided with a collector C.

In the utility model, a basic unit is composed of a groove type grid region and a corresponding P type base region, a polycrystal layer in N (N is more than or equal to 3) groove type grid regions is electrically connected with a device grid electrode, and the polycrystal layer in the groove type grid region is electrically connected with a device emitter and is repeatedly arranged according to the polycrystal layer; in the basic repeating unit, N (N is more than or equal to 3) polycrystalline layers connected with the gate electrode of the device increase the gate-collector capacitance of the device, namely the coupling effect of the gate electrode and the collector is increased.

In a preferred embodiment, six P-type base regions 102 are provided, periodic trench-type gate regions are inserted into the P-type base regions 102, only half of the trench-type gate regions at the leftmost end and the rightmost end of the basic unit belong to the device structure, the polycrystalline layers 105 in the middle three trench-type gate regions are connected to a gate G, and the polycrystalline layers 105 in the rest trench-type gate regions are connected to an emitter E. The 3 poly layers 105 connected to the device gate G increase the gate-collector capacitance of the device while increasing the gate-emitter capacitance of the device, i.e., the coupling of the gate G to the emitter E.

In some embodiments, a P-type heavily doped region 103 and two N-type heavily doped regions 104 are disposed on the upper portion of a second P-type base region 102 from the left to the right, respectively, with the central axis of the basic unit as the starting point, the P-type heavily doped region 103 is disposed between the two N-type heavily doped regions 104, and the portions of the N-type heavily doped regions 104 located in the P-type heavily doped regions 103 are separated by the etching process. The N-type heavily doped region 104 is located on the surface layer inside the N-type base region, and the part of the N-type heavily doped region 104 located in the P-type heavily doped region 103 is separated by the etching process, so that an extra layout is not needed in the actual manufacturing process, and the cost is saved.

The structure of the utility model is that the N-type heavily doped region 104 is formed by a general injection and junction pushing process without an extra photoetching plate, and is located the N-type heavily doped region 104 ^- The inner surface layer of the base region 101, the part of which is located in the P-type deep doped region 103, is separated by the etching process. Because the N-type heavily doped region 104 is arranged between the P-type base region 102 and the P-type deeply doped region 103, the electrical isolation between the P-type deeply doped region 103 and the P-type base region 102 is enhanced, an inversion channel connecting the P-type base region 102 and the P-type deeply doped region 103 is not easy to form, the floating potential change rate of the P-type deeply doped region 103 is reduced in the starting process, the influence on the grid G is reduced, and the stability of the grid voltage is improved.

Said N is ^- An intermediate medium layer 107 is arranged on the upper layer of the type base region 101, and the parts of the intermediate medium layer 107, which are positioned in the P-type heavily doped region 103 and the N-type heavily doped region 104, are separated by an etching process. The surface of the middle dielectric layer 107 is covered with a metal layer 108, and the metal layer 108 is in contact with the N-type heavily doped region 104 and the P-type heavily doped region 103. The upper surface of the metal layer 108 is provided with an emitter E, which is connected to the metal layer 108. P ⁺ The upper layer of the collector region 110 is provided with N ⁺ A type field stop layer 109.

The utility model discloses in apply the high level to device grid G, make the device get into the opening process, because the grid-emitter capacitance and the grid-collecting electrode capacitance of device all are greater than traditional IGBT structure, the event is under same biasing condition, the utility model discloses the grid voltage rising rate of device is slower, and then the rate that the control device channel switched on is slower to obtain lower current change rate di dt. And, because the utility model discloses the grid parasitic capacitance of device is bigger, and the effect that the floating area charges to grid polycrystal layer will obviously be less than traditional IGBT structure. And then under same float space area charging current, can know by i = c dv/dt, the utility model discloses the voltage change rate dv/dt of device opening in-process also is obviously less than traditional IGBT structure. And applying a low level to the grid electrode of the device to enable the device to enter a turn-off process. The change rule of the grid voltage, the current change rate di/dt and the voltage change rate dv/dt of the device is the same as the starting process, but the process is the reverse. From this, can use the utility model discloses the device structure through adjustment grid drive resistance, enables IGBT and obtains effective control opening the process and turn-off the voltage change rate and the current change rate of in-process. In the actual use process, the dynamic characteristics of the device can be easily adjusted by the driving end through adjusting the grid driving resistor so as to match the requirements of the application scene on the characteristics of the device, thereby preventing the problems of waveform oscillation, electromagnetic interference, parasitic switching-on and the like.

The above description is only for the preferred embodiment of the present invention, and is not intended to limit the present invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included within the protection scope of the present invention.

Claims

1. An IGBT device structure, comprising: n is a radical of ^- Base region (101), P ⁺ A collector region (110) and a basic cell, N ^- A basic unit is arranged above the base region (101), the basic unit comprises a groove-type gate region and a P-type base region (102), the groove-type gate region comprises a gate oxide layer (106) and a polycrystalline layer (105), and the polycrystalline layer (105) is positioned inside the gate oxide layer (106);

a periodic groove-type gate region is inserted into the P-type base region (102), N (N is more than or equal to 3) groove-type gate regions are arranged in the middle of the basic unit, a polycrystalline layer (105) in the middle groove-type gate region is connected to a gate (G), and polycrystalline layers (105) in the rest groove-type gate regions are connected to an emitter (E);

N ^- the lower surface of the base region (101) is provided with a P ⁺ Type collector region (110), P ⁺ The lower surface of the collector region (110) is provided with a collector (C).

2. The IGBT device structure of claim 1, wherein three trench-type gate regions are arranged in the middle of the basic unit.

3. The IGBT device structure according to claim 2, characterized in that a P-type heavily doped region (103) and two N-type heavily doped regions (104) are arranged on the upper portion of the second P-type base region (102) which is respectively towards left and right with the central axis of the basic unit as a starting point, the P-type heavily doped region (103) is arranged between the two N-type heavily doped regions (104), and the part of the N-type heavily doped region (104) located in the P-type heavily doped region (103) is separated by an etching process.

4. The IGBT device structure of claim 3, wherein only half of the trench-type gate regions at the leftmost end and the rightmost end of the basic unit belong to the device structure.

5. The IGBT device structure of claim 1, wherein N is ^- An intermediate dielectric layer (107) is arranged on the upper layer of the type base region (101), and the parts, located on the P-type heavily doped region (103) and the N-type heavily doped region (104), of the intermediate dielectric layer (107) are divided by an etching process.

6. The IGBT device structure according to claim 5, wherein the surface of the middle dielectric layer (107) is covered with a metal layer (108), and the metal layer (108) is in contact with the N-type heavily doped region (104) and the P-type heavily doped region (103).

7. An IGBT device structure according to claim 6, characterized in that the upper surface of the metal layer (108) is provided with an emitter (E), which is connected to the metal layer (108).

8. The IGBT device structure of claim 1, wherein P is P ⁺ N is arranged on the upper layer of the collector region (110) ⁺ A type field stop layer (109).