CN218213842U

CN218213842U - Key awakening circuit applied to frame circuit breaker

Info

Publication number: CN218213842U
Application number: CN202222282145.8U
Authority: CN
Inventors: 崔伟杰; 尚云辉
Original assignee: Shanghai Yimeng Electric Automatism Technology Co ltd
Current assignee: Shanghai Yimeng Electric Automatism Technology Co ltd
Priority date: 2022-08-29
Filing date: 2022-08-29
Publication date: 2023-01-03
Anticipated expiration: 2032-08-29

Abstract

The utility model relates to a be applied to button wake-up circuit of frame circuit breaker, including power module, button module and wake-up module, wherein, the button module mainly includes first triode, optical coupler and one or more button, and one of them button is used for the system of awakening up, and the module of awakening up is used for the basis break-make between button module's output level control power module output and back level circuit, if do not have the operation in a period can realize auto-power-off. Compared with the prior art, the utility model has the advantages of practice thrift the battery electric energy, do not influence original function of control button.

Description

Key wake-up circuit applied to frame circuit breaker

Technical Field

The utility model belongs to the technical field of the electronic circuit and specifically relates to a be applied to button awakening circuit of frame circuit breaker.

Background

The frame circuit breaker is also called a universal circuit breaker, all parts of the frame circuit breaker are arranged in an insulated metal frame, the frame circuit breaker is usually in an open type, various accessories can be arranged, contact and parts can be conveniently replaced, and the frame circuit breaker is used for a power end master switch. The current frame circuit breaker controller has two power supply modes, namely an external power supply (comprising external direct current 24V, USB5V and CT power supply) or battery power supply.

Under the condition that the external power supply is lost, the frame circuit breaker controller needs to immediately store data such as current operation parameters, fault information and the like. After the data is saved, the system is usually configured to enter a standby state or a power-off state for reducing the battery consumption, and if the system enters the power-off state, although the battery use time can be prolonged to the maximum extent, the parameters cannot be checked or adjusted. If the MCU needs to be configured in advance when entering the standby state, there is still less current in the standby state and the battery will drain slowly. In a standby state, the existing wake-up circuit wakes up the controller by sending a signal to an I/O port of a special MCU, at this time, parameter information of the controller can be checked or parameter configuration can be adjusted, a system operating state needs to be restored by complicated configuration after wake-up, and the controller needs to manually return to the standby state after checking or adjusting parameters.

In summary, the wake-up circuit of the existing frame circuit breaker has the following disadvantages:

(1) When the system enters a normal working mode from a standby mode, a key is required to send a signal to a specific I/O port of the MCU to wake up the controller, the MCU is required to be configured and occupy the resources of the special I/O port of the MCU, and meanwhile, the key is occupied, and other functions of the key cannot be realized;

(2) After the controller is awakened, the controller can always keep a working state, so that the battery is quickly consumed, and automatic power-off cannot be realized.

SUMMERY OF THE UTILITY MODEL

The utility model aims at overcoming the defect that above-mentioned prior art exists and providing one kind and not occupying the system of awakening up under the prerequisite of the special IO mouth of MCU, no operation is automatic power off after a period, remains the button wake-up circuit that the button acted on originally simultaneously.

The purpose of the utility model can be realized by the following technical proposal:

according to the utility model discloses an aspect provides a be applied to button wake-up circuit of frame circuit breaker, including power module, button module and the module of awakening up, wherein, awaken up the module and be used for the basis break-make between button module's output level control power module output and back stage circuit, button module includes: the key group comprises a control key and a first resistor, one end of the first resistor is connected with the output end of the power supply module, the other end of the first resistor is connected with the control key, and the other end of the control key is grounded; one end of the second resistor is connected with a common end formed by the first resistor and the control key; a base electrode of the first triode is connected with the other end of the second resistor, and an emitting electrode of the first triode is connected with the output end of the power supply module; one end of the third resistor is connected with the collector electrode of the first triode; the optical coupler comprises a diode and a photosensitive semiconductor, the anode of the diode is connected with the other end of the third resistor, the cathode of the diode is grounded, and the emitter of the photosensitive semiconductor is grounded; one end of the fourth resistor is connected with a collector electrode of a photosensitive semiconductor of the optical coupler, and the other end of the fourth resistor is connected with a system power supply which comes from a post-stage circuit; one end of the fifth resistor is connected with a common end formed by the collector of the first triode and the third resistor; one end of the sixth resistor is connected with the other end of the fifth resistor and a common end formed by the input end of the awakening module, and the other end of the sixth resistor is grounded; and one end of the capacitor is connected with a common end formed by the fifth resistor, the sixth resistor and the input end of the awakening module, and the other end of the capacitor is grounded.

As a preferred technical solution, the wake-up module includes: the input end of the OR gate is connected with a common end formed by the fifth resistor, the sixth resistor and the capacitor of the key module, the power supply input end is connected with the output end of the power supply module, and the grounding end is grounded; one end of the seventh resistor is connected with the output end of the OR gate; one end of the eighth resistor is connected with the other end of the seventh resistor, and the other end of the eighth resistor is grounded; a base electrode of the second triode is connected with a common end formed by the seventh resistor and the eighth resistor, and an emitting electrode of the second triode is grounded; the grid electrode of the MOS tube is connected with the collector electrode of the second triode, the drain electrode of the MOS tube is connected with the rear-stage circuit, and the source electrode of the MOS tube is connected with the output end of the power supply module; one end of the ninth resistor is connected with a common end formed by the grid electrode of the MOS tube and the collector electrode of the second triode, and the other end of the ninth resistor is connected with a common end formed by the source electrode of the MOS tube and the output end of the power supply module; and one end of the tenth resistor is connected with a common end formed by the drain electrode of the MOS tube and the input end of the post-stage circuit, and the other end of the tenth resistor is grounded.

As a preferred technical solution, the second triode is an NPN type triode.

As a preferred technical scheme, the MOS tube is a P-channel MOS tube.

As a preferred technical scheme, the key group further includes one or more operation key units, each operation key unit includes an operation key and a current limiting resistor connected in series with the operation key, the other end of the operation key is grounded, and the other end of the current limiting resistor is connected with a system power supply.

Preferably, the number of the operation key units is 4.

As a preferred technical solution, the power module includes a battery and a diode, wherein a positive electrode of the battery is connected with a positive electrode of the diode, and a negative electrode of the battery is grounded; and the other end of the diode is used as the output end of the power supply module.

As a preferred technical solution, the output voltage of the power supply module is in a range of 2 volts to 7 volts.

As a preferred technical solution, the first triode is a PNP type triode.

As a preferred technical solution, the optical coupler is an NPN triode output type optical coupler.

Compared with the prior art, the utility model has the advantages of it is following:

(1) The function of the original button is kept while saving the resources of the special I/O port, the utility model discloses the circuit need not to use the special I/O port of MCU to realize awakening up, simultaneously when the control button is pressed down, because the logic reverse phase effect of optical coupler, the level change can appear at the common end of fourth resistance and optical coupler, is connected with MCU, thereby MCU detectable changes and carries out corresponding action, consequently does not influence the function of original button;

(2) The battery consumption is reduced, a timing on-off function is designed in the wake-up circuit, after the control key is pressed down, the system is powered on, meanwhile, the control key is detected to be pressed down, a level signal is output to one input end of the OR gate and is kept for a period of time, the system keeps working during the period, and if no other operation is carried out during the period, the system is automatically powered off, so that the electric energy is saved.

Drawings

FIG. 1 is a schematic diagram of the connection of the modules of the present invention;

fig. 2 is a circuit diagram of the key module of the present invention;

fig. 3 is a circuit diagram of the wake-up module of the present invention;

FIG. 4 is a complete circuit diagram of the present invention;

figure 5 is a circuit diagram of embodiment 1,

the circuit comprises a K1, a control key, a BT1, a battery, a C1, a capacitor, a D1, a diode, an OR gate, an OCEP, an optical coupler, a Q1, a first triode, a Q2, a second triode, a Q3, an MOS tube, a R1, a first resistor, a R2, a second resistor, a R3, a third resistor, a R4, a fourth resistor, a R5, a fifth resistor, a R6, a sixth resistor, a R7, a seventh resistor, a R8, an eighth resistor, a R9, a ninth resistor, a R10, a tenth resistor, a 100, a power module, a 200, a key module, a 300, a wake-up module, a 400 and a voltage stabilizing module.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by a person skilled in the art without creative efforts shall fall within the protection scope of the present invention.

Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by a person skilled in the art without making creative efforts belong to the protection scope of the present invention.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

Furthermore, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Fig. 2-4 show the circuit diagram of the present invention. Fig. 4 is an overall circuit diagram, which includes a power module, a key module, and a wake-up module, where the wake-up module is configured to control on/off between an output terminal of the power module and a subsequent circuit according to an output level of the key module.

As shown in fig. 2, the key module includes: the key group comprises a control key K1 and a first resistor R1, one end of the first resistor R1 is connected with the output end of the power supply module, the other end of the first resistor R1 is connected with the control key, and the other end of the control key K1 is grounded; one end of the second resistor R2 is connected with a common end formed by the first resistor R1 and the control key K1; a base electrode of the first triode Q1 is connected with the other end of the second resistor R2, and an emitting electrode of the first triode Q1 is connected with the output end of the power supply module; one end of the third resistor R3 is connected with the collector electrode of the first triode Q1; the optical coupler OCEP comprises a diode and a photosensitive semiconductor, wherein the anode of the diode is connected with the other end of the third resistor R3, the cathode of the diode is grounded, and the emitter of the photosensitive semiconductor is grounded; one end of a fourth resistor R4 is connected with a collector of a photosensitive semiconductor of the optical coupler OCEP, the other end of the fourth resistor R4 is connected with a system power supply, and the system power supply comes from a post-stage circuit; one end of the fifth resistor R5 is connected with a common end formed by the collector of the first triode Q1 and the third resistor R3; one end of the sixth resistor R6 is connected with the common end formed by the other end of the fifth resistor R5 and the input end of the awakening module, and the other end of the sixth resistor R6 is grounded; and one end of the capacitor C1 is connected with a common end formed by the fifth resistor R5, the sixth resistor R6 and the input end of the awakening module, and the other end of the capacitor C1 is grounded.

As shown in fig. 3, the wake-up module includes: an input end of the OR gate is connected with a common end formed by a fifth resistor R5, a sixth resistor R6 and a capacitor C1 of the key module, a power supply input end is connected with an output end of the power supply module, and a grounding end is grounded; one end of the seventh resistor R7 is connected with the output end of the OR gate OR; one end of the eighth resistor R8 is connected with the other end of the seventh resistor, and the other end of the eighth resistor R8 is grounded; a base electrode of the second triode Q2 is connected with a common end formed by the seventh resistor R7 and the eighth resistor R8, and an emitting electrode of the second triode Q2 is grounded; a grid electrode of the MOS tube Q3 is connected with a collector electrode of the second triode Q2, a drain electrode of the MOS tube is connected with a rear-stage circuit, and a source electrode of the MOS tube is connected with the output end of the power supply module; one end of the ninth resistor R9 is connected with a common end formed by the grid electrode of the MOS tube Q3 and the collector electrode of the second triode Q2, and the other end of the ninth resistor R9 is connected with a common end formed by the source electrode of the MOS tube Q3 and the output end of the power supply module; and a tenth resistor R10 having one end connected to the common terminal formed by the drain of the MOS transistor Q3 and the input terminal of the post-stage circuit and the other end grounded.

Example 1

In this embodiment, the controller may adopt an MCU control module, a PLC industrial control module, and the like, which are already well-established and widely used in the prior art, or other control modules, which can realize a control function and are suitable for the utility model to control, in the prior art, may be purchased and used, which is not limited herein.

As shown in fig. 1, which is a schematic diagram of connections between modules in this embodiment, a dashed line frame is a circuit in this embodiment, in addition, a voltage stabilizing module is used as a post-stage circuit of the wake-up module, and is configured to adjust a power supply to a voltage at which a system can normally operate, an output of the voltage stabilizing module supplies power to the system, battery _ CTRL is configured to input a level signal to maintain a wake-up state, and KEY1_1 indicates a state of the control KEY K1.

Fig. 5 is a circuit diagram of the present embodiment. In the power module, a 3-volt battery is used as a power supply, a diode D1 is connected in series for rectification, and the output end is denoted as VCC _ OUT. In the KEY module, K1 is used as a control KEY and includes four other KEY units KEY2-KEY5, each KEY unit includes a switch and a 10K Ω current limiting resistor connected in series therewith. Keys K1-K5 are 5 operating keys of the controller, and K1 is used as a left direction key and a wake-up key at the same time. The first transistor Q1 employs a PNP transistor S8550, and the optocoupler OCEP employs an NPN transistor output optocoupler TLP185. In the wake-up module, an OR gate OR adopts SN74AHC1G32DBVR, an input terminal B is connected with a pin of the MCU, a second triode Q2 adopts an NPN-type triode S8050, an MOS transistor Q3 adopts a P-channel MOS transistor, a VCC _ USB terminal is connected to an input terminal of the voltage stabilizing module, an output of the voltage stabilizing module supplies power to the system, and is denoted as VCC in the figure.

When the external power supply is powered off, if the K1 key is pressed down, the base electrode of the Q1 is grounded and the Q1 is conducted. VCC _ OUT is grounded through Q1, R5 and R6, the A pin of an OR gate is input at high level, and the Y pin of the OR gate is output at high level. Q2 turns on causing the PMOS gate ground GS voltage to be negative and PMSO turns on. VCC _ USB and VCC _ OUT are on. VCC _ USB is converted to VCC (5V) by the boost circuit, at which time the system powers up. The system detects the KEY1_1 KEY press signal due to the level shifting and logic inversion action of the optocoupler TLP185. The master control chip immediately outputs a high level signal to the Battery _ CTRL and keeps the high level signal for 30s, the Y pin of the OR gate outputs high level for correspondingly delaying 30s because the signal is connected with the input pin of the OR gate, and the PMOS on-time is correspondingly prolonged for 30s. And then the Battery _ CTRL high level is output for a time delay of 30s each time any key press is detected. If no key operation 30S is carried out, the PMOS disconnects the system and powers down.

Since the system can know the state of the control KEY K1 through the level state of KEY1_1, when the controller adopts external power supply, K1 is a normal left KEY in the direction. When the controller uses the battery to supply power, the pressing of the K1 can activate the battery to supply power, and the controller is electrified and restarted. The controller can work all the time as long as a key is operated, and system information is convenient to check. The controller automatically powers off 30s after no operation. In the embodiment, a special I/O port of the MCU is not occupied, and I/O port resources are saved.

Example 2

Compared with embodiment 1, the power module of the present embodiment adopts USB power supply. The use of USB power does not require frequent battery replacement.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope of the present invention, and these modifications or replacements should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. The utility model provides a be applied to button awakening circuit of frame circuit breaker which characterized in that, includes power module, button module and awakens up the module, wherein awakens up the module and is used for the basis break-make between button module's output level control power module output and back stage circuit, the button module includes:

the key group comprises a control key K1 and a first resistor R1, one end of the first resistor R1 is connected with the output end of the power supply module, the other end of the first resistor R1 is connected with the control key, and the other end of the control key K1 is grounded;

one end of the second resistor R2 is connected with a common end formed by the first resistor R1 and the control key K1;

a base electrode of the first triode Q1 is connected with the other end of the second resistor R2, and an emitting electrode of the first triode Q1 is connected with the output end of the power supply module;

one end of the third resistor R3 is connected with the collector electrode of the first triode Q1;

the optical coupler OCEP comprises a diode and a photosensitive semiconductor, wherein the anode of the diode is connected with the other end of the third resistor R3, the cathode of the diode is grounded, and the emitter of the photosensitive semiconductor is grounded;

one end of the fourth resistor R4 is connected with the collector of the photosensitive semiconductor of the optical coupler OCEP, and the other end of the fourth resistor R4 is connected with a system power supply which comes from a post-stage circuit;

one end of the fifth resistor R5 is connected with a common end formed by the collector of the first triode Q1 and the third resistor R3;

one end of the sixth resistor R6 is connected with the common end formed by the other end of the fifth resistor R5 and the input end of the awakening module, and the other end of the sixth resistor R6 is grounded;

and one end of the capacitor C1 is connected with a common end formed by the fifth resistor R5, the sixth resistor R6 and the input end of the awakening module, and the other end of the capacitor C1 is grounded.

2. The key wake-up circuit applied to a frame circuit breaker according to claim 1, wherein the wake-up module comprises:

an input end of the OR gate OR is connected with a common end formed by the fifth resistor R5, the sixth resistor R6 and the capacitor C1 of the key module, a power supply input end is connected with an output end of the power supply module, and a grounding end is grounded;

a seventh resistor R7 having one end connected to the output end of the OR gate OR;

one end of the eighth resistor R8 is connected with the other end of the seventh resistor, and the other end of the eighth resistor R8 is grounded;

a base electrode of the second triode Q2 is connected with a common end formed by the seventh resistor R7 and the eighth resistor R8, and an emitting electrode of the second triode Q2 is grounded;

a grid electrode of the MOS tube Q3 is connected with a collector electrode of the second triode Q2, a drain electrode of the MOS tube Q3 is connected with a rear-stage circuit, and a source electrode of the MOS tube Q3 is connected with an output end of the power supply module;

a ninth resistor R9, one end of which is connected to a common terminal formed by the gate of the MOS transistor Q3 and the collector of the second transistor Q2, and the other end of which is connected to a common terminal formed by the source of the MOS transistor Q3 and the output terminal of the power supply module;

and one end of the tenth resistor R10 is connected with a common end formed by the drain electrode of the MOS tube Q3 and the input end of the post-stage circuit, and the other end of the tenth resistor R is grounded.

3. The key wake-up circuit applied to the frame circuit breaker as claimed in claim 2, wherein the second transistor Q2 is an NPN transistor.

4. The key wake-up circuit applied to the frame circuit breaker according to claim 2, wherein the MOS transistor Q3 is a P-channel MOS transistor.

5. The key wake-up circuit applied to the frame circuit breaker as claimed in claim 1, wherein the key set further comprises one or more operation key units, each operation key unit comprises an operation key and a current-limiting resistor connected in series with the operation key, the other end of the operation key is grounded, and the other end of the current-limiting resistor is connected to a system power supply.

6. A key wake-up circuit for frame circuit breaker according to claim 5, characterized in that the number of said operation key units is 4.

7. The key wake-up circuit applied to the frame circuit breaker according to claim 1, wherein the power module comprises a battery BT1 and a diode D1, the positive electrode of the battery BT1 is connected to the positive electrode of the diode D1, and the negative electrode is grounded; and the other end of the diode D1 is used as the output end of the power supply module.

8. The key wake-up circuit applied to a frame circuit breaker according to claim 1, wherein the output voltage of the power supply module is in a range of 2 v to 7 v.

9. The key wake-up circuit applied to the frame circuit breaker of claim 1, wherein the first transistor Q1 is a PNP transistor.

10. The key wake-up circuit applied to the frame circuit breaker according to claim 1, wherein the optical coupler OCEP is an NPN transistor output type optical coupler.