CN218160366U - Integrated circuit chip packaging structure - Google Patents
Integrated circuit chip packaging structure Download PDFInfo
- Publication number
- CN218160366U CN218160366U CN202222504241.2U CN202222504241U CN218160366U CN 218160366 U CN218160366 U CN 218160366U CN 202222504241 U CN202222504241 U CN 202222504241U CN 218160366 U CN218160366 U CN 218160366U
- Authority
- CN
- China
- Prior art keywords
- lead frame
- integrated circuit
- circuit chip
- area
- packaging structure
- Prior art date
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- 238000004806 packaging method and process Methods 0.000 title abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 239000002184 metal Substances 0.000 claims abstract description 30
- 229910000679 solder Inorganic materials 0.000 claims abstract description 21
- 238000009713 electroplating Methods 0.000 claims abstract description 16
- 239000000463 material Substances 0.000 claims abstract description 9
- 238000007788 roughening Methods 0.000 claims abstract description 4
- 238000007747 plating Methods 0.000 claims description 18
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 abstract description 2
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 abstract description 2
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000005022 packaging material Substances 0.000 description 3
- 238000006087 Brown hydroboration reaction Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005034 decoration Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model discloses an integrated circuit chip packaging structure, including lead frame, metal convex block and chip. The lead frame is provided with a roughened surface, and the chip is inversely arranged on the roughened surface of the lead frame through the metal lug. The surface of the pad on the coarsened surface of the lead frame is provided with an electroplating part, the solder part of the metal bump is connected with the electroplating part, and the upper surface area of the electroplating part is larger than the cross section area of the solder part. The integrated circuit chip packaging structure provided by the embodiment enhances the combination degree of the lead frame and the plastic package material by roughening the surface, and achieves the purpose of no rosin joint or empty solder joint between the metal lug and the lead frame by the electroplating part on the surface of the lead frame bonding pad, thereby improving the reliability of the integrated circuit chip packaging structure.
Description
Technical Field
The utility model belongs to the technical field of the semiconductor package technique and specifically relates to an integrated circuit chip packaging structure is related to.
Background
The integrated circuit chip packaging structure comprises a lead frame, a chip inversely arranged on the lead frame, and a metal Bump (Bump) for realizing the electrical connection between the chip and the lead frame. The lead frame is used as a chip carrier of an integrated circuit in the packaging process, the electrical connection between the leading-out end of an internal circuit of the chip and an external lead is realized by means of bonding materials such as gold wires, aluminum wires or copper wires, and the lead frame plays a role of a bridge connected with an external lead.
In recent years, with the continuous development of miniaturization and integration of packaging technology, flip chip process products are more popular, and the reliability requirement of the semiconductor packaging industry on the integrated circuit chip packaging structure is higher and higher, so that a new integrated circuit chip packaging structure is urgently needed to meet the higher and higher reliability requirement of the integrated circuit chip packaging structure.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to overcome the defect that exists among the prior art, provide a new integrated circuit chip packaging structure, improve its reliability to solve and have rosin joint, empty problem of welding between metal convex block and the lead frame.
In order to solve the technical problem, the utility model provides an integrated circuit chip packaging structure, including lead frame, metal convex block and chip. The lead frame is equipped with the alligatoring surface, and the chip passes through the metal bump flip-chip at the alligatoring surface of lead frame. The surface of the pad on the coarsened surface of the lead frame is provided with an electroplating part, the solder part of the metal bump is connected with the electroplating part, and the upper surface area of the electroplating part is larger than the cross section area of the solder part.
In some embodiments, the upper surface area of the plated portion is 1-2 times the area of the cross-section of the solder portion.
In some embodiments, the height of the plated portion is greater than the average height of the roughened surface.
In some embodiments, the height of the plating is 1.7-8um.
In some embodiments, the material of the plated portion is Ag.
In some embodiments, the area of the roughened surface of the lead frame is 1.2 to 3 times the area before roughening. The area ratio enables the bonding force between the roughened surface of the lead frame and the plastic package material to be suitable for being applied to packaging of integrated circuit chips.
The utility model provides an integrated circuit chip packaging structure compares with prior art, has following beneficial effect:
1. the roughened surface is arranged on the lead frame, so that the bonding force between the lead frame and the plastic package material is increased, and the problem that the lead frame and the plastic package material are layered in the subsequent application process of the integrated circuit chip packaging structure is solved;
2. the electroplating part is arranged on the surface of the pad on the coarsening surface of the lead frame, the cross section area of the upper surface area of the electroplating part and the cross section area of the welding part of the metal lug are ingeniously utilized, so that the electrical connection between the metal lug and the lead frame is realized, the problems of insufficient solder and empty solder between the metal lug and the lead frame are solved, and the reliability of the integrated circuit chip packaging structure is improved.
Drawings
FIG. 1 is a schematic diagram of a package structure of an inter-integrated circuit chip according to the present invention;
FIG. 2 is a schematic structural view of the upper surface of the plated portion and the cross section of the solder portion.
Detailed Description
The following description will further describe embodiments of the present invention with reference to the accompanying drawings and examples. The following examples are only used to illustrate the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
As shown in fig. 1, the present invention provides an integrated circuit chip package structure, which includes a lead frame 1, a metal bump 2 and a chip 3.
The lead frame 1 is provided with a roughened surface 10, and the chip 3 is inversely installed on the roughened surface 10 of the lead frame 1 through the metal bump 2. The upper surface of the lead frame 1 may be roughened by ME2 process and brown oxidation process. The principle of the ME2 process is to immerse the lead frame 1 in a chemical solution and perform galvanic corrosion, so that a plurality of regular circular pits with the same diameter are formed on the surface of the lead frame 1, thereby increasing the roughness of the surface of the lead frame 1. In the brown oxidation process, after electroplating is finished, a layer of spongy organic metal conversion film is deposited on the surface of the lead frame 1 by using a strong oxidant, and the bonding force between the conversion film and a plastic packaging material (plastic packaging resin) is greater than that between copper and the packaging material, so that the lead frame 1 and the packaging material are not easy to delaminate. Other techniques for forming the roughened surface 10 of the lead frame 1 can be used in the present invention.
The area of the roughened surface 10 of the lead frame 1 is 1.2 to 3 times the area before roughening. The area ratio makes the bonding force between the roughened surface 10 of the lead frame 1 and the molding compound suitable for being applied to the packaging of integrated circuit chips.
When the lead frame 1 provided with the roughened surface 10 is applied to an integrated circuit chip package structure, a new problem occurs: such as the bonding problem between the metal bumps 2 (Bump) and the roughened surface 10 of the lead frame 1. The metal (tin, copper, etc.) at the front end of the metal bump 2 cannot be effectively diffused on the roughened surface of the lead frame, so that the metal bump 2 and the lead frame 1 are weaker in combination, and the risk of insufficient soldering and empty soldering is high. This can affect the reliability of the integrated circuit chip package structure.
In order to solve the above problem, in the present embodiment, the plating part 11 is provided on the pad surface of the roughened surface 10 of the lead frame 1, and the solder part 20 of the metal bump 2 is connected to the plating part 11. The plating portion 11 may be formed by a conventional plating process to form a plating layer on the surface of the pad.
In practice, the top surface 1101 of the plating portion 11 is larger than the cross-sectional area 2001 of the solder portion 20, as shown in fig. 2. The plating part 11 is provided to enhance the bonding with the solder part 20 of the metal bump 2, so that the plating part 11 has a large enough area to provide a sufficient space for spreading the solder part 20 of the metal bump 2. If the area of the plated portion 11 is too small, the solder portion 20 of the metal bump 2 does not have enough space to spread, which may affect the solder-fixing of the metal bump 2 and the lead frame 1. Therefore, in order to stably and reliably connect the plating part 11 and the metal bump 2, the upper surface area of the plating part 11 in the present embodiment is set to be 1 to 2 times the area 2001 of the cross section of the solder part 20.
In the present embodiment, the height of the plating section 11 may be set to be larger than the average height of the roughened surface 10. Since the distance between the chip 3 and the lead frame 1 is constant, the height of the plating part 11 is set higher than the roughened surface 10, on one hand, the contact area between the solder part 20 of the metal bump 2 and the plating part 11 is larger; on the other hand, the solder part 20 can extend and spread all around, and the connection between the solder part 20 and the plating part 11 is more stable and reliable. In specific implementation, the height of the electroplating part 11 is set between 1.7 um and 8um. The material of the electroplating part adopts Ag.
The integrated circuit chip packaging structure provided by the embodiment enhances the combination degree of the lead frame 1 and the plastic package material through the roughened surface 10, and achieves the purpose of no cold joint or empty joint between the metal bump 2 and the lead frame 1 through the electroplating part 11 on the surface of the bonding pad of the lead frame 1, thereby improving the reliability of the integrated circuit chip packaging structure.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the technical principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.
Claims (6)
1. Integrated circuit chip package structure, its characterized in that includes lead frame, metal lug and chip, the lead frame is equipped with the alligatoring surface, the chip passes through the alligatoring surface of metal lug flip-chip at the lead frame, the pad surface on lead frame alligatoring surface sets up electroplating portion, metal lug's solder portion connects electroplating portion, electroplating portion's upper surface area is greater than the area of solder portion cross section.
2. The integrated circuit chip package structure of claim 1, wherein an upper surface area of the plating portion is 1-2 times an area of a cross section of the solder portion.
3. The integrated circuit chip package structure of claim 2, wherein the height of the plated portion is greater than the average height of the roughened surface.
4. The integrated circuit chip package structure of claim 3, wherein the height of the plating portion is 1.7-8um.
5. The package structure of claim 4, wherein the material of the plating is Ag.
6. The integrated circuit chip package structure of claim 1, wherein the area of the roughened surface of the lead frame is 1.2 to 3 times the area before roughening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222504241.2U CN218160366U (en) | 2022-09-21 | 2022-09-21 | Integrated circuit chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222504241.2U CN218160366U (en) | 2022-09-21 | 2022-09-21 | Integrated circuit chip packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218160366U true CN218160366U (en) | 2022-12-27 |
Family
ID=84561944
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222504241.2U Active CN218160366U (en) | 2022-09-21 | 2022-09-21 | Integrated circuit chip packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN218160366U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116885501A (en) * | 2023-09-05 | 2023-10-13 | 深圳市方向电子股份有限公司 | Connector terminal and PCB (printed circuit board) patch structure |
-
2022
- 2022-09-21 CN CN202222504241.2U patent/CN218160366U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116885501A (en) * | 2023-09-05 | 2023-10-13 | 深圳市方向电子股份有限公司 | Connector terminal and PCB (printed circuit board) patch structure |
| CN116885501B (en) * | 2023-09-05 | 2023-11-28 | 深圳市方向电子股份有限公司 | Connector terminal and PCB (printed circuit board) patch structure |
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| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 210000 No. 8, Linchun Road, Pukou Economic Development Zone, Pukou District, Nanjing, Jiangsu Province Patentee after: Jiangsu Xinde Semiconductor Technology Co.,Ltd. Country or region after: China Address before: 210000 No. 8, Linchun Road, Pukou Economic Development Zone, Pukou District, Nanjing, Jiangsu Province Patentee before: Jiangsu Xinde Semiconductor Technology Co.,Ltd. Country or region before: China |