CN218158772U

CN218158772U - Multilayer elevator control system

Info

Publication number: CN218158772U
Application number: CN202221454937.2U
Authority: CN
Inventors: 杰瑞.科斯基宁
Original assignee: Guangzhou Quanyu Technology Co ltd
Current assignee: Guangzhou Quanyu Technology Co ltd
Priority date: 2022-06-09
Filing date: 2022-06-09
Publication date: 2022-12-27
Anticipated expiration: 2032-06-09

Abstract

The utility model discloses a multilayer elevator control system, which is characterized in that a CPU connector, an elevator external calling circuit, an arrival indicating circuit, an elevator internal calling circuit, a target floor indicating circuit, an elevator position indicating circuit, a calling driving circuit, a first indicating driving circuit and a second indicating driving circuit are arranged in the elevator; the CPU connector is respectively connected with a calling drive circuit, a first indication drive circuit and a second indication drive circuit, the calling drive circuit is respectively connected with an elevator external calling circuit and an elevator internal calling circuit, the first indication drive circuit is respectively connected with an arrival indication circuit and a target floor indication circuit, and the second indication drive circuit is connected with an elevator position indication circuit. The utility model discloses a set up the CPU connector and connect CPU and each drive circuit respectively to can extend CPU's interface, reduce elevator system's cable wiring's complexity and wiring cost, improve the security and the maintainability of system.

Description

Multilayer elevator control system

Technical Field

The utility model belongs to the technical field of elevator control, concretely relates to multilayer elevator control system.

Background

With the increasing of floor buildings, the elevator becomes indispensable mobility devices in the high-rise buildings, and users call the elevator through the elevator outbound device.

In present elevator trade, elevator control system adopts mainboard and the point-to-point parallel communication of external device more, and every signal that the elevator gathered all needs to realize electrical connection through cable and peripheral part, and whole electrical system cable is numerous, very easily make mistakes, the equipment production of being not convenient for, engineering installation and later maintenance. Moreover, since the main board is usually far from the peripheral devices, the whole system requires a large number of cables, which makes the overall cost of the elevator high.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a multilayer elevator control system for solve the elevator control system cable that exists among the prior art numerous, the higher problem of cost.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

the utility model provides a multilayer elevator control system, include: the elevator control system comprises a CPU connector, an elevator calling circuit, a arrival indicating circuit, an elevator calling circuit, a target floor indicating circuit, an elevator position indicating circuit, a call driving circuit, a first indication driving circuit and a second indication driving circuit;

the CPU connector is respectively connected with the call driving circuit, the first indication driving circuit and the second indication driving circuit, the call driving circuit is respectively connected with the elevator call-out circuit and the elevator call-in circuit, the first indication driving circuit is respectively connected with the arrival indication circuit and the target floor indication circuit, and the second indication driving circuit is connected with the elevator position indication circuit.

In one possible design, the CPU connector is a single chip microcomputer with the model number STM32L052K8T 6.

In one possible design, the call driving circuit comprises a multiplexer IC3 with the model number 74HC4051-SO16, a pin A0 of the multiplexer IC3 is connected with a pin PA0 of the single chip microcomputer, a pin A1 of the multiplexer IC3 is connected with a pin PA1 of the single chip microcomputer, and a pin A2 of the multiplexer IC3 is connected with a pin PA2 of the single chip microcomputer; a GB pin of the multiplexer IC3 is grounded, and a BUT _ READ pin of the multiplexer IC3 is connected with a PA5 pin of the singlechip; the GB pin of the multiplexer IC3 is grounded; and the 0-3 parallel output pins of the multiplexer IC3 are respectively connected with the elevator internal calling circuit, and the 4-7 parallel output pins of the multiplexer IC3 are respectively connected with the elevator external calling circuit.

In a possible design, the first indication driving circuit includes a displacement buffer IC4 with a model number of 74HC595, an EN3 pin of the displacement buffer IC4 is grounded, a C2 pin of the displacement buffer IC4 is connected with a PA10 pin of the single chip microcomputer, an R pin of the displacement buffer IC4 is connected with a PA9 pin of the single chip microcomputer, a C1 pin of the displacement buffer IC4 is connected with a PA8 pin of the single chip microcomputer, a 1D pin of the displacement buffer IC4 is connected with a PA15 pin of the single chip microcomputer, 4 parallel output pins of the displacement buffer IC4 are respectively connected with the arrival indicating circuit, and the other 4 parallel output pins of the displacement buffer IC4 are respectively connected with the destination floor indicating circuit.

In one possible design, the second indication driving circuit comprises a counter IC1 with a model 74HC193 and a demultiplexer IC2 with a model 74HC138, a C3 pin of the counter IC1 is connected to a voltage VCC, A2 + pin and a G1 pin of the counter IC1 are connected to a PA6 pin of a single chip microcomputer, A1-pin and a G2 pin of the counter IC1 are connected to a PA7 pin of the single chip microcomputer, an R pin of the counter IC1 is connected to a PA4 pin of the single chip microcomputer, a 3D pin of the counter IC1 is grounded, A0, A1 and A2 pins of the counter IC1 are connected to A0, A1 and A2 pins of the demultiplexer IC2, respectively, and 1-6 parallel output pins of the demultiplexer IC2 are connected to the elevator position indication circuit, respectively.

In one possible design, the elevator hall call circuit includes a plurality of first key switches S5, S6, S7, and S8, each of which is connected to one of the 0-3 parallel output pins of the multiplexer IC 3.

In one possible design, the elevator hall call circuit includes a plurality of second key switches S1, S2, S3 and S4, each of which is connected to one of the 4-7 parallel output pins of the multiplexer IC 3.

In one possible design, the arrival indication circuit includes multiple first LED circuits, each first LED circuit includes a first resistor and a first light emitting diode, one end of the first resistor is connected to 1 of the parallel output pins of the shift buffer IC4, the other end of the first resistor is connected to the forward end of the first light emitting diode, and the reverse end of the first light emitting diode is grounded.

In one possible design, the destination floor indication circuit includes multiple second LED circuits, each second LED circuit includes a second resistor and a second light emitting diode, one end of the second resistor is connected to one of the 1 parallel output pins of the shift register IC4, the other end of the second resistor is connected to the forward end of the second light emitting diode, and the reverse end of the second light emitting diode is grounded.

In one possible design, the elevator position indicating circuit comprises multiple third LED circuits, each third LED circuit comprises a third resistor and a third light emitting diode, one end of the third resistor is connected with 1 of the parallel output pins of the demultiplexer IC2, the other end of the third resistor is connected with the reverse end of the second light emitting diode, and the forward end of the third light emitting diode is grounded.

Has the advantages that:

the utility model provides a multilayer elevator control system, through with the CPU connector respectively with call drive circuit, first instruction drive circuit and second instruction drive circuit connection, will call drive circuit respectively with the elevator call circuit and call circuit connection in circuit and the elevator outward, with first instruction drive circuit respectively with arrive instruction circuit and target floor instruction circuit connection, with second instruction drive circuit and elevator position instruction circuit connection. The utility model discloses a set up the CPU connector and connect CPU and each drive circuit respectively to can extend CPU's interface, reduce elevator system's cable wiring's complexity and wiring cost, improve the security and the maintainability of system.

Drawings

Fig. 1 is a block diagram of a circuit configuration of a multi-deck elevator control system in the present embodiment;

FIG. 2 is a schematic circuit diagram of the CPU connector in the present embodiment;

fig. 3 is a schematic circuit diagram of a call driving circuit in the present embodiment;

fig. 4 is a circuit schematic diagram of a first indication driving circuit in the present embodiment;

FIG. 5 is a schematic circuit diagram of a second indicator driving circuit in the present embodiment;

fig. 6 is a schematic circuit diagram of an elevator hall call circuit in the present embodiment;

fig. 7 is a schematic circuit diagram of an elevator hall call circuit in the present embodiment;

fig. 8 is a circuit schematic diagram of the arrival indication circuit in the present embodiment;

fig. 9 is a circuit schematic diagram of a destination floor indication circuit in the present embodiment;

fig. 10 is a schematic circuit diagram of an elevator position indicating circuit in the present embodiment;

fig. 11 is a schematic circuit diagram of the filter circuit in this embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, but not all embodiments of the present disclosure. All other embodiments obtained by a person skilled in the art based on the embodiments in the present specification without any creative effort belong to the protection scope of the present invention.

Examples

As shown in fig. 1-11, the present invention provides a multi-deck elevator control system comprising: the elevator control system comprises a CPU connector, an elevator calling circuit, a arrival indicating circuit, an elevator calling circuit, a target floor indicating circuit, an elevator position indicating circuit, a call driving circuit, a first indication driving circuit and a second indication driving circuit;

The CPU connector is used for connecting the CPU controller and each rear-stage driving circuit, receiving a control instruction of the CPU controller, and transmitting the control instruction to each rear-stage driving circuit to drive the corresponding circuit to work; the call driving circuit is used for receiving a control instruction of the CPU controller and respectively driving the elevator outbound circuit and the elevator inbound circuit to work; the elevator outbound circuit is used for receiving an instruction input by a user from the outside of the elevator, transmitting the instruction to the CPU controller, informing the user of the floor where the user is located and driving the elevator to reach the corresponding floor to receive the user; the elevator calling circuit is used for receiving a target floor instruction input by a user in the car, transmitting the target floor instruction to the CPU for control, and driving the elevator to reach the target floor; the first indication driving circuit is used for receiving a CPU controller instruction and respectively driving an arrival indication circuit and a target floor indication circuit to work, the arrival indication circuit is used for displaying an elevator arrival signal outside an elevator when the elevator arrives at a certain floor, and the target floor indication circuit is used for displaying a key corresponding to a target floor input by a user in a car; the elevator arrival position indicating circuit is used for displaying the current elevator arrival floor position in the elevator car.

Wherein, this embodiment is preferably applicable to 4 floor elevators, including minus one floor, two floors and three floors. Specific circuit structures will be explained below one by one, and are not described in detail here.

Based on the above disclosure, in this embodiment, by using the multi-layer elevator control system, the CPU connector is connected to the call driving circuit, the first indication driving circuit, and the second indication driving circuit, the call driving circuit is connected to the elevator call circuit and the elevator call circuit, the first indication driving circuit is connected to the arrival indication circuit and the destination floor indication circuit, and the second indication driving circuit is connected to the elevator position indication circuit. The utility model discloses a set up the CPU connector and connect CPU and each drive circuit respectively to can extend CPU's interface, reduce elevator system's cable wiring's complexity and wiring cost, improve the security and the maintainability of system.

As shown in fig. 2, in a specific embodiment, the CPU connector is an STM32L052K8T6 single chip microcomputer, which is an embedded single chip microcomputer specially designed to require high performance, low cost and low power consumption in an STM32 series single chip microcomputer, so that the power consumption and cost of the whole elevator control system can be reduced while the elevator control performance is ensured.

As shown in fig. 3, in a specific embodiment, the call driving circuit includes a multiplexer IC3 with a model number of 74HC4051-SO16, a pin A0 of the multiplexer IC3 is connected to a pin PA0 of the single chip microcomputer, a pin A1 of the multiplexer IC3 is connected to a pin PA1 of the single chip microcomputer, and a pin A2 of the multiplexer IC3 is connected to a pin PA2 of the single chip microcomputer; a GB pin of the multiplexer IC3 is grounded, and a BUT _ READ pin of the multiplexer IC3 is connected with a PA5 pin of the singlechip; the GB pin of the multiplexer IC3 is grounded; and the 0-3 parallel output pins of the multiplexer IC3 are respectively connected with the elevator internal calling circuit, and the 4-7 parallel output pins of the multiplexer IC3 are respectively connected with the elevator external calling circuit.

As shown in fig. 4, in a specific embodiment, the first indication driving circuit includes a displacement buffer IC4 of a model 74HC595, an EN3 pin of the displacement buffer IC4 is grounded, a C2 pin of the displacement buffer IC4 is connected to a PA10 pin of the single chip microcomputer, an R pin of the displacement buffer IC4 is connected to a PA9 pin of the single chip microcomputer, a C1 pin of the displacement buffer IC4 is connected to a PA8 pin of the single chip microcomputer, a 1D pin of the displacement buffer IC4 is connected to a PA15 pin of the single chip microcomputer, 4 parallel output pins of the displacement buffer IC4 are respectively connected to the arrival indication circuit, and the other 4 parallel output pins of the displacement buffer IC4 are respectively connected to the destination floor indication circuit.

As shown in fig. 5, in a specific embodiment, the second indication driving circuit includes a counter IC1 with a model 74HC193 and a demultiplexer IC2 with a model 74HC138, a pin C3 of the counter IC1 is connected to a voltage VCC, a pin 2+ and a pin G1 of the counter IC1 are connected to a pin PA6 of the single chip microcomputer, a pin 1-and a pin G2 of the counter IC1 are connected to a pin PA7 of the single chip microcomputer, a pin R of the counter IC1 is connected to a pin PA4 of the single chip microcomputer, a pin 3D of the counter IC1 is grounded, pins A0, A1, and A2 of the counter IC1 are connected to pins A0, A1, and A2 of the demultiplexer IC2, and pins 1-6 parallel outputs of the demultiplexer IC2 are connected to the elevator position indicating circuit.

In a specific embodiment, as shown in fig. 6, the hall call circuit includes a plurality of first key switches S5, S6, S7 and S8, each of which is connected to one of the parallel 0-3 output pins of the multiplexer IC 3.

In a specific embodiment, as shown in fig. 7, the elevator hall call circuit includes a plurality of second key switches S1, S2, S3 and S4, each of which is connected to one of the parallel output pins 4-7 of the multiplexer IC 3.

In a specific embodiment, as shown in fig. 8, the arrival indication circuit includes multiple first LED circuits, each first LED circuit includes a first resistor and a first light emitting diode, one end of the first resistor is connected to one of the 1 parallel output pins of the shift buffer IC4, the other end of the first resistor is connected to the forward end of the first light emitting diode, and the reverse end of the first light emitting diode is grounded.

In a specific embodiment, as shown in fig. 9, the destination floor indicating circuit includes multiple second LED circuits, each second LED circuit includes a second resistor and a second light emitting diode, one end of the second resistor is connected to one of the 1 parallel output pins of the shift buffer IC4, the other end of the second resistor is connected to the forward end of the second light emitting diode, and the reverse end of the second light emitting diode is grounded.

In a specific embodiment, as shown in fig. 10, the elevator position indicating circuit includes multiple third LED circuits, each of which includes a third resistor and a third LED, one end of the third resistor is connected to one of the 1 parallel output pins of the demultiplexer IC2, the other end of the third resistor is connected to the reverse end of the second LED, and the forward end of the third LED is grounded.

In a specific embodiment, as shown in fig. 11, the control system further includes a filtering circuit, and the filtering circuit is disposed on one side of the chips IC1-IC4 for filtering the chips. Specifically, the filter circuit includes a plurality of shunt capacitors connected in parallel, one end of each shunt capacitor is connected to a voltage VCC, and the other end is grounded.

Based on the disclosure, the control system of the four-layer elevator is designed, and the CPU connector is arranged to be respectively connected with the CPU controller and each rear-stage drive circuit, so that the laying of cables can be effectively reduced, the wiring cost is reduced, and the line safety is improved.

Finally, it should be noted that: the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A multi-level elevator control system, comprising: the elevator calling system comprises a CPU connector, an elevator calling circuit, a arrival indicating circuit, an elevator calling circuit, a target floor indicating circuit, an elevator position indicating circuit, a calling driving circuit, a first indicating driving circuit and a second indicating driving circuit;

2. The multi-deck elevator control system of claim 1 wherein the CPU connector is a single chip microcomputer model STM32L052K8T 6.

3. The multi-deck elevator control system according to claim 2, wherein the call driving circuit comprises a multiplexer IC3 of type 74HC4051-SO16, a pin A0 of the multiplexer IC3 is connected to a pin PA0 of the single chip microcomputer, a pin A1 of the multiplexer IC3 is connected to a pin PA1 of the single chip microcomputer, and a pin A2 of the multiplexer IC3 is connected to a pin PA2 of the single chip microcomputer; a GB pin of the multiplexer IC3 is grounded, and a BUT _ READ pin of the multiplexer IC3 is connected with a PA5 pin of the singlechip; and the 0-3 parallel output pins of the multiplexer IC3 are respectively connected with the elevator internal calling circuit, and the 4-7 parallel output pins of the multiplexer IC3 are respectively connected with the elevator external calling circuit.

4. The multi-layer elevator control system according to claim 2, wherein the first indication driving circuit includes a displacement buffer IC4 of a model 74HC595, an EN3 pin of the displacement buffer IC4 is grounded, a C2 pin of the displacement buffer IC4 is connected with a PA10 pin of the single chip microcomputer, an R pin of the displacement buffer IC4 is connected with a PA9 pin of the single chip microcomputer, a C1 pin of the displacement buffer IC4 is connected with a PA8 pin of the single chip microcomputer, a 1D pin of the displacement buffer IC4 is connected with a PA15 pin of the single chip microcomputer, 4 parallel output pins of the displacement buffer IC4 are respectively connected with the arrival indication circuit, and the other 4 parallel output pins of the displacement buffer IC4 are respectively connected with the target floor indication circuit.

5. The multi-layer elevator control system according to claim 4, wherein the second indication driving circuit comprises a counter IC1 with the model number 74HC193 and a demultiplexer IC2 with the model number 74HC138, the C3 pin of the counter IC1 is connected to the voltage VCC, the 2+ pin and the G1 pin of the counter IC1 are connected to the PA6 pin of the single chip microcomputer, the 1-pin and the G2 pin of the counter IC1 are connected to the PA7 pin of the single chip microcomputer, the R pin of the counter IC1 is connected to the PA4 pin of the single chip microcomputer, the 3D pin of the counter IC1 is grounded, the A0, A1 and A2 pins of the counter IC1 are respectively connected to the A0, A1 and A2 pins of the demultiplexer IC2, and the 1-6 parallel output pins of the demultiplexer IC2 are respectively connected to the elevator position indication circuit.

6. The multi-deck elevator control system according to claim 3, wherein the elevator hall call circuit comprises a plurality of first key switches S5, S6, S7 and S8, each of which is connected to one of the 0-3 parallel output pins of the multiplexer IC 3.

7. The multi-deck elevator control system according to claim 3, wherein the elevator hall call circuit comprises a plurality of second key switches S1, S2, S3 and S4, each second key switch connected to one of the 4-7 parallel output pins of the multiplexer IC 3.

8. The multi-deck elevator control system according to claim 4, wherein the arrival indication circuit comprises a plurality of first LED circuits, each first LED circuit comprises a first resistor and a first LED, one end of the first resistor is connected to one of the 1 parallel output pins of the displacement buffer IC4, the other end of the first resistor is connected to the forward terminal of the first LED, and the reverse terminal of the first LED is grounded.

9. The multi-deck elevator control system according to claim 5, wherein the destination floor indicating circuit comprises a plurality of second LED circuits, each second LED circuit comprising a second resistor and a second LED, one end of the second resistor being connected to one of the 1 parallel output pins of the displacement buffer IC4, the other end of the second resistor being connected to a forward terminal of the second LED, and a reverse terminal of the second LED being grounded.

10. The multi-deck elevator control system according to claim 9, wherein the elevator position indicating circuit comprises multiple third LED circuits, each third LED circuit comprising a third resistor and a third LED, one end of the third resistor being connected to one of the 1 parallel output pins of the demultiplexer IC2, the other end of the third resistor being connected to the reverse terminal of the second LED, and the forward terminal of the third LED being grounded.