CN218071468U

CN218071468U - Low level reset circuit with reset chip function

Info

Publication number: CN218071468U
Application number: CN202120434086.4U
Authority: CN
Inventors: 叶剑兵; 王剑波; 马亚斌; 韦栋
Original assignee: Hangzhou Nationalchip Science & Technology Co ltd
Current assignee: Hangzhou Guoxin Microelectronics Co.,Ltd.
Priority date: 2021-02-26
Filing date: 2021-02-26
Publication date: 2022-12-16
Anticipated expiration: 2031-02-26

Abstract

The utility model relates to a low level reset circuit with chip function resets. The application chip generally needs an external low-level reset circuit. The utility model discloses a charge-discharge resistance R, electrolytic capacitor C, schottky diode D, two NPN triodes and three control resistor. The three control resistors respectively control the on and off of the two NPN triodes, the two NPN triodes are used as electronic switches, and the electrolytic capacitor C is used for charging and discharging. After the IO power supply of the chip rises, a low level reset signal lasting for a certain time is obtained by resetting until the chip reset pin considers that the high level reset is finished. When the IO power supply of the chip is reduced to the reset threshold voltage, the NPN triode switch is conducted, the reset pin of the chip is pulled down rapidly, and abnormal reset is avoided. The utility model discloses a simple stable circuit has guaranteed the safe and reliable that the chip resets to can freely adjust reset threshold value and low level reset time.

Description

Low-level reset circuit with chip reset function

Technical Field

The utility model belongs to the technical field of integrated circuit, a low level reset circuit with chip function resets is related to.

Background

The chip is a large scale integrated circuit which contains a large number of digital-analog modular units, wherein part of the chip design has a reset unit, the purpose of which is to restore the whole system of the chip to an initial known state to start executing tasks. However, many chips are designed without a self-reset unit, and need to be reset by an external independent reset circuit or a reset chip. The reset chip has a good reset effect, but the use cost is high. And once the reset threshold voltage value and the reset time of the reset chip are selected, the reset threshold voltage value and the reset time cannot be changed and cannot be adjusted according to needs. The reset chip, such as MAX809, has only fixed several reset threshold voltage values (2.32/2.63/2.93/3.08/4.00/4.38/4.63V) and only provides fixed low level reset time. The existing reset circuit only adopts a structure of a resistor and an electrolytic capacitor or a ceramic capacitor, and the simple reset circuits have many defects in the actual debugging process, such as faults of halt and the like caused by incomplete reset.

Disclosure of Invention

The utility model aims at providing a low level reset circuit with chip function resets.

The utility model comprises a charge-discharge resistor R, an electrolytic capacitor C, a Schottky diode D, two NPN triodes and three control resistors; the three control resistors respectively control the on and off of the two NPN triodes, the two NPN triodes are used as electronic switches, and the electrolytic capacitor C is used for charging and discharging.

A cathode of the Schottky diode D is connected with one end of the charge-discharge resistor R, one end of the first control resistor R1 and one end of the second control resistor R2 and then serves as a power supply input end VDD; the base electrode of the first NPN triode Q1 is connected with the other end of the first control resistor R1 and one end of the third control resistor R3, and the collector electrode of the first NPN triode Q1 is connected with the other end of the second control resistor R2 and the base electrode of the second NPN triode Q2; a collector of the second NPN triode Q2, an anode of the Schottky diode D, the other end of the charge-discharge resistor R and the anode of the electrolytic capacitor C are connected and then serve as a reset output end RESETN; the emitting electrodes of the first NPN triode Q1 and the second NPN triode Q2, the negative electrode of the electrolytic capacitor C and the other end of the third control resistor R3 are connected and then grounded.

The utility model discloses set up NPN triode switch, RC charge and discharge circuit and schottky diode between chip reset foot and power ground, before chip IO power rises to the threshold voltage that resets, NPN triode switch switches on, and the low level reset signal who lasts a certain time resets to obtain, and NPN triode switch disconnection after exceeding threshold voltage that resets utilizes the not sudden change of capacitance voltage by RC charge and discharge circuit, continues to provide low level reset signal, and the foot considers the high level to reset the end until the chip resets. When the IO power supply of the chip suddenly drops, the voltage of the reset pin also quickly drops through the unidirectional conductivity of the Schottky diode, when the voltage drops to the reset threshold voltage, the NPN triode switch is conducted, the reset pin of the chip is quickly pulled down, and the reset pin is prevented from entering a level uncertain state to cause the next quick reset abnormal problem. The utility model discloses safe and reliable has guaranteed the safe and reliable that the chip resets through simple stable circuit. The utility model discloses can freely adjust reset threshold value and low level reset time, this reset circuit and reset method safe and reliable.

Drawings

Fig. 1 is a circuit diagram of the present invention.

Detailed Description

As shown in fig. 1, a low level reset circuit with a function of resetting a chip includes a charge and discharge resistor R, an electrolytic capacitor C, a schottky diode D, two NPN triodes, and three control resistors. The three control resistors respectively control the on and off of the two NPN triodes, the two NPN triodes are used as electronic switches, and the electrolytic capacitor C is used for charging and discharging.

When the circuit is used, a power input end VDD of the circuit is connected with an IO power supply of the chip, and a reset output end RESETN is connected with a low-level reset pin of the chip.

When the base emitter of the first PNP triode Q1 is more than or equal to the base emitter threshold of the triode Q1, the collector emitter of the first NPN triode Q1 is in saturated conduction to output a low level; when the base emitter of the first PNP triode Q1 is smaller than the base emitter threshold of the triode Q1, the collector emitter of the first NPN triode Q1 is cut off to output high level.

When the base emitter of the second PNP triode Q2 is more than or equal to the base emitter threshold of the triode Q2, the collector emitter of the second NPN triode Q2 is in saturation conduction and outputs low level; when the base emitter of the second PNP triode Q2 is smaller than the base emitter threshold of the triode Q2 itself, the collector emitter of the second NPN triode Q2 is cut off and is in the off state.

After the chip IO power supply is powered on, before the IO power supply rises to a reset threshold voltage value, the base electrode of the first NPN triode Q1 does not reach the base emitter junction threshold voltage of the triodes, the first NPN triode Q1 is cut off, the IO power supply voltage is directly added to the base electrode of the second NPN triode Q2 through controlling the second control resistor R2 at the same time, the second NPN triode Q2 is in saturated conduction, and the reset output end RESETN is clamped at a low level by the collector emitter junction of the second NPN triode Q2. When the IO power supply rises to a reset threshold voltage value, the base electrode of the first NPN triode Q1 reaches the base emitter junction threshold voltage of the triode, the first NPN triode Q1 is in saturated conduction, the collector emitter junction of the first NPN triode Q1 clamps the base emitter junction of the second NPN triode Q2, so that the second NPN triode Q2 is cut off, the IO power supply voltage charges the electrolytic capacitor C through the charge-discharge resistor R, and the reset output end RESETN keeps a low-level signal for a certain time (the length of the keeping time is determined by preset adjustment of the charge-discharge resistor R and the electrolytic capacitor C), so that the chip plays a role in resetting the refrigerator. The reset threshold voltage value is the reset threshold voltage value of the first NPN triode Q1, and is preset and adjusted by the first control resistor R1 and the third control resistor R3.

After the power failure of the IO power supply of the chip, the electrolytic capacitor C is rapidly powered down along with the IO power supply through the Schottky diode D, when the power failure reaches a reset threshold voltage value, the first NPN triode Q1 is rapidly cut off, and the second NPN triode Q2 is rapidly in saturation conduction, so that the electrolytic capacitor C is rapidly discharged to the ground through the collector-emitter junction of the second NPN triode Q2, the reset output RESETN is guaranteed not to appear in a level uncertain state, the reset abnormal phenomenon is avoided, the cold machine reset is ready to be connected again, and the problem that the abnormal starting of the second time is caused due to the fact that the machine is repeatedly started and shut down for the first time is avoided. The presetting of the reset threshold voltage value can avoid the incomplete reset problem caused by the power supply fluctuating to the unidentifiable level region.

When the reset threshold voltage value V is found _RESETN When not suitable, according to the requirement of the IO power supply voltage of the connected chip and the base emitter junction threshold voltage V of the first NPN triode Q1 _BE By varying the resistance R of the first control resistor R1 ₁ And a resistance value R of the third control resistor R3 ₃ And freely adjusting the magnitude of the reset threshold voltage value:

when the low-level reset time is not enough, according to the maximum reset time specifically required by the chip, the resistance value R 'of the charge-discharge resistor R and the capacitance value C' of the electrolytic capacitor C are changed, so that the low-level reset time T is changed _RESETN ：

V _DD For chip IO supply voltage, V _T The low level threshold voltage of the chip reset pin.

Claims

1. A low level reset circuit with chip reset function, its characterized in that:

the device comprises a charge-discharge resistor R, an electrolytic capacitor C, a Schottky diode D, two NPN triodes and three control resistors; the three control resistors respectively control the on and off of the two NPN triodes, the two NPN triodes are used as electronic switches, and the electrolytic capacitor C is used for charging and discharging;