CN217904414U

CN217904414U - Communication circuit and communication system

Info

Publication number: CN217904414U
Application number: CN202220770960.6U
Authority: CN
Inventors: 涂贤玲
Original assignee: Beijing SoundAI Technology Co Ltd
Current assignee: Beijing SoundAI Technology Co Ltd
Priority date: 2022-04-02
Filing date: 2022-04-02
Publication date: 2022-11-25
Anticipated expiration: 2032-04-02

Abstract

The application discloses communication circuit and communication system, this communication circuit includes switch circuit, charge-discharge circuit, RS trigger circuit and RS-485 chip. The switch circuit can control the level of the set end of the RS trigger circuit based on the level of the signal sending end in the communication circuit. The RS flip-flop circuit may adjust the level of its output terminal based on the level of its set terminal and the level of the signal transmitting terminal to which the reset terminal is connected. Because the output end of the RS trigger circuit is connected with the receiving enabling pin and the sending enabling pin of the RS-485 chip, the RS trigger circuit can realize the switching of the signal receiving and sending modes of the RS-485 chip by adjusting the level of the output end of the RS trigger circuit. According to the scheme provided by the application, the MCU is not required to switch the signal receiving and transmitting mode of the RS-485 chip, so that the control efficiency of the RS-485 chip is effectively improved, and the control complexity of the RS-485 chip is reduced.

Description

Communication circuit and communication system

Technical Field

The present disclosure relates to electronic technologies, and in particular, to a communication circuit and a communication system.

Background

Recommended standard-485 (RS-485) is a transmission standard of differential signals. Two devices in the communication system can realize the transmission of differential signals based on RS-485.

In the related art, two devices based on the communication system each include a Micro Controller Unit (MCU) and an RS-485 chip. When the MCU in any device needs to send signals, the sending enabling pin of the RS-485 chip can be controlled to be effective, so that the RS-485 chip transmits the signals sent by the MCU to the RS-485 chip of another device based on the RS-485. When the MCU needs to receive signals, the receiving enabling pin of the RS-485 chip can be controlled to be effective, so that the RS-485 chip can transmit signals sent by another device to the MCU.

However, the above communication method requires the MCU to control the valid states of the transmit enable pin and the receive enable pin of the RS-485 chip, and further control the RS-485 chip to transmit or receive signals. Therefore, the control complexity of the RS-485 chip is high, and the efficiency is low.

SUMMERY OF THE UTILITY MODEL

The application provides a communication circuit and a communication system, which can solve the problems of higher control complexity and lower efficiency of an MCU (micro control unit) to an RS-485 chip in the related art. The technical scheme is as follows:

in one aspect, a communication circuit is provided, where the communication circuit has a signal sending end and a signal receiving end, where the signal sending end and the signal receiving end are used to connect a communication chip, and the communication circuit includes: the device comprises an RS-485 chip, a switching circuit, a charging and discharging circuit and a Reset (Reset) Set (Set) RS trigger circuit;

a receiving pin of the RS-485 chip is connected with the signal receiving end, a sending pin of the RS-485 chip is connected with the signal sending end, a receiving enabling pin and a sending enabling pin of the RS-485 chip are respectively connected with a first power supply end and the output end of the RS trigger circuit, and a first transmission pin and a second transmission pin of the RS-485 chip are both used for being connected with a communication bus;

the control end of the switch circuit is connected with the signal sending end, the first end of the switch circuit is respectively connected with the first power end and the charge-discharge circuit, the second end of the switch circuit and the charge-discharge circuit are both connected with a ground end, the switch circuit is used for disconnecting the first end from the second end if the level of the signal sending end is a first level so as to enable the first power end to charge the charge-discharge circuit, and conducting the first end with the second end if the level of the signal sending end is a second level, wherein the second level is a high level relative to the first level;

the charging and discharging circuit is further connected with a setting end of the RS trigger circuit, and is used for keeping the level of the setting end at the second level after charging, discharging through the switch circuit after the first end is conducted with the second end, and keeping the level of the setting end at the second level in the discharging process;

the reset end of the RS trigger circuit is connected with the signal sending end, and the RS trigger circuit is used for adjusting the level of the output end based on the level of the reset end and the level of the reset end;

the effective level of the receiving enabling pin is the first level, and the effective level of the sending enabling pin is the second level.

Optionally, the switching circuit comprises: a switching transistor;

the grid of the switch transistor is used as the control end and connected with the signal sending end, the first pole of the switch transistor is used as the first end and respectively connected with the first power end and the charge and discharge circuit, and the second pole of the switch transistor is used as the second end and respectively connected with the grounding end and the charge and discharge circuit.

Optionally, the switch transistor is a Metal Oxide Semiconductor (MOS) transistor.

Optionally, the charging and discharging circuit includes: a first diode, a first resistor and a capacitor;

the anode of the first diode is connected with the first power supply end, the first end of the switch circuit and one end of the first resistor respectively, and the cathode of the first diode is connected with the position end of the RS trigger circuit, the other end of the first resistor and one end of the capacitor respectively;

and the other end of the capacitor is respectively connected with the second end of the switch circuit and the grounding end.

Optionally, the communication circuit further comprises: a current limiting circuit;

the current limiting circuit is respectively connected with the first power end, the receiving enabling pin, the sending pin, the first end of the switch circuit, the reset end of the RS trigger circuit and the charging and discharging circuit, and the current limiting circuit is used for limiting the current of the signal of the first power end, then respectively transmitting the current to the switch circuit, the charging and discharging circuit, the receiving enabling pin and the sending enabling pin, and respectively transmitting the current of the signal sending end to the reset end and the sending pin after limiting the current.

Optionally, the current limiting circuit comprises: a second resistor, a third resistor and a fourth resistor;

one end of the second resistor is connected with the first end of the switch circuit and the charging and discharging circuit respectively, the other end of the second resistor is connected with the first power end and one end of the third resistor respectively, and the other end of the third resistor is connected with the receiving enabling pin and the sending enabling pin respectively;

one end of the fourth resistor is connected with the signal sending end, and the other end of the fourth resistor is connected with the reset end of the RS trigger circuit and the sending pin respectively.

Optionally, the communication circuit further comprises: a matching circuit;

the matching circuit is respectively connected with a second power supply end, the ground end, the first transmission pin and the second transmission pin, and the matching circuit is used for pulling up the level of the first transmission pin to a third level and pulling down the level of the second transmission pin to a fourth level under the driving of the second power supply end and the ground end.

Optionally, the matching circuit comprises: a fifth resistor and a sixth resistor;

one end of the fifth resistor is connected with the second power supply end, and the other end of the fifth resistor is connected with the first transmission pin;

one end of the sixth resistor is connected with the second transmission pin, and the other end of the sixth resistor is connected with the ground terminal.

Optionally, the matching circuit further comprises: a seventh resistor;

one end of the seventh resistor is connected with the first transmission pin, and the other end of the seventh resistor is connected with the second transmission pin.

Optionally, the RS flip-flop circuit includes: the reset sub-circuit is connected with the reset end and the output end respectively;

the set sub-circuit includes: the circuit comprises a second diode, a third diode, a fourth diode, an eighth resistor, a ninth resistor, a tenth resistor, a first triode and a second triode;

the reset sub-circuit includes: the circuit comprises a fifth diode, a sixth diode, a seventh diode, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a third triode and a fourth triode.

In another aspect, a communication system is provided, the communication system including: a communication bus, a first device and a second device;

the first device includes: the first communication chip is respectively connected with a signal sending end and a signal receiving end of the first communication circuit;

the second device includes: the second communication chip is respectively connected with a signal sending end and a signal receiving end of the second communication circuit;

one end of the communication bus is connected with a first transmission pin and a second transmission pin of an RS-485 chip in the first communication circuit, and the other end of the communication bus is connected with a first transmission pin and a second transmission pin of an RS-485 chip in the second communication circuit;

wherein the first communication circuit and the second communication circuit are both the communication circuit of the above aspect.

The beneficial effect that technical scheme that this application provided brought includes at least:

the application provides a communication circuit and a communication system, wherein the communication circuit comprises a switch circuit, a charge and discharge circuit, an RS trigger circuit and an RS-485 chip. The switch circuit can control the level of the set end of the RS trigger circuit based on the level of the signal sending end in the communication circuit. The RS flip-flop circuit may adjust the level of its output terminal based on the level of its set terminal and the level of the signal transmitting terminal to which the reset terminal is connected. Because the output end of the RS trigger circuit is connected with the receiving enable pin and the sending enable pin of the RS-485 chip, the RS trigger circuit can realize the switching of the signal receiving and sending modes of the RS-485 chip by adjusting the level of the output end of the RS trigger circuit. According to the scheme provided by the application, the MCU is not required to switch the signal receiving and transmitting mode of the RS-485 chip, so that the control efficiency of the RS-485 chip is effectively improved, and the control complexity of the RS-485 chip is reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a communication system according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a communication circuit according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of another communication circuit provided in an embodiment of the present application;

fig. 4 is a schematic structural diagram of an RS flip-flop circuit according to an embodiment of the present application.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a communication system provided in an embodiment of the present application, and referring to fig. 1, the communication system includes: a communication bus, a first device 10 and a second device 20.

Wherein the first device 10 comprises: a first communication chip U1 and a first communication circuit 11. The first communication chip U1 is connected to a signal transmitting terminal TX1 and a signal receiving terminal RX1 of the first communication circuit 11, respectively.

The second device 20 includes: a second communication chip U2 and a second communication circuit 12, where the second communication chip U2 is connected to a signal transmitting terminal TX2 and a signal receiving terminal RX2 of the second communication circuit 12, respectively.

The communication bus is an RS-485 communication bus and comprises a first communication bus L1 and a second communication bus L2. The first communication bus L1 is connected to a first transmission pin A1 of the RS-485 chip 111 in the first communication circuit 11 and a first transmission pin A2 of the RS-485 chip 121 in the second communication circuit 12, respectively, and the second communication bus L2 is connected to a second transmission pin B1 of the RS-485 chip 111 in the first communication circuit 11 and a second transmission pin B2 of the RS-485 chip 121 in the second communication circuit 12, respectively.

In the embodiment of the present application, the first device 10 and the second device 20 may be two devices in the same electronic apparatus. Alternatively, the first device 10 and the second device 20 may be two devices in different electronic apparatuses. That is, the communication system provided in the embodiment of the present application may implement communication between two devices in the same electronic device, or may implement communication between different electronic devices.

It is to be understood that each of the first communication circuit 11 and the second communication circuit 12 has both a function of receiving a signal and a function of transmitting a signal. That is, the first communication chip U1 in the first device 10 may receive a signal from the second device 20 through the first communication circuit 11, and may transmit a signal to the second device 20 through the first communication circuit 11. Similarly, the second communication chip U2 in the second device may receive a signal from the first device 10 through the second communication circuit 12, and may transmit a signal to the first device 10 through the second communication circuit 12.

The first communication chip U1 in the first device 10 and the second communication chip U2 in the second device 20 may be Integrated Circuits (ICs) capable of communicating via an RS-485 bus in an electronic device. For example, the first communication chip U1 and the second communication chip U2 may both be MCUs.

Fig. 2 is a schematic structural diagram of a communication circuit according to an embodiment of the present disclosure. The communication circuit may be applied to the communication system shown in fig. 1, for example, the communication circuit may be the first communication circuit 11 or the second communication circuit 12 in the communication system shown in fig. 1. Referring to fig. 2, the communication circuit has a signal transmitting terminal TX and a signal receiving terminal RX. The signal transmitting terminal TX and the signal receiving terminal RX are used to connect a communication chip. The communication circuit includes: the circuit comprises an RS-485 chip 110, a switch circuit 120, a charge and discharge circuit 130 and an RS trigger circuit 140.

A receiving pin R of the RS-485 chip 110 is connected with a signal receiving terminal RX, a sending pin D of the RS-485 chip is connected with a signal sending terminal TX, and a receiving enabling pin of the RS-485 chip 110

And the transmission enable pin DE is respectively connected with the first power supply terminal V1 and the output terminal P _ Q of the RS trigger circuit 140, the first transmission pin a and the second transmission pin B of the RS-485 chip 110 are both used for being connected with a communication bus, the power supply pin of the RS-485 chip 110 is connected with the power supply terminal VCC, and the ground pin of the RS-485 chip 110 is connected with the ground terminal GND.

The RS-485 chip 110 is used for: if receiving the enable pin

Transmits signals of the first and second transmission pins a and B to the reception pin R if the level of the transmission enable pin DE is an active level, and transmits a signal of the transmission pin D to the first and second transmission pins a and B if the level of the transmission enable pin DE is an active levelAnd a pin B.

Wherein, the receiving enable pin

Is a first level, and the active level of the transmission enable pin DE is a second level, which is a high level with respect to the first level. For example, the first level may be a level having a magnitude of 0 volt (i.e., a low level), and the second level may be a level having a magnitude of the voltage of the first power source terminal V1 (i.e., a high level).

In the embodiment of the present application, the signals transmitted by the first transmission pin a and the second transmission pin B are differential signals. When the receiving enable pin of the RS-485 chip 110

When the level of (B) is an active level, the operation mode of the RS-485 chip 110 is a receiving mode, which can receive a differential signal on the communication bus through the first transmission pin a and the second transmission pin B. Thereafter, the RS-485 chip 110 can convert the differential signals on the first transmission pin a and the second transmission pin B into single-ended signals (which may also be referred to as level signals) and output the single-ended signals to the receiving pin R. The receiving pin R is further capable of transmitting the single-ended signal to a communication chip through a signal receiving terminal RX.

When the transmit enable pin DE of the RS-485 chip 110 is at an active level, the operating mode of the RS-485 chip 110 is a transmit mode, which can receive a single-ended signal of the signal transmit terminal TX through the transmit pin D. Then, the RS-485 chip 110 can convert the single-ended signal into a differential signal and output the differential signal to the first transmission pin a and the second transmission pin B.

Based on the above analysis, it can be known that the receiving enable pin of the RS-485 chip 110 is controlled

And the level of the transmission enable pin DE, the operating mode of the RS-485 chip 110 can be switched, thereby implementing transmission and reception of signals.

With reference to fig. 2, the control terminal C of the switch circuit 120 is connected to the signal transmitting terminal TX, the first terminal 1 of the switch circuit 120 is connected to the first power terminal V1 and the charge/discharge circuit 130, and the second terminal 2 of the switch circuit 120 and the charge/discharge circuit 130 are both connected to the ground GND. The switch circuit 120 is configured to disconnect the first terminal from the first terminal 1 and the second terminal 2 if the level of the signal transmitting terminal TX is a first level, so that the first power terminal V1 charges the charging and discharging circuit 130, and connect the first terminal 1 and the second terminal 2 if the level of the signal transmitting terminal TX is a second level.

As shown in fig. 2, the charge and discharge circuit 130 is further connected to the set terminal P _ S of the RS flip-flop circuit 140. The charging and discharging circuit 130 is configured to keep the level of the set terminal P _ S at the second level after charging, discharge through the switch circuit 120 after the first terminal 1 and the second terminal 2 of the switch circuit 120 are turned on, and keep the level of the set terminal P _ S at the second level during discharging.

The reset terminal P _ R of the RS flip-flop circuit 140 is connected to the signal transmitting terminal TX, and the RS flip-flop circuit 140 is configured to adjust the level of the output terminal P _ Q based on the level of the set terminal P _ S and the level of the reset terminal P _ R. If the level of the set terminal P _ S of the RS flip-flop circuit 140 is the first level, the level of the output terminal P _ Q is controlled to be the first level, and if the level of the set terminal P _ S is the second level and the level of the reset terminal P _ R is the first level, the level of the output terminal P _ Q is controlled to be the second level.

TABLE 1

Table 1 is a truth table for the RS flip-flop circuit 140. A value "1" in the truth table is used to indicate a high level (i.e., a second level), and a value "0" is used to indicate a low level (i.e., a first level). P _ Q ⁿ Indicating the level of the output terminal P _ Q of the RS flip-flop circuit 140 at the previous moment, i.e., the level before the transition. P _ Q ⁿ⁺¹ Indicating the current level, i.e., the level after the transition, of the output terminal P _ Q of the RS flip-flop circuit 140.

In the embodiment of the present application, the default electrical average of the signal transmitting terminal TX and the signal receiving terminal RX of the communication circuitAt a second level. In this case, the first terminal 1 and the second terminal 2 of the switch circuit 120 are turned on, and the charge and discharge circuit 130 may set the level of the set terminal P _ S of the RS flip-flop circuit 140 to the first level. Since the level of the reset terminal P _ R of the RS flip-flop circuit 140 is the second level, as shown in table 1, the level of the output terminal P _ Q of the RS flip-flop circuit 140 is the same as the level of the set terminal P _ S, and is also the first level. At this time, the RS-485 chip 110 is enabled by the receive enable pin

The RS-485 chip 110 can convert the differential signals received by the first transmission pin a and the second transmission pin B into single-ended signals and output the single-ended signals to the receiving pin R. Based on the above analysis, the RS-485 chip 110 is default to operate in the receiving mode.

When the communication chip sends a signal through the RS-485 chip 110, the RS-485 chip 110 needs to be converted from a default operating mode (i.e., a receiving mode) to a sending mode. It is understood that the data amount of the data transmitted by the communication chip at a time may be fixed, for example, 10 bits (bit) of data may be transmitted at a time. And, the level of the start bit of data transmitted each time defaults to a low level (i.e., a first level). Thus, each time the communication chip transmits data through the RS-485 chip, the electrical average of the signal transmitting terminal TX jumps from a high level (i.e., the second level) to a low level (i.e., the first level). At this time, the switch circuit 120 can disconnect the first terminal 1 from the second terminal 2, so that the first power source terminal V1 charges the charge/discharge circuit 130.

The charge and discharge circuit 130 may maintain the level of the set terminal P _ S at the second level (i.e., high level) after charging. Based on the truth table shown in table 1, when the set terminal P _ S of the RS flip-flop circuit 140 is at the second level and the reset terminal P _ R is at the first level, the level of the output terminal P _ Q of the RS flip-flop circuit 140 jumps from the default first level to the second level. At this time, since the transmission enable pin DE of the RS-485 chip 110 is at an active level, the RS-485 chip 110 can be automatically switched from a default receiving mode to a transmitting mode, and can transmit a start bit of received data of the transmitting pin D to the first and second transmission pins a and B.

In the process that the communication chip transmits data to the signal transmitting terminal TX through the RS-485 chip 110, if the level of the transmitted data is a low level, the signal transmitting terminal TX is a low level. Referring to the above-mentioned transmission procedure of the start bit, the transmit enable pin DE of the RS-485 chip 110 can maintain an active level, and the RS-485 chip 110 can transmit the data of the low level received by the transmit pin D to the first transmit pin a and the second transmit pin B.

If the level of the data transmitted by the communication chip is high, the signal transmitting terminal TX is high (i.e., the second level), and the reset terminal P _ R of the RS flip-flop circuit 140 is also high. At this time, the switch circuit 120 may turn on the first terminal 1 and the second terminal 2, so that the RS flip-flop circuit 140 discharges through the switch circuit 120, and the level of the set terminal P _ S can be maintained as the second level in the discharging process. Based on the truth table shown in table 1, when the levels of the set terminal P _ S, the reset terminal P _ R and the output terminal P _ Q of the RS flip-flop circuit 140 at the previous time are all the second level, the first power terminal V1 can enable the transmit enable pin DE and the receive enable pin DE of the RS-485 chip 110

Is pulled up to a second level. That is, the transmission enable pin DE of the RS-485 chip 110 is still at an active level, and the RS-485 chip 110 still operates in the transmission mode.

After the communication chip finishes transmitting data, the level of the signal transmitting terminal TX may be restored to a default second level. At this time, the reset terminal P _ R of the RS flip-flop circuit 140 is at the second level. Since the switch circuit 120 has completed discharging, the set terminal P _ S of the RS flip-flop circuit 140 is at the first level. At this time, based on the truth table of the RS flip-flop circuit 140 shown in table 1, the level of the output terminal P _ Q of the RS flip-flop circuit 140 is the same as the level of the set terminal P _ S, i.e., the output terminal P _ Q changes from the second level to the first level. At this time, the receiving enable pin of the RS-485 chip 110

Is active, the RS-485 chip 110 is thus able to automatically switch from a transmit mode to a receive mode.

In the embodiment of the present application, the discharge time period of the charge and discharge circuit 130 may be set based on the time period required for the communication chip to transmit data through the RS-485 chip 110 each time. For example, the discharge time period may be greater than or equal to a time period for which the communication chip transmits data through the RS-485 chip 110 each time. Thus, it can be ensured that the set terminal P _ S of the RS flip-flop circuit 140 can maintain the second level during the transmission of data, so that the transmission enable pin DE of the RS-485 chip 110 maintains an active level. After the discharge of the charge/discharge circuit 130 is completed, the level of the set terminal P _ S of the RS flip-flop circuit 140 is lowered to the first level.

It can be understood that the RS-485 chip 110 receiving enable pin is controlled by the RS trigger circuit 140

And the level of the enabling pin DE is sent, so that the time delay generated by the enabling pin of the RS-485 chip 110 in the process of switching the level can be effectively reduced. Moreover, the RS trigger circuit 140 can also be used as a data keeper to stabilize the receiving enable pin of the RS-485 chip 110

And a level of the transmission enable pin DE, thereby ensuring stable transmission of a signal. In addition, the receiving enable pin of the RS-485 chip 110 is controlled by the change of the level of the output end P _ Q of the RS trigger circuit 140

And the level of the transmission enable pin DE, when the switching rate of the switching circuit 120 is too high, the problem of packet loss generated when the RS-485 chip 110 receives and transmits signals is avoided.

It can also be understood that the charging and discharging circuit 130 and the RS trigger circuit 140 are disposed between the switch circuit 120 and the RS-485 chip 110, so as to improve the switch delay caused by the on/off state change of the switch circuit 120. Further, it is possible to ensure the reception enable of the RS-485 chip 110Pin

And the level of the transmission enable pin DE can be switched to a corresponding effective level in time to ensure the reliability of the RS-485 chip 110 for transmitting and receiving signals.

In summary, the embodiment of the application provides a communication circuit, which comprises a switch circuit, a charge and discharge circuit, an RS trigger circuit and an RS-485 chip. The switch circuit can control the level of the set end of the RS trigger circuit based on the level of the signal sending end in the communication circuit. The RS flip-flop circuit may adjust the level of its output terminal based on the level of its set terminal and the level of the signal transmitting terminal to which the reset terminal is connected. Because the output end of the RS trigger circuit is connected with the receiving enable pin and the sending enable pin of the RS-485 chip, the RS trigger circuit can realize the switching of the signal receiving and sending modes of the RS-485 chip by adjusting the level of the output end of the RS trigger circuit. According to the scheme provided by the embodiment of the application, the MCU is not needed to switch the signal receiving and sending modes of the RS-485 chip, so that the control efficiency of the RS-485 chip is effectively improved, and the control complexity of the RS-485 chip is reduced.

Fig. 3 is a schematic structural diagram of another communication circuit provided in an embodiment of the present application, and referring to fig. 3, the switch circuit 120 may include: the transistor Q1 is switched. A Gate (Gate, G) of the switching transistor Q1 is connected to the signal transmitting terminal TX as a control terminal C, a first pole of the switching transistor Q1 is connected to the first power terminal V1 and the charge/discharge circuit 130 as a first terminal 1, and a second pole of the switching transistor Q1 is connected to the ground terminal GND and the charge/discharge circuit 130 as a second terminal 2.

The switching transistor Q1 may be an N-type MOS transistor, the first pole of the switching transistor Q1 may be a Drain (Drain, D), and the second pole of the switching transistor Q1 may be a Source (Source, S).

It is understood that when the signal transmitting terminal TX is at the first level, the voltage of the gate G of the switching transistor Q1 is less than or equal to the voltage of the source S thereof, and the switching transistor Q1 is in an off state. At this time, the first power source terminal V1 can charge the charge and discharge circuit 130.

When the signal transmitting terminal TX is at the second level, the voltage of the gate G of the switching transistor Q1 is greater than the voltage of the source S thereof. Accordingly, a voltage between the gate G and the source S of the switching transistor Q1 is greater than a threshold voltage of the switching transistor Q1, and the drain D and the source S of the switching transistor Q1 are turned on. Thus, the level of the drain D of the switching transistor Q1 is pulled down to the first level by the ground GND. That is, the level of the first terminal 1 of the switch circuit 120 is pulled down to the first level by the ground terminal GND.

With continued reference to fig. 3, the charging and discharging circuit 130 may include: a first diode D1, a first resistor R1 and a capacitor C1. The anode of the first diode D1 is connected to the first power source terminal V1, the first end 1 of the switch circuit 120, and one end of the first resistor R1, and the cathode of the first diode D1 is connected to the set terminal P _ S of the RS flip-flop circuit 140, the other end of the first resistor R1, and one end of the capacitor C1. The other end of the capacitor C1 is connected to the second end 2 of the switch circuit 120 and the ground GND, respectively.

When the switching transistor Q1 of the switching circuit 120 is in an off state, the first power source terminal V1 can charge the capacitor C1 through the first resistor R1. After the capacitor C1 is charged, the end of the capacitor C1 connected to the set end P _ S is at a high level (i.e., a second level).

When the switching transistor Q1 in the switching circuit 120 is turned on, the first diode D1 is turned off based on the one-way conductivity of the first diode D1. Therefore, the capacitor C1 can be discharged through the first resistor R1 and the on-state switching transistor Q1. And, in the process of discharging the capacitor C1, the capacitor C1 can maintain the level of the set terminal P _ S of the RS flip-flop circuit 140 at the second level.

It can be understood that the driving capability of the switching transistor Q1 is weak. If the receiving enable pin of the RS-485 chip 110 is directly controlled by the switching transistor Q1

And a level of the transmission enable pin DE, which causes the RS-485 chip 110 to transmit and receive signalsThe capacity is weak, and the received or transmitted signals cannot be transmitted in a long distance. In the embodiment of the present application, the RS flip-flop circuit 140 has a capability of holding data and a strong driving capability. Therefore, the charge-discharge circuit 130 and the RS trigger circuit 140 are arranged between the switching transistor Q1 and the RS-485 chip 110, and the receiving enable pin of the RS-485 chip 110 is controlled by the output end P _ Q of the RS trigger circuit 140

And the level of the enable pin DE is sent, so that the RS-485 chip 110 is driven by strong driving capability to send and receive signals, and long-distance transmission of the signals is realized.

Optionally, with continued reference to fig. 3, the communication circuit may further include: a current limiting circuit 150. The current limiting circuit 150 is connected to the first power supply terminal V1 and the receiving enable pin respectively

The transmission enable pin DE, the transmission pin D, the first terminal 1 of the switching circuit 120, the reset terminal P _ R of the RS flip-flop circuit 140, and the charging and discharging circuit 130 are connected.

In the embodiment of the present application, the current limiting circuit 150 is configured to limit the current of the signal at the first power end V1 and transmit the signal to the switching circuit 120, the charging/discharging circuit 130, and the receiving enable pin

And a transmission enable pin DE, and is used for limiting the current of the signal from the signal transmitting terminal TX and then transmitting the current to the reset terminal P _ R of the RS trigger circuit 140 and the transmission pin D of the RS-485 chip 110, respectively.

As shown in fig. 3, the current limiting circuit 150 may include: a second resistor R2, a third resistor R3 and a fourth resistor R4. One end of the second resistor R2 is connected to the first end 1 of the switch circuit 120 and the charge/discharge circuit 130, and the other end of the second resistor R2 is connected to the first power terminal V1 and one end of the third resistor R3. The other end of the third resistor R3 is connected with the receiving enable pin of the RS-485 chip 110

And a transmit enable pin DE connection. One end of the fourth resistor R4 is connected to the signal transmitting terminal TX, and the other end of the fourth resistor R4 is connected to the reset terminal P _ R of the RS trigger circuit 140 and the transmitting pin D of the RS-485 chip 110, respectively.

In the embodiment of the present application, the second resistor R2 is used for limiting the current of the signal of the first power source terminal V1 and then respectively transmitting the current to the drain D of the switching transistor Q1 and the capacitor C1, so as to prevent the performance of the switching transistor Q1 and the capacitor C1 from being damaged when the signal of the first power source terminal V1 is too large. The third resistor R3 is used for limiting the current of the signal of the first power supply end V1 and then respectively transmitting the current to the receiving enable pin of the RS-485 chip 110

And a transmit enable pin DE to prevent performance of the RS-485 chip 110 from being compromised.

Optionally, the second resistor R2 may be further configured to: if the first terminal 1 and the second terminal 2 of the switch circuit 120 are turned off, the level of the set terminal P _ S of the RS flip-flop circuit 140 is pulled up to the second level under the driving of the first power terminal V1. The third resistor R3 may also be used to: if the first terminal 1 and the second terminal 2 of the switch circuit 120 are turned off and the output level of the RS flip-flop circuit 140 is variable, the receiving enable pin of the RS-485 chip 110 is driven by the first power source terminal V1

And the voltage average pull-up of the transmit enable pin DE to a second level.

The fourth resistor R4 is configured to limit a current of a signal from the signal sending terminal TX and transmit the current to the reset terminal P _ R of the RS trigger circuit 140 and the sending pin D of the RS-485 chip 110, so as to further prevent the performance of the RS-485 chip 110 from being damaged when the signal from the signal sending terminal TX is too large. In addition, the fourth resistor R4 can also play a role of delaying a signal of the signal transmitting terminal TX, so as to ensure that when the signal of the signal transmitting terminal TX is transmitted to the transmitting pin D of the RS-485 chip 110, the level of the transmitting enable terminal DE of the RS-485 chip 110 is hopped to an effective level.

Optionally, as shown in fig. 3, the communication circuit may further include: a matching circuit 160. The matching circuit 160 is connected to the second power source terminal V2, the ground terminal GND, the first transmission pin a, and the second transmission pin B, respectively.

In the embodiment of the present application, the matching circuit 160 is configured to pull up the level of the first transmission pin a to a third level and pull down the level of the second transmission pin B to a fourth level under the driving of the second power terminal V2 and the ground terminal GND. The third level is greater than the fourth level, that is, the third level is high relative to the fourth level. And, the level difference between the third level and the fourth level should be greater than the threshold level of the RS-485 chip (typically 200 mV).

The second power supply end V2 and the first power supply end V1 are both direct current power supplies in the communication system, and the direct current voltage of the second power supply end V2 and the direct current voltage of the first power supply end V1 can be set according to the communication requirement.

Referring to fig. 3, the matching circuit 160 may include: a fifth resistor R5 and a sixth resistor R6. One end of the fifth resistor R5 is connected to the second power terminal V2, and the other end of the fifth resistor R5 is connected to the first transmission pin a. One end of the sixth resistor R6 is connected to the second transmission pin B, and the other end of the sixth resistor R6 is connected to the ground GND.

It will be appreciated that when the RS-485 communication bus is open or idle (i.e., no signal is transmitted on the RS-485 communication bus), the differential voltage between the two buses in the RS-485 communication bus may be 0. At this time, the RS-485 communication bus is in an uncertain state, and the communication state of the RS-485 chip 110 is susceptible to interference from external factors.

In the embodiment of the present application, the matching circuit 160 can make the fifth resistor R5 pull up the level of the first transmission pin a to the third level under the driving of the second power terminal V2, and make the sixth resistor R6 pull down the level of the second transmission pin B to the fourth level under the driving of the ground terminal GND. Therefore, when the RS-485 communication bus is in an open circuit or an idle state, the differential voltage between the RS-485 communication buses is not 0 and is kept stable, so that the communication state of the RS-485 chip 110 is prevented from being interfered by external factors.

With continued reference to fig. 3, the matching circuit 160 may further include: a seventh resistor R7. One end of the seventh resistor R7 is connected to the first transmission pin a, and the other end of the seventh resistor R7 is connected to the second transmission pin B.

The seventh resistor R7 may be used as a terminal resistor to match the characteristic impedance of the RS-485 communication bus, so as to prevent the signal in the RS-485 communication bus from being reflected in the communication process between the first device 10 and the second device 20, thereby improving the communication quality of the communication system.

Fig. 4 is a schematic structural diagram of an RS flip-flop circuit 140 according to an embodiment of the present disclosure, and referring to fig. 4, the RS flip-flop circuit 140 may include a set sub-circuit 141 and a reset sub-circuit 142.

As shown in fig. 4, the set sub-circuit 141 includes: the circuit comprises a second diode D2, a third diode D3, a fourth diode D4, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a first triode T1 and a second triode T2.

The cathode of the second diode D2 is connected to the set terminal P _ S of the RS flip-flop circuit 140, and the anode of the second diode D2 is connected to one end of the eighth resistor R8, the anode of the third diode D3, and the anode of the fourth diode D4, respectively. The cathode of the fourth diode D4 is connected to the output terminal P _ Q of the RS flip-flop circuit 140, and the cathode of the third diode D3 is connected to the base of the first transistor T1. The collector of the first triode T1 is connected to the first power terminal V1, the other end of the eighth resistor R8, and one end of the ninth resistor R9, respectively. The other end of the ninth resistor R9 is connected to the collector of the second transistor T2 and the output end P _ Q of the RS flip-flop circuit 140. The emitter of the first triode T1 is connected to the base of the second triode T2 and one end of the tenth resistor R10, respectively. The other end of the tenth resistor R10 is connected to the emitter of the second diode T2 and the ground GND, respectively.

With continued reference to fig. 4, the reset sub-circuit 142 may include: a fifth diode D5, a sixth diode D6, a seventh diode D7, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a third triode T3, and a fourth triode T4.

The cathode of the fifth diode D5 is connected to the collector of the second transistor T2, the anode of the fifth diode D5 is connected to one end of the eleventh resistor R11, the anode of the sixth diode D6, and the anode of the seventh diode D7, the cathode of the seventh diode D7 is connected to the reset terminal P _ R of the RS flip-flop circuit 140, and the cathode of the sixth diode D6 is connected to the base of the third transistor T3. The collector of the third triode T3 is connected to the third power supply terminal V3, the other end of the eleventh resistor R11, and one end of the twelfth resistor R12, respectively. The other end of the twelfth resistor R12 is connected to the collector of the fourth transistor T4 and the output end P _ Q of the RS flip-flop circuit 140. The emitter of the third triode T3 is connected to the base of the fourth triode T4 and one end of the thirteenth resistor R13, respectively. The other end of the thirteenth resistor R13 is connected to the emitter of the fourth transistor T4 and the ground GND, respectively.

It is understood that the RS flip-flop circuit 140 implements the state transition of the set terminal P _ S, the reset terminal P _ R and the output terminal P _ Q thereof based on two nand gates. The second diode D2 and the fourth diode D4 in the set sub-circuit 141 form an and gate, and the first triode T1 and the second triode T2 form an inverter gate. The fifth diode D5 and the seventh diode D7 in the reset sub-circuit 142 form an and gate, and the third transistor T3 and the fourth transistor T4 form an not gate. Optionally, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may be NPN transistors.

In the embodiment of the present application, the nand gate in the set sub-circuit 141 has inputs of the level of the set terminal P _ S and the level of the output terminal P _ Q of the RS flip-flop circuit 140, and an output of the nand gate is the level of the collector of the second transistor T2. The working principle of the setting sub-circuit 141 is as follows: the level of the setting terminal P _ S and the level of the output terminal P _ Q of the RS flip-flop circuit 140 are and-operated by an and gate formed by a second diode D2 and a fourth diode D4, and then are not-operated by a not gate formed by a first triode T1 and a second triode T2. The level of the collector of the second transistor T2 is the output result of the set sub-circuit 141, i.e. the nand result.

For the nand gate in the reset sub-circuit 142, its inputs are the nand result in the set sub-circuit 141 and the level of the reset terminal P _ R, and its output is the level of the output terminal P _ Q of the RS flip-flop circuit 140. The operation principle of the reset sub-circuit 142 is as follows: the level of the reset terminal P _ R of the RS flip-flop circuit 140 and the nand result of the position sub-circuit 141 are and-operated by an and gate formed by a fifth diode D5 and a seventh diode D7, and then are not-operated by an nor gate formed by a third triode T3 and a fourth triode T4. The level of the collector of the fourth transistor T4 is the output result of the reset sub-circuit 142, i.e. the nand result.

For the set terminal P _ S and the reset terminal P _ R of the RS flip-flop circuit 140 in table 1 both being at the second level, the P _ Q of the RS flip-flop circuit 140 ⁿ⁺¹ Two cases where the true value is uncertain. When P _ Q ⁿ When the true value is "0" (i.e., the RS-485 chip 110 operates in the receiving mode at the last moment), if the communication chip is to transmit data through the RS-485 chip 110, the level of the set terminal P _ S of the RS flip-flop circuit 140 is set to the first level. Since the start bit of data transmitted by the communication chip at each time defaults to the first level, the level of the reset terminal P _ R connected to the signal transmitting terminal TX is also the first level. Therefore, in the embodiment of the present application, the true values of the set terminal P _ S and the reset terminal P _ R shown in table 1 are both "1", and the true values of the set terminal P _ S and the reset terminal P _ R do not appear, and the true values of the set terminal P _ S and the reset terminal P _ R are P _ Q ⁿ Is "0".

In this application, the terms "first," "second," and the like are used for distinguishing identical or similar items with substantially identical functions and functionalities, and it should be understood that "first," "second," and "n" have no logical or temporal dependency, and no limitation on the number or execution order.

The above description is only exemplary of the present application and should not be taken as limiting the present application, and any modifications, equivalents, improvements and the like that are made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A communication circuit having a signal transmitting end (TX) and a signal receiving end (RX) for connecting a communication chip, the communication circuit comprising: the device comprises an RS-485 chip (110), a switch circuit (120), a charge and discharge circuit (130) and a reset set RS trigger circuit (140);

a receiving pin (R) of the RS-485 chip (110) is connected with the signal receiving end (RX), a sending pin (D) of the RS-485 chip (110) is connected with the signal sending end (TX), and a receiving enabling pin of the RS-485 chip (110)

The transmission enable pin (DE) is respectively connected with a first power supply end (V1) and an output end (P _ Q) of the RS trigger circuit (140), and a first transmission pin (A) and a second transmission pin (B) of the RS-485 chip (110) are respectively used for being connected with a communication bus;

the control terminal (C) of the switch circuit (120) is connected to the signal transmitting Terminal (TX), the first terminal (1) of the switch circuit (120) is connected to the first power terminal (V1) and the charge and discharge circuit (130), the second terminal (2) of the switch circuit (120) and the charge and discharge circuit (130) are both connected to a ground terminal (GND), and the switch circuit (120) is configured to disconnect the first terminal (1) from the second terminal (2) if the level of the signal transmitting Terminal (TX) is a first level, so as to charge the charge and discharge circuit (130) with the first power terminal (V1), and to connect the first terminal (1) to the second terminal (2) if the level of the signal transmitting Terminal (TX) is a second level, where the second level is a high level relative to the first level;

the charging and discharging circuit (130) is further connected with a set terminal (P _ S) of the RS trigger circuit (140), the charging and discharging circuit (130) is used for keeping the level of the set terminal (P _ S) at the second level after charging, discharging is carried out through the switch circuit (120) after the first terminal (1) and the second terminal (2) are conducted, and the level of the set terminal (P _ S) is kept at the second level in the discharging process;

a reset terminal (P _ R) of the RS trigger circuit (140) is connected with the signal transmitting Terminal (TX), and the RS trigger circuit (140) is used for adjusting the level of the output terminal (P _ Q) based on the level of the set terminal (P _ S) and the level of the reset terminal (P _ R);

wherein the receive enable pin

Is the first level, and the active level of the transmit enable pin (DE) is the second level.

2. The communication circuit according to claim 1, wherein the switching circuit (120) comprises: a switching transistor (Q1);

the grid of the switching transistor (Q1) is used as the control end (C) and connected with the signal sending end (TX), the first pole of the switching transistor (Q1) is used as the first end (1) and connected with the first power end and the charging and discharging circuit (130) respectively, and the second pole of the switching transistor (Q1) is used as the second end (2) and connected with the grounding end (GND) and the charging and discharging circuit (130) respectively.

3. The communication circuit according to claim 2, wherein the switching transistor (Q1) is an N-type metal oxide semiconductor MOS transistor.

4. The communication circuit according to claim 1, wherein the charge and discharge circuit (130) comprises: a first diode (D1), a first resistor (R1) and a capacitor (C1);

an anode of the first diode (D1) is connected to the first power source terminal (V1), the first end (1) of the switch circuit (120), and one end of the first resistor (R1), respectively, and a cathode of the first diode (D1) is connected to the set terminal (P _ S) of the RS flip-flop circuit (140), the other end of the first resistor (R1), and one end of the capacitor (C1), respectively;

the other end of the capacitor (C1) is connected with the second end (2) of the switch circuit (120) and the ground terminal (GND) respectively.

5. The communication circuit according to any of claims 1 to 4, wherein the communication circuit further comprises: a current limiting circuit (150);

the current limiting circuit (150) is respectively connected with the first power supply end (V1) and the receiving enabling pin

The transmission enable pin (DE), the transmission pin (D), the first end (1) of the switch circuit (120), the reset end (P _ R) of the RS trigger circuit (140) and the charge and discharge circuit (130) are connected, and the current limiting circuit (150) is used for limiting the current of the signal of the first power end (V1) and then respectively transmitting the current to the switch circuit (120), the charge and discharge circuit (130) and the reception enable pin

And the transmission enable pin (DE) is used for limiting the current of the signal transmitting Terminal (TX) and then respectively transmitting the current to the reset terminal (P _ R) and the transmission pin (D).

6. The communication circuit according to claim 5, wherein the current limiting circuit (150) comprises: a second resistor (R2), a third resistor (R3) and a fourth resistor (R4);

one end of the second resistor (R2) is connected with the first end (1) of the switch circuit (120) and the charge-discharge circuit (130) respectively, the other end of the second resistor (R2) is connected with one end of the first power supply end (V1) and one end of the third resistor (R3) respectively, and the other end of the third resistor (R3) is connected with the receiving enable pin respectively

Is connected with the sending enable pin (DE);

one end of the fourth resistor (R4) is connected with the signal sending end (TX), and the other end of the fourth resistor (R4) is connected with the reset end (P _ R) of the RS trigger circuit (140) and the sending pin (D) respectively.

7. The communication circuit according to any of claims 1 to 4, further comprising: a matching circuit (160);

the matching circuit (160) is respectively connected with a second power supply end (V2), the ground end (GND), the first transmission pin (A) and the second transmission pin (B), and the matching circuit (160) is used for pulling up the level of the first transmission pin (A) to a third level and pulling down the level of the second transmission pin (B) to a fourth level under the driving of the second power supply end (V2) and the ground end (GND).

8. The communication circuit of claim 7, wherein the matching circuit (160) comprises: a fifth resistor (R5) and a sixth resistor (R6);

one end of the fifth resistor (R5) is connected with the second power supply end (V2), and the other end of the fifth resistor (R5) is connected with the first transmission pin (A);

one end of the sixth resistor (R6) is connected with the second transmission pin (B), and the other end of the sixth resistor (R6) is connected with the ground terminal (GND).

9. The communication circuit of claim 8, wherein the matching circuit (160) further comprises: a seventh resistor (R7);

one end of the seventh resistor (R7) is connected with the first transmission pin (A), and the other end of the seventh resistor (R7) is connected with the second transmission pin (B).

10. The communication circuit according to any of claims 1 to 4, wherein the RS trigger circuit (140) comprises: a set sub-circuit (141) and a reset sub-circuit (142), the set sub-circuit (141) being connected to the set terminal (P _ S) and the output terminal (P _ Q), respectively, the reset sub-circuit (142) being connected to the reset terminal (P _ R) and the output terminal (P _ Q), respectively;

the set sub-circuit (141) includes: a second diode (D2), a third diode (D3), a fourth diode (D4), an eighth resistor (R8), a ninth resistor (R9), a tenth resistor (R10), a first triode (T1) and a second triode (T2);

the reset sub-circuit (142) comprises: a fifth diode (D5), a sixth diode (D6), a seventh diode (D7), an eleventh resistor (R11), a twelfth resistor (R12), a thirteenth resistor (R13), a third transistor (T3) and a fourth transistor (T4).

11. A communication system, characterized in that the communication system comprises: a communication bus, a first device (10) and a second device (20);

the first device (10) comprises: the communication device comprises a first communication chip (U1) and a first communication circuit (11), wherein the first communication chip (U1) is respectively connected with a signal transmitting end (TX 1) and a signal receiving end (RX 1) of the first communication circuit (11);

the second device (20) comprises: the communication device comprises a second communication chip (U2) and a second communication circuit (12), wherein the second communication chip (U2) is respectively connected with a signal sending end (TX 2) and a signal receiving end (RX 2) of the second communication circuit (12);

one end of the communication bus is connected with a first transmission pin (A1) and a second transmission pin (B1) of an RS-485 chip (111) in the first communication circuit (11), and the other end of the communication bus is connected with a first transmission pin (A2) and a second transmission pin (B2) of an RS-485 chip (121) in the second communication circuit (12);

wherein the first communication circuit (11) and the second communication circuit (12) are both communication circuits according to any of claims 1 to 10.