CN217883396U - Analog-digital converter, chip and electronic equipment thereof - Google Patents

Abstract

The application provides an analog-digital converter, a chip and an electronic device thereof. The analog-to-digital converter includes: a sampling circuit; a switched capacitor circuit; a quantization noise shaping circuit; a quantizer; wherein the noise shaping circuit comprises: the filter circuit comprises a first filter circuit, a second filter circuit, a third filter circuit and an amplifier which are cascaded; the amplifier amplifies the shared quantization margin and shares the quantization margin to the first filter circuit and the second filter circuit, so that the first filter circuit and the second filter circuit can filter the received signals to be quantized. The application improves the precision of the ADC and reduces the power consumption.

Description

Analog-digital converter, chip and electronic equipment thereof

Technical Field

The present disclosure relates to circuit technologies, and in particular, to an analog-to-digital converter, a chip, and an electronic device thereof.

Background

Analog-to-Digital converters (ADCs) are widely used in electronic devices. The ADC is used to convert the detected analog signal to a digital signal that can be recognized by the processor of the electronic device.

In order to improve the conversion accuracy of the ADC, the ADC uses an oversampling sampling rate to improve the accuracy of the digital signal. In particular, when the number of quantization bits generated by the ADC is high, quantization noise in the circuit is large, and it is difficult to achieve a high accuracy.

Therefore, a noise shaping circuit of quantization noise is configured in the ADC so as to reduce the influence of the quantization noise on the precision. Although the noise shaping circuit effectively suppresses quantization noise in the digital signal, the problem that the accuracy and power consumption are difficult to meet engineering requirements still exists in some practical engineering.

SUMMERY OF THE UTILITY MODEL

The application provides an analog-digital converter, a chip and electronic equipment thereof, which are used for overcoming the problems of poor precision and high power consumption of the conventional ADC.

In a first aspect, the present application provides an analog-to-digital converter, wherein the analog-to-digital converter comprises: the sampling circuit is coupled to the input end of the analog-digital converter and samples the received analog signal according to a sampling period so as to output a sampling signal of an ith sampling period; the switch capacitor circuit is coupled between the quantizer and the sampling circuit and used for converting the received digital code into a reference signal in the ith sampling period so as to enable the reference signal and the sampling signal to be subtracted to form a signal to be quantized; the quantization noise shaping circuit is coupled to the output end of the switched capacitor circuit and used for performing noise filtering on the received signal to be quantized by using a quantization margin generated by at least the (i-1) th sampling period; the quantizer is coupled with the output end of the noise shaping circuit and the output end of the analog-digital converter and is used for converting the signal to be quantized after noise shaping into digital codes and outputting the digital codes; wherein the noise shaping circuit comprises: the cascade-connected third filter circuit, the first filter circuit, the second filter circuit and the amplifier; the amplifier amplifies the shared quantization margin and shares the quantization margin to the first filter circuit and the second filter circuit, so that the first filter circuit and the second filter circuit can filter the received signals to be quantized.

In an embodiment of the first aspect, the third filter circuit is coupled to a previous stage of the first filter circuit to form a cascade filter with the first filter circuit and the second filter circuit.

In an embodiment of the first aspect, the first filter circuit is a second order loop filter circuit; and/or the second filtering circuit is a first order loop filter.

In an embodiment of the first aspect, the first filtering circuit comprises: a plurality of first capacitor branches alternately coupled in a feedback path of a transmission path transmitting the signal to be quantized to store the shared quantization margin output from the amplifier at the (i-2) th sampling period; a second circuit branch coupled in a feedback path of the transmission path to store the shared quantization margin output by the amplifier at the (i-1) th sampling period; and the first capacitor branch storing the quantization residue of the (i-2) th sampling period and the second capacitor branch storing the quantization residue of the (i-1) th sampling period form a second-order feedback filter circuit, and the received signal is filtered in the ith sampling period.

In an embodiment of the first aspect, the quantizer comprises: the comparison circuit is coupled with the output end of the filter circuit and used for comparing the filtered signal to be quantized with a reference signal and outputting a comparison level; and the logic processing circuit is coupled to the output end of the comparison circuit and used for outputting the digital code according to the received comparison level.

In an embodiment of the first aspect, the ADC further comprises: and the control circuit is coupled with the noise shaping circuit and the quantizer, and controls the noise shaping circuit to share the quantization margin of the ith sampling period when the quantizer finishes digital coding of the corresponding analog signal in the ith sampling period is detected.

In an embodiment of the first aspect, the analog-to-digital converter comprises two inputs corresponding to a differential signal to receive the differential analog signal; and two differential transmission paths respectively connected with the input ends; wherein, each path of differential transmission path is connected with the sampling circuit, the switched capacitor circuit and the quantization noise shaping circuit.

In an embodiment of the first aspect, the quantization noise shaping circuits of the two differential transmission paths share the same amplifier; two input ends of the amplifier are respectively connected with each differential transmission path, and two output ends of the amplifier are respectively connected with a first filter circuit and a second filter circuit in the quantization noise shaping circuit of the corresponding differential transmission path.

In an embodiment of the first aspect, the logic processing circuit is a successive approximation logic module.

A second aspect of the application provides a chip, wherein the chip comprises an analog-to-digital converter according to any one of the first aspect.

In an embodiment of the second aspect, the chip is a chip of a radar sensor.

A third aspect of the present application provides an electronic device, which includes the chip of the second aspect, and a digital signal processor connected to the chip, for performing data processing on the digital signal output by the analog-to-digital converter, and outputting a processing result.

According to the analog-digital converter, the chip and the electronic equipment thereof, N-order noise shaping can be realized through at least two noise shaping loops in the analog-digital converter, and the residual voltage after the N-order noise shaping is obtained. The headroom voltage of at least two noise shaping loops in the noise shaping process can be amplified by one amplifying unit. Through the analog-digital converter, a plurality of amplifiers are not needed, the power consumption of the analog-digital converter is reduced, high-order noise shaping is realized, and the precision of analog-digital conversion of the analog-digital converter is improved.

Drawings

In order to more clearly illustrate the technical solutions in the present application or the prior art, the following briefly introduces the drawings needed to be used in the description of the embodiments or the prior art, and obviously, the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without inventive labor.

Fig. 1 is a schematic diagram of a circuit architecture of an ADC according to the present application;

FIG. 2a is a schematic diagram of a circuit architecture of an ADC including a quantization noise shaping circuit;

FIG. 2b is a schematic diagram of the equivalent model of FIG. 2 a;

FIG. 2c is a timing diagram of the operation of the ADC shown in FIG. 2 a;

FIG. 3 is a schematic diagram of another equivalent model of an ADC including a quantization noise shaping circuit;

FIG. 4 is a schematic diagram of another circuit architecture of an ADC including a quantization noise shaping circuit;

FIG. 5a is a schematic diagram of an equivalent model of the first filter circuit;

FIG. 5b is a schematic circuit diagram of the first filter circuit of FIG. 5 a;

FIG. 6 is a timing diagram of an ADC of the present application;

FIG. 7a is a schematic diagram of an equivalent model of the second filter circuit;

FIG. 7b is a circuit diagram of a second filter circuit corresponding to FIG. 7 a;

FIG. 8a is a schematic diagram of an equivalent model of the third filter circuit;

FIG. 8b is a schematic circuit diagram of a third filter circuit corresponding to FIG. 8 a;

fig. 9 is a schematic diagram of an equivalent model of the quantization noise shaping circuit 314 provided in the present application;

fig. 10 is a schematic circuit diagram of an ADC according to the present application;

fig. 11 is a schematic diagram of another circuit structure of the ADC provided in the present application.

With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.

Detailed Description

To make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.

The following first explains a part of the noun concept referred to in the present application:

the term "coupled" or "coupling" can have several different meanings depending on the context in which the term is used. For example, the term coupled may have the meaning of mechanically coupled or electrically coupled. As used herein, the term "coupled" or "coupling" may mean that two elements or devices may be connected to each other directly or through one or more intermediate elements or devices via electrical, or mechanical elements (such as, but not limited to, wires or cables, for example, depending on the particular application). Examples of couplings described herein include: direct electrical, inductive, or opto-coupling connections, etc. For example, electrical connections between two electrical devices are made using connections used in semiconductor manufacturing processes. For another example, signal connection between two electric devices is realized by using a non-contact connection mode such as an optical coupler assembly or an inductive sensing assembly. As another example, electrical or signal connections or the like may be made between regions representing different electrical devices using semiconductor processing.

Analog-to-Digital Converter (ADC): the ADC may be used to convert an analog signal to a digital quantity (e.g., digital encoding).

Resolution of ADC: the resolution of the ADC is expressed in terms of the number of bits of the output binary (or decimal) number. The resolution of the ADC may be used to characterize the resolution capability of the ADC on the incoming analog signal. The more bits the ADC outputs, the higher the resolution of the ADC, i.e., the greater the resolution of the ADC for analog signals. The smaller the number of bits output by the ADC, the lower the resolution of the ADC, indicating that the ADC has a weaker resolution for the analog signal.

In electronic devices such as sensors and driving circuits, the amplitude, frequency, or phase of an analog signal reflects the operating state of the electronic device, and therefore, the analog signal is converted into a digital code by the ADC, which is beneficial for subsequent circuits to analyze the signal.

To achieve the description of the analog signal with digital coding, the ADC converts each sampled discrete electrical signal into a corresponding digital code by sampling the analog signal. For example, fig. 1 is a schematic circuit architecture of an ADC according to the present application. As shown in fig. 1, the ADC includes: a sampling circuit 111, a quantizer 113, a switched capacitor circuit 112, and the like. The sampling circuit 111 is coupled to a signal transmission path between the input terminal of the ADC and the quantizer 113, and the switched capacitor circuit 112 is coupled between the quantizer 113 and the signal transmission path. In a sampling period, the sampling circuit 111 samples the level of the received analog signal to generate a sampling signal, the switched capacitor circuit 112 converts the digital code output by the ADC into an analog reference signal, and feeds back the analog reference signal to the output terminal of the sampling circuit 111 to obtain a deviation signal between the sampling signal and the reference signal, and the deviation signal (also called a quantized signal) is input to the quantizer 113, so that the quantizer 113 updates the output digital code. By repeatedly adjusting the above update of the corresponding bit number in one sampling period, the digital code output by the ADC represents the level of the sampled signal.

The sampling circuit 111 samples the received analog signal according to a sampling period to output a sampling signal of an ith sampling period. The sampling period is usually a period of several clock signal periods. The sampling circuit 111 includes a switching device, a holding circuit, and the like to hold a sampling signal reflecting the analog signal at the sampling timing within one sampling period.

The switched capacitor circuit 112 is coupled between the quantizer 113 and the sampling circuit 111, and is configured to encode the received digital code in the ith sampling period and convert the encoded digital code into a reference signal, so that the reference signal and the sampling signal are subtracted from each other to form a signal to be quantized.

The switched capacitor circuit 112 includes a digital-to-analog converter (DAC) for converting a digital code into an analog reference signal. The DAC comprises a switch array and an energy storage device array, wherein fig. 2a is a schematic diagram of a circuit architecture of an ADC comprising a quantization noise shaping circuit. As shown in the switched capacitor circuit 112 shown in fig. 2a or the switched capacitor circuit 512 shown in fig. 10, the switch array selectively charges/discharges the energy storage device array under the control of the level signal representing each bit in the digital code, so that the energy storage device array outputs the reference signal corresponding to the digital code. The energy storage device array is exemplified by a capacitor device array. According to the feedback mechanism of the switched capacitor circuit 112, the reference signal and the sampling signal are destructively mixed to form a deviation signal, the deviation signal represents the level deviation between the reference signal and the sampling signal, and the deviation signal is transmitted to the quantizer 113 as the signal to be quantized through the transmission path connected to the output terminal of the sampling circuit 111.

The quantizer 113 receives a signal to be quantized, converts the received signal to be quantized into digital codes, and outputs the digital codes. Here, the number of bits n is set at a higher than nyquist sampling rate. The quantizer 113 converts the level of the sampled signal into the nearest digital code of n bits by quantizing the signal to be quantized at least once in one sampling period, where n > 2. As shown in fig. 1, the quantizer 113 includes a comparison circuit and a logic processing circuit. The comparison circuit compares the signal to be quantized with a reference signal and outputs a comparison level (high or low level) in accordance with a bit n. The logic processing circuit is coupled to the output end of the comparison circuit and used for generating quantized digital codes according to the received comparison level. The reference signal is, for example, a preset level signal, such as a zero level signal, for the comparison circuit to compare the voltage levels of the signal to be quantized and the reference signal. For example, the Logic processing circuit includes a successive approximation type Logic circuit (also referred to as SAR Logic circuit). The logic processing circuit outputs the digital code of each adjusted bit to the switched capacitor circuit 112, so that the switched capacitor circuit 112 adjusts the corresponding reference signal and performs differential mixing with the sampling signal; the comparison circuit outputs a corresponding comparison level along with the level change of the signal to be quantized, and then the logic processing circuit adjusts the digital coding of the next bit. Thus, the logic processing circuit executes judgment for n times in one sampling period, and finally the digital code closest to the sampling signal is obtained.

In still other examples, the ADC includes two inputs to receive a differential analog signal. Correspondingly, each signal transmission path in the dual-input ADC includes a sampling circuit 111 and a switched capacitor circuit 112. The quantizer 113 receives two signals to be quantized, compares the voltages of the two signals to be quantized with each other by using reference signals of the two signals to be quantized, and performs logic processing on corresponding bits according to the voltage, so as to adjust the corresponding digital codes. The quantizer 113 performs the decision n times in one sampling period, and finally obtains the digital code of the sampled signal closest to the difference.

In the above digital conversion process, the quantizer 113 generates a process of digital coding representing the sampled signal by using the signal to be quantized, which is also called quantization process, and the generated quantization error is accumulated along with the increase of the number of times of adjusting the digital coding, so that when the ADC outputs a plurality of bit numbers of the digital coding, it is difficult to converge, resulting in low precision, which does not meet the precision requirement of some electronic devices (such as sensors, etc.). For example, in a radar sensor, the digital code output by the ADC representing the DC signal cannot reflect abnormal fluctuations in the DC signal, and the like.

To this end, a quantization noise shaping circuit is also included in the ADC, which has the ability to push quantization noise (from quantizer 113) to higher frequencies, also referred to as noise shaping. The quantization noise shaping circuit suppresses quantization noise of a low frequency by loop filtering or the like in accordance with the number of bits set based on the oversampling rate, so as to shift the quantization noise to a high frequency outside the band, thereby improving the accuracy of the output digital code. For example, the quantization noise shaping circuit shares the quantization noise accumulated in at least one sampling period as a quantization margin to an energy storage device in the quantization noise shaping circuit to form at least one stage of a filter circuit using the shared quantization margin to suppress power of a low frequency part of the quantization noise. To this end, the quantization noise shaping circuit is coupled to an analog transmission path in the ADC.

The quantization noise shaping circuit is pre-stored with charges for realizing low-pass or high-pass filtering. Wherein the stored charge can be injected from the outside. In some examples, the ADC further comprises: and a control circuit, coupled to the quantization noise shaping circuit and the quantizer 113, for controlling at least some energy storage devices in the noise shaping circuit to share the quantization margin of the ith sampling period when it is detected that the quantizer 113 completes digital encoding of the corresponding sampling signal in the ith sampling period.

The control circuit is typically integrated with the logic processing circuit, and may be configured independently. The control circuit monitors the completion of the last bit converted in the current sampling period, e.g. the last phi bit in the current sampling period _CONV A down-going edge of the signal; and output phi _EX The signal is effective to control the on-off of a switch device in the quantization noise shaping circuit so as to form a circuit loop which enables an energy storage device in the quantization noise shaping circuit to share the quantization allowance of the current sampling period; when phi is _EX And when the signal is invalid, the control circuit adjusts the on-off of a switch element in the quantization noise shaping circuit to form a plurality of cascaded loop filter circuits for filtering the signal to be quantized in the next sampling period. The control circuit may also generate an AND-voltage in dependence on the control voltage of the group of switching devices _XX Phi of signal inversion _NS Signals to implement the control logic described above.

Fig. 2b is a schematic diagram of the equivalent model of fig. 2 a. As shown in fig. 2b, it is an equivalent model diagram of the quantization noise shaping circuit in the ADC. The equivalent model may be configured as a passive first order quantization noise shaping circuit. Where Vi is the sampled signal, E _q To quantify noise, do is a digital code, a1, b1, and c1 are all charge sharing coefficients, Z ^-1 The amount of charge shared by the previous sampling cycle. The equivalent model may be represented by the circuit structure of the quantization noise shaping circuit 114 in the ADC as shown in fig. 2 a.

As shown in fig. 2a, where VREFP represents the positive reference level, VREFN represents the negative reference level, and C1, C2 are both capacitances in the quantization noise shaping circuit 114. The quantizer 113 in the ADC includes a comparator (also called a comparison circuit) and a SAR Logic (Logic) module (i.e., a Logic processing circuit).

Fig. 2c is a timing diagram of the operation of the ADC shown in fig. 2 a. As shown in FIG. 2c, CLK represents the clock signal, φ _S Represents the sampled signal phi _CONV Indicating a control signal, phi, outputting one bit _EX And the control signal is used for sharing residual charge between the reference signal and the sampling signal in the current sampling period. Wherein, the residual charge includes the quantization error accumulated in the current sampling period. At the phi _EX Under the action of the signal, a quantization noise shaping circuit in the ADC shares the residual charge as a quantization margin to each energy storage device. Specifically, as shown in FIG. 2c, in addition to the normal sampling and quantization operation of the ADC, an additional time slot is added, consisting of _EX Controlling a group of switches of each capacitor C1 connected between two analog signal transmission paths to be switched on, and controlling another group of switches of each capacitor C1 connected between a single transmission path to be switched off, so that the pair of capacitors C1 extract quantization allowance (namely residual charge); by

The control is opposite to the two groups of switches. Thus, charge sharing of the quantization margin from the capacitor C1 to the capacitors C1 and C2 is completed before sampling of the next cycle. In the quantization process of the next sampling period, the noise shaping loop filters low-frequency components in the signal to be quantized by using the shared quantization margin of the previous sampling period, so that the comparison circuit not only quantizes the input signal obtained by sampling, but also quantizes the integral margin of the previous period.

However, the first-order quantization noise shaping circuit has a limited filtering effect, so that the quantization noise of its ADC is also limited to be improved.

To this end, fig. 3 is a schematic diagram of another equivalent model of an ADC including a quantization noise shaping circuit. As shown in fig. 3, the quantization noise shaping circuit comprises two cascaded FIR Filters (FIRs) ₁ And FIR ₂ ). Wherein, V _IN For the signal to be input to the FIR filter in the transmission path, QE (also called Eq) is the quantization noise, D _OUT Is digitally encoded. The FIR filter is a filter comprising an active device, and although the low-frequency power can be effectively inhibited by adopting modes such as a cascade FIR filter and the like, the shaping effect of quantization noise is improved; however, since high precision is still required to be maintained at low bits of digital coding, an amplifier is provided in each stage of the FIR filter, thereby increasing the power consumption of the ADC. For a sensor chip with low power consumption, the precision of digital coding output by an ADC in some low power consumption modes is in a contradiction with the power consumption of the ADC. The low power consumption mode includes, for example, a standby mode of the radar sensor.

Therefore, the application also provides the ADC, and the number of active devices is reduced on the basis of not reducing the shaping effect of quantization noise of the ADC, namely the power consumption of the ADC is reduced.

Fig. 4 is a schematic diagram of another circuit architecture of an ADC including a quantization noise shaping circuit. As shown in fig. 4, the ADC includes: a sampling circuit 311, a switched capacitor circuit 312, a quantization noise shaping circuit 314, and a quantizer 313. The circuit structures and the operation processes of the sampling circuit 311, the switched capacitor circuit 312, and the quantizer 313 are substantially equivalent to those shown in fig. 1, and will not be repeated here. Unlike fig. 1, the quantization noise shaping circuit 314 is coupled to the output terminal of the switched capacitor circuit, and is configured to perform noise filtering on the received signal to be quantized by using a quantization margin generated by at least an (i-1) th sampling period. Wherein the noise shaping circuit is set according to a noise transfer function. The noise shaping circuit includes: a first filter circuit, a second filter circuit, a third filter circuit, and an amplifier (shown as Amp in fig. 4) in cascade; the amplifier amplifies the shared quantization margin and shares the quantization margin to the first filter circuit and the second filter circuit, so that the first filter circuit and the second filter circuit can filter the received signals to be quantized.

Here, the noise shaping circuit is according to phi as shown in FIG. 2c _EX The signals share a charge signal including at least the quantization margin generated by the (i-1) th sampling period, i.e., the difference between the reference signal and the sampling signal remaining in the DAC after the (i-1) th sampling period is determined using the last bit. To this end, in phi _EX And in the signal storage duration, the switch components in the first filter circuit and the second filter circuit share the quantization margin amplified by the amplifier to each energy storage device. And in phi _EX In the signal invalid time period, the switch components in the first filter circuit and the second filter circuit are controlled to form two loop filter circuits by each energy storage device, so that the time slot (such as phi) of each bit in the ith sampling period _CONV Pulse duration), the signal to be quantized is filtered and transmitted to the quantizer 313.

Unlike fig. 1, the signal to be quantized received by the quantizer 313 is a signal filtered by the quantization noise shaping circuit 314. The filtered signal to be quantized contains a shaped low-frequency part, so that the quantizer 313 can perform more accurate quantization judgment on the corresponding bit, and the quantization precision is improved.

The quantization noise shaping circuit 314 in this example is an active filter comprising at least two loops of amplifiers with better low frequency rejection compared to a passive filter, while providing quantization margin of gain for both filtering loops with one amplifier, thereby effectively reducing power consumption of the ADC.

To improve the noise shaping effect, in some examples, the first filter circuit is a second order loop filter circuit. An example of an equivalent model of the first filter circuit is shown in fig. 5 a. Fig. 5a is a schematic diagram of an equivalent model of the first filter circuit. The sharing coefficients c2, e2, etc. of the quantization margin are related to the capacitance ratio in the first filter circuit. Where Vin is a sampling signal, vref is a reference signal generated by digital encoding, and Vout1 is a signal output by the first filter circuit.

Wherein, in order to realize the loop filter of second order, the first filter circuit includes: a plurality of first capacitance branches alternately coupled in a feedback path of a transmission path transmitting a signal to be quantized to alternately implement: storing the shared quantization margin output by the amplifier during the (i-1) th sampling period, and switching in the feedback path during the (i + 1) th sampling period to provide a filtering function. Thereby corresponding to the circuit configuration shown by path P11 in fig. 5 a.

For example, a Ping-Pong controlled capacitor array is formed by a plurality of first capacitor branches, and fig. 5b is a schematic circuit structure diagram of the first filter circuit corresponding to fig. 5 a. Referring to fig. 5b, the Ping-Pong capacitor array includes a plurality of first capacitor branches (K20, C8, K21, or K20', C8', K21 '), a first input terminal of each of the first capacitor branches is coupled to the output terminal of the amplifier, and a second input terminal of each of the first capacitor branches is coupled to a VCM (voltage common mode). The first output end of each first capacitor branch is coupled to two sides of a capacitor C4 in a transmission path of a signal to be quantized through a first switch path (K12, K14) and the second output end of each first capacitor branch is coupled to two sides of the capacitor C4 in the transmission path of the signal to be quantized through a second switch path (K13, K15) to form a loop filter.

Fig. 6 is a timing diagram of an ADC of the present application. As shown in FIG. 5b and FIG. 6, during the (i-1) th sampling period φ _EX Under the control of the signal, the control circuit selects the switch device groups (K20 and K21) in one part of the first capacitor branches to be turned on, selects the switch device groups (K20 'and K21') in the other part of the first capacitor branches to be turned off, and switches (K12, K10, K13 and K11) on the corresponding first switch paths and second switch paths to be turned off, so that the capacitor C8 in the corresponding first capacitor branches stores the quantization margin of the (i-1) th shared amplifier output. Phi in the ith sampling period _NS A signal (or)

Signal), the control circuit selects the switching devices (K12 ) on the first and second switching paths,K10, and K13, K11) are turned on, and the switching devices (K20 and K21) on the corresponding first capacitance branch are turned off, and the switching device groups (K20 ' and K21 ') in the first capacitance branch are turned on, so that the corresponding capacitance C8' shares the stored quantization margin of the (i-2) th amplified output to the capacitance C4.

The first filter circuit further includes a second circuit branch (e.g., branch K8, C5, K9 shown in fig. 5 b) coupled to a feedback path of a transmission path for transmitting a signal to be quantized, for storing a shared quantization margin output from the amplifier at the (i-1) th sampling period.

Still referring to fig. 5b and 6, in contrast to the connection of the Ping-Pong controlled capacitance array, the first input of the second circuit branch is connected to the VCM and the second input is connected to the output of the amplifier. Corresponding to the circuit structure shown in path P12 in fig. 5a, the second capacitor branch and the first capacitor branch form a negative feedback path according to the parameter configuration of the two capacitor branches. Phi in the (i-1) th sampling period _EX Under signal control, the switch device groups (K8 and K9) are turned on, and the switch device groups (K12, K10, and K13, K11) are turned off, so that the capacitor C5 stores the quantization margin of the amplifier output shared at the (i-1) th time. Phi in the ith sampling period _NS A signal (or)

Signal), the set of switches (K8 and K9) is turned off, and the set of switches (K12, K10, and K13, K11) is turned on, and the capacitor C5 provides a negative feedback signal using the stored quantization margin.

The Ping-Pong controlled capacitor array and the second capacitor branch form a negative feedback path of a signal to be quantized in the transmission path, the negative feedback path and the capacitor C4 are used for filtering, and the first filter circuit outputs the signal to be quantized to the second filter circuit.

Illustratively, the second filtering circuit filters the signal to be quantized received in the ith sampling period by a quantization margin obtained in at least one sampling period and amplified by the amplifier. The second filter circuit is exemplified by a first order or a second order loop filter.

To balance the accuracy of the digital encoding with the convergence efficiency of the quantization noise shaping circuit 314, in some examples, the second filtering circuit is a first order loop filter. Fig. 7a is a schematic diagram of an equivalent model of the second filter circuit, where IN and OUT represent the input and output of the signal to be quantized on the transmission path, respectively, and d3 and b3 correspond to coefficients of quantization margin shared by the energy storage devices IN the second filter circuit. Fig. 7b is a schematic circuit structure diagram of the second filter circuit corresponding to fig. 7 a. The third capacitance branch (K16, C7 and K17) is coupled to two sides of the capacitor C6, wherein the capacitor C6 is connected to the transmission path of the signal to be quantized, the first input terminal of the third capacitance branch (K16, C7 and K17) is connected to the output terminal of the amplifier, and the second input terminal thereof is connected to the VCM, so as to form a feedforward filter circuit.

As shown in FIG. 6 in conjunction with FIG. 7b, at Φ _EX Under signal control, the switch device groups (K16 and K17) are turned on, and the switch device groups (K18, K19) are turned off, so that the capacitor C7 stores the quantization margin of the (i-1) th shared output of the amplifier. Phi in the ith sampling period _NS A signal (or)

Signal), the switch group (K16 and K17) is turned off, and the switch group (K18, K19) is turned on, the capacitor C7 shares the stored quantization margin to the capacitor C6, so that the capacitor C7 and the capacitor C6 form a mixed loop filter.

And the third filter circuit in the quantization noise shaping circuit 314 is used for shaping and filtering the signal to be quantized formed by the switched capacitor circuit and the sampling circuit 311, and outputting the signal to be quantized to the first filter circuit. The third filter circuit is preferably a passive loop filter to improve the filtering effect without increasing the power consumption of the ADC. Here, the third filter circuit is a feedforward loop filter in order to filter the signal to be quantized in time response. For example, fig. 8a is a schematic diagram of an equivalent model of the third filter circuit. As shown in fig. 8a, the third filter circuit has the same equivalent model structure as the second filter circuit, except that the third filter circuit does not obtain the shared quantization margin from the output of the amplifier. IN and OUT represent the input-output relationship of the signal to be quantized on the signal transmission path, respectively, and d4 and b4 correspond to the coefficients of the quantization margin shared by the energy storage device IN the second filter circuit.

Fig. 8b is a schematic circuit structure diagram of the third filter circuit corresponding to fig. 8 a. As shown in fig. 8b, the capacitor C1 is controlled by two sets of switching devices, wherein the set of switching devices (K2 and K1) connects the capacitor C1 between the transmission path of the signal to be quantized and the voltage VCM, and the set of switching devices (K3 and K4) connects the capacitor C1 across the fourth capacitor branch (K5, C3 and K6). And the fourth capacitor branch is connected to a transmission path of the signal to be quantized. Thereby forming a first order loop filter as shown in fig. 8 a.

In conjunction with FIG. 8a and FIG. 6, at phi _EX Under signal control, the switch device groups (K2 and K1) are turned on, and the switch device groups (K3, K4, and K5, K6) are turned off, so that the capacitor C1 stores the quantization margin shared by the (i-1) th output of the amplifier. Phi in the ith sampling period _NS A signal (or)

Signal), the switch element groups (K2 and K1) are turned off, and the switch element groups (K3, K4, and K5, K6) are turned on, the capacitor C1 shares the stored quantization margin to the capacitor C3, thus realizing the feedforward loop filtering formed by the capacitors C1 and C3.

It should be noted that the first filter circuit may be cascaded at the input or output of the second filter circuit according to the transfer function of the quantization noise shaping circuit 314. The third filter circuit may be cascaded at the input of the first filter circuit or cascaded at the output of the second filter circuit. Accordingly, the coefficients in the transfer function may be different.

Fig. 9 is a schematic diagram of an equivalent model of the quantization noise shaping circuit 314 provided in the present application. As shown in the schematic diagram of the equivalent model shown in fig. 9, taking an example that the quantization noise shaping circuit 314 includes a third filter circuit 1141, a first filter circuit 1142, and a second filter circuit 1143 that are sequentially cascaded, an amplifier 1144 is connected between the first filter circuit 1142 and the second filter circuit 1143. The technician sets the sharing coefficients in each filter circuit according to the swing of the analog signal received by the ADC and the number of digital coded bits. For example, the coefficients g = f =0.5, d =1/8, e =1/16, b =16/17, c =1/17, and the amplification factor amp =16 of the amplifier; the noise transfer function can be derived as:

correspondingly, the capacitance parameter in the third filter circuit in the quantization noise shaping circuit 314 conforms to C1= C3; the capacitance parameter in the first filter circuit conforms to C4: C5: C8= 13; the capacitance parameter in the second filter circuit corresponds to C6=16C7.

In summary, the quantization noise shaping circuit 314 including the first filter circuit, the second filter circuit and the third filter circuit forms a four-order noise shaping filter cascaded in a three-loop. The quantization noise shaping circuit 314 not only applies the quantization margin of at least one sampling period to the filtering operation of the subsequent sampling period, but also provides the shared quantization margin to the two cascaded filters by using the amplifier, thereby effectively suppressing the power of the quantization noise in the low frequency band, and effectively reducing the power consumption of the ADC itself.

Fig. 10 is a schematic circuit diagram of an ADC according to the present application. With reference to fig. 6 and 10, the operation of the ADC in the (i-1) th and ith sampling periods, where i is greater than 2, is illustrated as follows:

under the control of the clock signal CLK, logic devices in the ADC, such as registers, flip-flops, etc., perform corresponding logic operations to adjust the digital code. Signal phi _S 、φ _CONV 、φ _NS 、φ _EX Are generated by logic processing circuits or control circuits integrated in logic processing circuits. Wherein phi is _S For controlling the sampling circuit 311 to perform a sampling operation on the received analog signal, wherein the sampling operation is performed under phi as shown in FIG. 10 _S Controlled by signalsThe switching device group aims to enable the energy storage devices in the filter circuits to inject initial voltage into the energy storage devices before the energy storage devices obtain shared charges, so that the energy storage devices can operate normally. Phi is a _CONV For controlling the switched-capacitor circuit to generate a time-slot update reference signal for each digital code in a sampling period. Phi is a unit of _NS 、φ _EX A pair of inverse control signals for controlling the switch device set in the quantization noise shaping circuit 314 to switch on and off, so as to perform the operation of sharing the quantization margin and perform the filtering operation in different time slots.

Phi at the (i-1) th sampling period _S Phi corresponding to the last bit during the signal failure period _CONV Under control of the signal, the CDAC in the switched-capacitor circuit 512 adjusts the switch array to generate a reference signal, and the deviation between the reference signal and the sampled signal sampled by the sampling circuit (not shown) contains the accumulated quantization error of performing quantization conversion for a plurality of times during the sampling period. Phi of the last bit in the (i-1) th sampling period _CONV During signal failure, and at signal phi _EX The deviation is shared as a quantization margin to each filter circuit (5141, 5142, 5143) in the quantization noise shaping circuit 314 for feedforward/feedback loop filtering in the ith sampling period. Among the shared quantization residuals, at least a part of the quantization residuals is amplified by the amplifier 5144 and shared to the first filter circuit 5142 and the second filter circuit 5143.

Phi at ith sampling period _S In the effective period of the signal, the sampling circuit collects the received analog signal and keeps the sampled signal voltage in the whole sampling period, and the switched capacitor circuit outputs a preset (also called initial) reference signal to a transmission path of the analog signal connected with the output end of the sampling circuit, so that the transmission path transmits a deviation signal of the sampling signal and the reference signal, namely a signal to be quantized. At a phi _CONV In the pulse time slot of the signal, the signal to be quantized passes through the third filter circuit 5141, the first filter circuit 5142 and the second filter circuit 5143 in sequence to realize the filtering of the signal to be quantized. Wherein the third filter circuit 5141 is of a previous stageA feed filter circuit that integrates the received signal to be quantized to provide low pass filtering; the first filter circuit 5142 is a second-order negative feedback filter circuit, which performs band-pass filtering on the received signal to be quantized through signal amplification provided by an amplifier and negative feedback provided by a second-order loop; the second filter circuit 5143 is still a first-order feedforward filter circuit, which is configured with a capacitor C6 much larger than a capacitor C7 to match the amplified quantization margin output by the amplifier 5144, so as to implement low-pass filtering suitable for the third stage. The quantization noise in the deviation signal is shaped to a high frequency region in this way, so as to obtain a signal to be quantized which is subjected to noise shaping. The noise-shaped signal to be quantized is input to the quantizer, wherein the comparator 5131 performs quantization judgment on the signal by using a reference signal, and wherein the logic processing 5132 adjusts the value of the corresponding bit in the digital code according to the quantization judgment level, and outputs the adjusted value to the switched capacitor 512 and to a next stage port (not shown), such as an output terminal of the ADC or an input terminal of the digital filter. While outputting the digital code, a control circuit (not shown) generates a signal having a phi _CONV So that the switched capacitor circuit 512 outputs a new reference signal, and the filtering and digital conversion processes are repeatedly performed. Different from the last repeated process, in the last filtering process, because the deviation signal is in the step-by-step filtering process, the quantization margin obtained by each stage of energy storage device is adjusted according to the level of the deviation signal. Therefore, the ADC equipped with the quantization noise shaping circuit 314 can convert an analog signal into 16-bit digital code, and the quantization error is below-98 dBFS.

The ADC provided by the present application may also be adapted to a differential signal analog-to-digital converter, which, unlike the above-described ADC example, includes two analog signal inputs, each of which is connected to a separate differential transmission path. A sampling circuit, a switched capacitor circuit, and a quantization noise shaping circuit 314 are arranged in each of the differential transmission paths. In order to simplify the circuit complexity, fig. 11 is a schematic diagram of another circuit structure of the ADC provided in the present application. As shown in fig. 11, the quantization noise shaping circuits 314 of the two differential transmission paths in the ADC share the same amplifier amp, where the amplifier amp is a fully differential amplifier, and two input ends of the amplifier amp are respectively connected to each of the differential transmission paths; and two output terminals thereof are respectively connected to the first filter circuit and the second filter circuit in each quantization noise shaping circuit 314. Two input ends of a comparison circuit in the quantizer respectively receive the differential transmission paths so as to receive the differential signal to be quantized after quantization noise shaping. In the quantization process, quantization noise Eq is introduced, and the output digital codes Do are respectively output to two switch capacitor circuits so as to respectively subtract the differential sampling signals Vin.

In this embodiment, the three-loop cascade and the four-order noise shaping are performed, and only a single amplifier is used for the ADC, so that the purpose of multi-loop high-order quantization noise shaping in the ADC for differential signals is achieved by using the single amplifier, the accuracy of analog-to-digital conversion performed by the ADC is further improved, and the power consumption of the analog-to-digital conversion is reduced.

The present application also provides a chip that may include an analog-to-digital converter as described in any of the previous embodiments.

It should be appreciated that the present application contemplates that the ADC in the chip is adapted to digitally convert intermediate or low frequency signals, such as DC signals for testing by external circuitry, or baseband signals. Illustratively, the chip may be a chip of a radar sensor, for example. Correspondingly, the DC signal includes, for example, a detection signal indicating the output power of the signal transmitter, or a DC signal indicating the power supply of the chip, or the like. The baseband signal includes, for example, a received signal down-converted by a signal receiver, and the like.

Alternatively, the chip may be a chip of other types of sensors, such as a pressure sensor, a voice signal receiving sensor, an acceleration sensor, a speed sensor, and the like. Taking the chip as a chip of a radar sensor as an example, the chip of the radar sensor converts a radio frequency electrical signal into an intermediate frequency electrical signal, for example; then, a digital code representing the intermediate frequency electrical signal is obtained by the analog-to-digital converter. The chip of the radar sensor is beneficial to the digital coding and signal processing to realize the measurement, target processing and the like of the target.

The embodiment of the application also provides electronic equipment configured with the chip, such as an automatic auxiliary driving system of an automobile, indoor cabin detection equipment and the like. The chip configured for the electronic device includes an ADC provided by any of the above examples of the present application. For example, the chip is a chip of a radar sensor, and the chip converts a baseband signal, a detection signal, and the like into digital codes by using an ADC and outputs the digital codes. The chip may further include a signal processor to perform, for example, 2-FFT, or angle FFT on the baseband digital signal output from the ADC to obtain physical quantities including distance, velocity, and angle. With the physical quantity, the signal processor can perform processing including object detection, object recognition, and the like.

Part of or all of the circuits in the signal processor may also be independent of the chip for physical quantity detection of the surrounding environment and subsequent data processing.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and these modifications or substitutions do not depart from the scope of the technical solutions of the embodiments of the present application.

Claims (12)

1. An analog-to-digital converter, comprising:

the sampling circuit is coupled to the input end of the analog-digital converter and samples the received analog signal according to a sampling period so as to output a sampling signal of an ith sampling period;

the switch capacitor circuit is coupled between the quantizer and the sampling circuit and used for coding the received digital code in the ith sampling period and converting the coded digital code into a reference signal so as to enable the reference signal and the sampling signal to be subtracted to form a signal to be quantized;

the quantization noise shaping circuit is coupled to the output end of the switched capacitor circuit and used for performing noise filtering on the received signal to be quantized by using a quantization margin generated by at least the (i-1) th sampling period;

the quantizer is coupled with the output ends of the noise shaping circuit and the analog-digital converter and is used for converting the signal to be quantized after noise shaping into digital codes and outputting the digital codes;

wherein the noise shaping circuit comprises: the filter circuit comprises a first filter circuit, a second filter circuit, a third filter circuit and an amplifier which are cascaded; the amplifier amplifies the shared quantization margin and shares the quantization margin to the first filter circuit and the second filter circuit, so that the first filter circuit and the second filter circuit can filter the received signals to be quantized.

2. The adc of claim 1, wherein the third filter circuit is coupled to a previous stage of the first filter circuit to form a cascade filter with the first filter circuit and the second filter circuit.

3. The analog-to-digital converter according to claim 1, wherein the first filter circuit is a second order loop filter circuit; and/or the second filtering circuit is a first order loop filter.

4. The analog-to-digital converter according to claim 1, wherein the first filter circuit comprises:

a plurality of first capacitor branches alternately coupled in a feedback path of a transmission path transmitting the signal to be quantized, for storing the shared quantization margin output from the amplifier at the (i-2) th sampling period;

a second circuit branch coupled in a feedback path of the transmission path to store the shared quantization margin output by the amplifier at the (i-1) th sampling period;

and the first capacitor branch storing the quantization residue of the (i-2) th sampling period and the second capacitor branch storing the quantization residue of the (i-1) th sampling period form a second-order feedback filter circuit, and the received signal is filtered in the ith sampling period.

5. The analog-to-digital converter according to claim 1, wherein the quantizer comprises:

the comparison circuit is coupled to the output end of the filter circuit and used for comparing the filtered signal to be quantized with a reference signal and outputting a comparison level;

and the logic processing circuit is coupled with the output end of the comparison circuit and used for outputting a digital code according to the received comparison level.

6. The analog-to-digital converter according to claim 5, wherein the logic processing circuit is a successive approximation type logic block.

7. The analog-to-digital converter of claim 1, further comprising: and the control circuit is coupled with the noise shaping circuit and the quantizer and controls the noise shaping circuit to share the quantization allowance of the ith sampling period when the quantizer finishes the digital coding of the corresponding analog signal in the ith sampling period is detected.

8. The analog-to-digital converter of claim 1, wherein the analog-to-digital converter comprises two inputs corresponding to a differential signal for receiving the differential analog signal; and two differential transmission paths respectively connected with the input ends; wherein, each path of differential transmission path is connected with the sampling circuit, the switched capacitor circuit and the quantization noise shaping circuit.

9. The analog-to-digital converter according to claim 8, wherein the quantization noise shaping circuits of the two differential transmission paths share the same amplifier; two input ends of the amplifier are respectively connected with each differential transmission path, and two output ends of the amplifier are respectively connected with a first filter circuit and a second filter circuit in the quantization noise shaping circuit of the corresponding differential transmission path.

10. A chip, characterized in that it comprises an analog-to-digital converter according to any of claims 1 to 9.

11. The chip of claim 10, wherein the chip is a chip of a radar sensor.

12. An electronic device, comprising the chip of claim 10 or 11, and a digital signal processor connected to the chip for performing data processing on the digital signal output by the analog-to-digital converter and outputting a processing result.

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