CN217690049U

CN217690049U - SOC chip circuit

Info

Publication number: CN217690049U
Application number: CN202220561959.2U
Authority: CN
Inventors: 罗小平; 鄢曹臣; 刘文龙; 陈旭
Original assignee: Shenzhen Longhorn Automotive Electronic Equipment Co Ltd
Current assignee: Shenzhen Longhorn Automotive Electronic Equipment Co Ltd
Priority date: 2022-03-11
Filing date: 2022-03-11
Publication date: 2022-10-28
Anticipated expiration: 2032-03-11

Abstract

An embodiment of the utility model provides a SOC chip circuit, the circuit includes: each level configuration module is provided with a level sampling point; an eMMC memory in which startup data is stored; the card reader is used for inserting a storage card with starting data stored inside, and comprises a data reading pin and a storage card insertion detection pin; the SOC chip comprises card reading pins and level detection pins, the SOC chip is configured to detect the level states of the level detection pins during power-on so as to obtain actual starting parameters of the SOC chip, when the actual starting parameters are the same as prestored comparative starting parameters, starting operation is performed by selecting to read starting data in the storage card from the card reader, and otherwise, starting operation is performed by directly selecting to read starting data from the eMMC memory. The system of the embodiment has higher safety and can provide various starting ways for the SOC chip.

Description

SOC chip circuit

Technical Field

The embodiment of the utility model provides a SOC chip technical field especially relates to an SOC chip circuit.

Background

At present, vehicle-mounted ECU systems such as vehicle-mounted image controllers, automatic parking systems, automatic driving systems, and streaming media rearview mirrors generally adopt an SOC chip circuit as a main control core. When an SOC chip (for example, a tda2ex series chip) of an existing SOC chip circuit is powered on, the SOC chip detects the actual level configuration of a level configuration module outside the SOC chip through a level detection pin, and then converts the actual level configuration into actual starting parameters for storage; and after the vehicle-mounted ECU system is produced and manufactured, the SOC chip directly judges the starting mode of the SOC chip according to the actual starting parameters, and the traditional starting mode of the SOC chip is to perform starting work by reading starting data pre-stored in an external eMMC memory. However, since the startup data is usually stored in the vfat partition of the eMMC storage, when the eMMC storage is abnormally powered down, the internal startup data is easily damaged, which may cause the SOC chip to start up abnormally, the startup path is relatively single, and the system security is poor; in order to improve the safety, on the basis of keeping the existing SOC chip starting circuit, a norflash which is safer and more stable to store is added outside the SOC chip to backup system starting data, but the mode obviously increases the design cost and the starting time is longer.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a technical problem who solves lies in, provides a SOC chip circuit, and system security is higher, can provide multiple start-up way for the SOC chip, and reduction in production cost shortens the start-up time.

In order to solve the technical problem, an embodiment of the utility model provides a following technical scheme: an SOC chip circuit comprising:

the system comprises a plurality of level configuration modules connected between an external power supply and a ground terminal, wherein each level configuration module is provided with a level sampling point;

an eMMC memory in which startup data is stored;

the card reader is used for inserting a storage card with starting data stored inside, and comprises a plurality of data reading pins and a storage card insertion detection pin which is switched from a default first level to a second level when the storage card is inserted into the card reader, wherein the storage card insertion detection pin is connected with at least one level sampling point; and

the SOC chip connected with the eMMC memory comprises a plurality of card reading pins connected with the data reading pins in a one-to-one corresponding mode and a plurality of level detection pins connected with the level sampling points in a one-to-one corresponding mode, the SOC chip is configured to detect the level states of the level detection pins when the SOC chip is powered on so as to obtain actual starting parameters of the SOC chip, when the actual starting parameters are the same as prestored comparison starting parameters, starting data in the memory card are selected to be read from the card reader to start running, otherwise, starting data are directly selected to be read from the eMMC memory to start running, and the comparison starting parameters are starting parameters obtained by converting the level states of the level sampling points connected with the memory card insertion detection pins into the level states of the level sampling points at the second level.

Further, the card reader also comprises a CMD pin, a VDD pin, a CLK pin and a GND pin, wherein:

the CMD pin is connected to a command sending pin of the SOC through a first resistor R1;

the VDD pin is connected to an external power supply;

the CLK pin is connected to a clock pin of the SOC chip;

the GND pin is connected to a ground terminal.

Further, the VDD pin is also connected to a ground terminal through a parallel connection body of the first capacitor C1 and the second capacitor C2.

Furthermore, the CMD pin, the CLK pin, the memory card insertion detection pin, and each of the data reading pins are connected to a ground terminal through an anti-static diode, and are connected to the external power supply through a current limiting resistor.

Furthermore, each data reading pin is correspondingly connected to the card reading pin through a protection resistor, and the memory card insertion detection pin is also correspondingly connected to the state judgment pin of the SOC chip through a protection resistor.

Furthermore, each level configuration module comprises a pull-up resistor and a pull-down resistor which are connected in series, wherein the pull-up resistor is connected with an external power supply, the pull-down resistor is connected with a grounding terminal, and each level configuration module is provided with one level sampling point on a line between the pull-up resistor and the pull-down resistor.

Further, the SOC chip further includes a parameter storage register for storing the actual startup parameter.

After the technical scheme is adopted, the embodiment of the utility model provides an at least, following beneficial effect has: the embodiment of the utility model provides a through at every level configuration module of connecting between external power source and earthing terminal configuration a level sampling point, correspond the storage card with the card reader insert detect the pin at least with one the level sampling point links to each other, because the storage card inserts detect the pin when the storage card inserts the card reader by acquiescent first level switch into the second level, and SOC chip's level detect the pin with the level sampling point one-to-one is connected, can insert the card reader through the storage card and adjust the level state of at least one level detection pin of SOC chip, and then adjust actual start parameter, on the one hand, the contrast start parameter that each level state of level detection pin corresponds when the storage card corresponds the card reader, and the contrast start parameter is with the storage card inserts detect the pin and link to each level sampling point's level that the level sampling point is when the second level state conversion and get the start parameter, thereby via the card reader reads in the storage card start data starts the operation; on the other hand, the SOC chip corresponds to the level state of each level detection pin when the storage card is not inserted into the card reader, so that the starting data in the eMMC memory is directly read for starting operation, and then the SOC chip can realize different starting modes according to the insertion state of the storage card.

Drawings

Fig. 1 is a schematic block diagram of an alternative embodiment of the SOC chip circuit of the present invention.

Fig. 2 is a schematic circuit diagram of an alternative embodiment of the SOC chip circuit of the present invention.

Fig. 3 is a flowchart illustrating steps of an alternative embodiment of a method for controlling a start path of an SOC chip using an SOC chip circuit according to an embodiment of the present invention.

Fig. 4 is a schematic block diagram of an eMMC memory according to an optional embodiment of a SOC chip start path control method for an SOC chip circuit according to an embodiment of the present invention.

Detailed Description

The present application will now be described in further detail with reference to the accompanying drawings and specific examples. It is to be understood that the following illustrative embodiments and description are only intended to illustrate the present invention, and are not intended to limit the present invention, and features in the embodiments and examples may be combined with each other in the present application without conflict.

As shown in fig. 1 and 2, an alternative embodiment of the present invention provides an SOC chip circuit, including: the system comprises a plurality of level configuration modules 1 connected between an external power supply A and a ground terminal, wherein each level configuration module 1 is provided with a level sampling point B;

an eMMC memory 3 in which startup data is stored;

the card reader 5 is used for inserting a storage card with starting data stored inside, the card reader 5 comprises a plurality of data reading pins (such as D0-D3 shown in fig. 2) and a storage card insertion detection pin (such as a CD pin shown in fig. 2) which is switched from a default first level to a second level (usually, from a high level to a low level) when the storage card is inserted into the card reader 5, and the storage card insertion detection pin is connected with at least one level sampling point B; and

the SOC chip 7 connected to the eMMC memory 3 includes a plurality of card reading pins (MMIC _ D0 to D3 shown in fig. 2) connected to the data reading pins in a one-to-one correspondence manner, and a plurality of level detection pins (GPMC _ AD5 to AD0 shown in fig. 2) connected to the level sampling points B in a one-to-one correspondence manner, the SOC chip 7 is configured to detect the level states of the level detection pins during power-up to obtain actual start parameters of the SOC chip 7, when the actual start parameters are the same as pre-stored comparison start parameters, the start parameters read from the memory card in the memory card 5 are selected to start operation, otherwise, the start parameters read from the eMMC memory 3 are directly selected to start operation, and the comparison start parameters are converted from the level states of the level sampling points at the second level.

The embodiment of the utility model provides a through dispose a level sampling point B in every level configuration module 1 of connecting between external power supply A and earthing terminal, correspond the storage card that will card reader 5 insert detect the pin at least with one level sampling point B links to each other, because the storage card inserts detect the pin when the storage card inserts card reader 5 by acquiescent first level switch into the second level, and SOC chip 7's level detect the pin with level sampling point B one-to-one is connected, can insert card reader 5 through the storage card and adjust the level state of SOC chip 7 at least one level detect the pin, and then adjust actual start parameter, on the one hand, SOC chip 7 corresponds the contrast start parameter that the level state of each level detect the pin corresponds when the storage card inserts card reader 5, and the contrast start parameter is with the storage card inserts the level of detecting the level sampling point that detects the pin and links to each level state conversion of level sampling point at the second level and gets the start parameter, thereby read in the storage card via card reader 5 start data start operation; on the other hand, the SOC chip 7 detects the level state of the pins according to the level when the storage card is not inserted into the card reader 5, so that the starting data in the eMMC memory 3 is directly read to start operation, and then the SOC chip 7 realizes different starting modes according to the insertion state of the storage card.

In an optional embodiment of the present invention, as shown in fig. 2, the card reader 5 further includes a CMD pin, a VDD pin, a CLK pin, and a GND pin, wherein:

the CMD pin is connected to a command sending pin of the SOC chip 7 through a first resistor R1;

the VDD pin is connected to an external power supply A;

the CLK pin is connected to a clock pin of the SOC chip 7;

the GND pin is connected to a ground terminal.

In this embodiment, the CMD pin is a command of the card reader 5 and a corresponding multiplexing pin, and is used for command interaction between the SOC chip 7 and the memory card; the VDD pin is a power supply pin of the card reader 5 and is used for supplying power to the memory card; the CLK pin is a clock signal pin of the SOC chip 7 and is used for synchronizing the memory card and the clock of the SOC chip 7; the GND pin is a grounding pin and is used for grounding the memory card, and the normal and stable work of the card reader 5 and the memory card is ensured through the circuit arrangement. In specific implementation, since there may be a difference between rated voltages of different types of memory cards, the supply voltage of the external power supply a connected to the VDD pin may be 3.3V or 1.8V, and the supply voltage of the external power supply a connected to the level configuration module 1 is 3.3V.

In an alternative embodiment of the present invention, as shown in fig. 2, the VDD pin is further connected to the ground terminal through a parallel connection body of the first capacitor C1 and the second capacitor C2. In this embodiment, the VDD pin is connected to the ground terminal through the parallel connection body of the first capacitor C1 and the second capacitor C2, so that noise and ac components in the external power supply a can be effectively filtered, and the stability of circuit operation is ensured.

In an alternative embodiment of the present invention, as shown in fig. 2, the CMD pin, the CLK pin, the memory card insertion detection pin, and each of the data reading pins are respectively connected to a ground terminal through an anti-static diode (e.g., ED7 to ED1 shown in fig. 1) on the one hand, and are respectively connected to the external power supply a through a current limiting resistor (e.g., R14 to R20 shown in fig. 1) on the other hand. In this embodiment, the card reader 5 can be effectively protected by further providing the anti-static diode and the current-limiting resistor, thereby avoiding electrostatic interference.

In an optional embodiment of the present invention, as shown in fig. 2, each of the data reading pins is correspondingly connected to the card reading pin through a protection resistor (e.g., R21 to R24 shown in fig. 2), and the memory card insertion detection pin is also correspondingly connected to the state determination pin (e.g., MMIC _ SDCD shown in fig. 2) of the SOC chip 7 through a protection resistor (e.g., R25 shown in fig. 2). In this embodiment, the protection resistor is arranged to effectively protect the card reading pin and the state judgment pin of the SOC chip 7, and to realize stable data transmission and communication, wherein the SOC chip 7 judges whether the memory card is inserted into the card reader 5 according to the level state of the state judgment pin when operating normally.

In an optional embodiment of the present invention, each of the level configuration modules 1 includes a pull-up resistor and a pull-down resistor connected in series, in the embodiment shown in fig. 2, there are 6 level configuration modules 1, the resistors R2, R4, R6, R8, R10 and R12 in fig. 2 are pull-up resistors in the corresponding level configuration module 1 respectively, and the resistors R3, R5, R7, R9, R11 and R13 are pull-down resistors in the corresponding level configuration module 1 respectively, wherein the pull-up resistors are connected to an external power supply a, the pull-down resistors are connected to a ground terminal, and a line between the pull-up resistor and the pull-down resistor of each level configuration module 1 is provided with a level sampling point B. In this embodiment, each of the level configuration modules 1 adopts a pull-up resistor and a pull-down resistor connected in series, and level configuration can be realized by adjusting the pull-up resistor and the pull-down resistor.

In specific implementation, as shown in fig. 2, the resistances of the resistors R2 and R4 are the same and are both 1 kilo-ohm; the resistances of the resistors R6, R8, R10, R12, R3, R5, R7, R9, R11 and R13 are all 10 kilo-ohms; the SOC chip 7 determines actual start parameters according to the level states of the pins GPMC _ AD5 to AD0, for example, in the embodiment of fig. 2, level sampling points B corresponding to GPMC _ AD0, GPMC _ AD3, and GPMC _ AD4 are connected to a memory card insertion detection pin (CD pin); correspondingly, when the memory card is not inserted into the card reader 5, the level states of the GPMC _ AD5 to AD0 are high level, low level, high level and high level in sequence, and the corresponding starting parameter is 0b111011 in binary form; when the memory card is inserted into the card reader 5, the level states of the GPMC _ AD5 to the GPMC 0 are high level, low level, high level and low level in sequence, and the corresponding starting parameter is 0b100010 in a binary form.

In an optional embodiment of the present invention, the SOC chip 7 further includes a parameter storage register for storing the actual start parameter. In this embodiment, the actual start parameter is stored in the parameter storage register, so that the SOC chip 7 can directly read the actual start parameter in the parameter storage register when powering on next time, thereby implementing power on start without repeatedly determining the level state of each level detection pin, and increasing the start speed.

As shown in fig. 3, the SOC chip start path control method using the SOC chip circuit provided by the embodiment of the present invention includes the following steps:

s1: level detection pins of the SOC chip 7 are correspondingly connected with level sampling points B of the level configuration module 1 one by one, and a storage card insertion detection pin of the card reader 5 is connected with at least one level sampling point B, the storage card insertion detection pin is switched from a default first level to a second level when a storage card is inserted into the card reader 5, and starting data are stored in the storage card;

s2: power up the SOC chip 7;

s3: the SOC chip 7 detects the level state of each level detection pin to obtain the actual starting parameter of the SOC chip 7; and

s4: when the actual starting parameter is the same as a prestored comparison starting parameter, the SOC chip 7 selects to read the starting data in the storage card from the card reader 5 to start operation, otherwise, the SOC chip directly selects to read the starting data from the eMMC memory 3 connected with the SOC chip 7 to start operation, and the comparison starting parameter is obtained by converting the level state of each level sampling point B when the level of the level sampling point B connected with the insertion detection pin of the storage card is the second level.

In the present embodiment, by the above method, a level sampling point B is configured in each level configuration module 1 connected between an external power supply a and a ground terminal, and a storage card insertion detection pin of a card reader 5 is correspondingly connected with at least one level sampling point B, and since the storage card insertion detection pin is switched from a default first level to a second level when a storage card is inserted into the card reader 5, and the level detection pins of the SOC chip 7 are connected with the level sampling points B in a one-to-one correspondence manner, it is possible to adjust a level state of at least one level detection pin of the SOC chip 7 by whether the storage card is inserted into the card reader 5, and further adjust an actual start parameter, on one hand, the SOC chip 7 corresponds to a comparison start parameter corresponding to the level state of each level detection pin when the storage card is inserted into the card reader 5, and the comparison start parameter is a start parameter obtained by converting the level of the level sampling point connected with the storage card insertion detection pin to the level state of each level sampling point at the second level state of each level sampling point, so as to read the start operation data in the storage card via the card reader 5; on the other hand, the SOC chip 7 detects the level state of the pin according to the level when the memory card is not inserted into the card reader 5, so as to directly read the startup data in the built-in memory 50 to start up the operation, and further realize that the SOC chip 7 realizes different startup modes according to the insertion state of the memory card.

In addition, as shown in fig. 4, the vfat partition 30 and the boot partition 32 of the eMMC memory 3 both store the startup data, and when the actual startup parameter is different from the comparative startup parameter, the SOC chip 7 reads the startup data in the boot partition 32 of the eMMC memory 3 to start up the operation; when the actual start parameter is the same as the comparative start parameter and the start data in the memory card cannot be read for starting operation, the SOC chip 7 directly reads the start data in the vfat partition of the eMMC memory 3 for starting operation. In this embodiment, the boot data is respectively stored in the vfat partition 30 and the boot partition 32 of the eMMC memory 3, the vfat partition 30 has poor security, and the boot partition 32 is a read-only partition of the eMMC memory 3, when the actual boot parameters are different from the comparative boot parameters, that is, the memory card is not inserted, the boot partition 32 is used for booting, the security is relatively stronger, and when the actual boot parameters are the same as the comparative boot parameters and the boot data in the memory card cannot be read for booting, that is, the memory card is inserted into the memory card but the boot data is not stored in the memory card, the vfat partition 30 is used for booting at this time, so as to achieve effective booting of the SOC chip 7.

In addition, after the SOC chip 7 reads the startup data in the memory card to start up the operation, the SOC chip 7 further checks whether the startup data in the vfat partition 30 and the boot partition 32 of the eMMC memory 3 is damaged, and replaces the startup data in the vfat partition 30 and the boot partition 32 of the eMMC memory 3 with the startup data in the memory card when the startup data is judged to be damaged. In this embodiment, after the SOC chip 7 starts the operation by reading the startup data in the memory card, the startup data in the vfat partition 30 and the boot partition 32 of the eMMC memory 3 is checked, and when it is determined that the SOC chip is damaged, the startup data in the memory card is used to replace the startup data in the vfat partition 30 of the eMMC memory 3, so that the vfat partition 30 and the boot partition 32 of the eMMC memory 3 are automatically repaired, and the security of the system is improved. In a specific implementation, the boot partition 32 may be a boot1 partition or a boot2 partition of the eMMC storage 3.

The embodiments of the present invention have been described with reference to the accompanying drawings, but the present invention is not limited to the above-mentioned embodiments, which are only illustrative and not restrictive, and those skilled in the art can make many forms without departing from the spirit and scope of the present invention, and these forms are within the scope of the present invention.

Claims

1. An SOC chip circuit, the circuit comprising:

an eMMC memory in which startup data is stored;

the card reader is used for inserting a storage card with starting data stored inside, the card reader comprises a plurality of data reading pins and a storage card insertion detection pin which is switched from a default first level to a second level when the storage card is inserted into the card reader, and the storage card insertion detection pin is connected with at least one level sampling point; and

2. The SOC chip circuit of claim 1, wherein the card reader further comprises a CMD pin, a VDD pin, a CLK pin, and a GND pin, wherein:

the VDD pin is connected to an external power supply;

the CLK pin is connected to a clock pin of the SOC chip;

the GND pin is connected to a ground terminal.

3. The SOC chip circuit of claim 2, wherein the VDD pin is further connected to ground through a parallel connection of a first capacitor C1 and a second capacitor C2.

4. The SOC chip circuit according to claim 2, wherein the CMD pin, the CLK pin, the memory card insertion detection pin, and each of the data read pins are each connected to ground through an ESD protection diode, and to the external power source through a current limiting resistor.

5. The SOC chip circuit of claim 2, wherein each of the data reading pins is correspondingly connected to the card reading pin through a protection resistor, and the memory card insertion detection pin is also correspondingly connected to the state determination pin of the SOC chip through a protection resistor.

6. The SOC chip circuit of claim 1, wherein each of the level configuration modules comprises a pull-up resistor and a pull-down resistor connected in series, wherein the pull-up resistor is connected to an external power source, the pull-down resistor is connected to a ground terminal, and each level configuration module sets one of the level sampling points on a line between the pull-up resistor and the pull-down resistor.

7. The SOC chip circuit of claim 1, wherein the SOC chip further comprises a parameter storage register for storing the actual startup parameter.