CN217606001U - Current test system of sample chip - Google Patents
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- CN217606001U CN217606001U CN202220982762.6U CN202220982762U CN217606001U CN 217606001 U CN217606001 U CN 217606001U CN 202220982762 U CN202220982762 U CN 202220982762U CN 217606001 U CN217606001 U CN 217606001U
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Abstract
The embodiment of the utility model discloses sample chip's current test system, this system includes: the system comprises a main control terminal, a cascade unit in communication connection with the main control terminal and a plurality of test units in communication connection with the cascade unit; the main control terminal is used for issuing a sampling instruction and processing data of the sampling current; the cascade unit comprises a plurality of sub-controllers; a plurality of sub-controllers are connected in cascade to expand the number of test channels; each test unit is provided with a plurality of mutually independent test channels and is used for obtaining the sampling current of the sample chip positioned in the test channels; the sampling instruction issued by the main control terminal is transmitted to the corresponding test unit through the cascade unit; and the sampling current is transmitted to the main control terminal through the cascade unit for data processing. In this way, the utility model discloses can be at the consumption that burns the stage and test sample chip in batches, avoid the bad sample chip that the electric current exceeds standard to get into next production stage, reduced the rework cost.
Description
Technical Field
The embodiment of the utility model provides a relate to chip test field, especially relate to a current test system of sample chip.
Background
Before and after the chip packaging is completed, the related electrical characteristic functions of the chip need to be tested. However, when a program maker burns a PCBA or burns a chip, the power consumption (current) of the chip is not usually tested in the burning stage, which may cause a part of the chips with excessive power consumption to flow into the next production link, and the problem is discovered only in the finished product test, thereby finally increasing the rework cost. Therefore, it is necessary to increase the power consumption screening test of the chip during the burning stage.
SUMMERY OF THE UTILITY MODEL
In order to solve the technical problem, the utility model discloses a technical scheme be: provided is a current test system of a sample chip, including: the system comprises a main control terminal, a cascading unit in communication connection with the main control terminal and a plurality of testing units in communication connection with the cascading unit; the main control terminal is used for issuing a sampling instruction and processing data of the sampling current; the cascade unit comprises a plurality of sub-controllers; a plurality of the sub-controllers are connected in cascade to expand the number of the test channels; each test unit is provided with a plurality of mutually independent test channels and is used for obtaining sampling current of a sample chip positioned in each test channel; the sampling instruction issued by the main control terminal is transmitted to the corresponding test unit through the cascade unit; and the sampling current is transmitted to the main control terminal through the cascade unit for data processing.
In some embodiments, the cascade unit comprises: a first sub-controller, a second sub-controller, and a third sub-controller; wherein the first sub-controller is cascaded with four second sub-controllers; each second sub-controller is cascaded with two third sub-controllers; the first sub-controllers are in communication connection with the main control terminal, and each third sub-controller is in communication connection with one test unit.
In some embodiments, each of the test units comprises: a sampling circuit and a plurality of mutually independent power supply circuits; the sampling circuit is used for acquiring the sampling current of the sample chip.
In some embodiments, the power supply circuit comprises: the voltage stabilizing circuit comprises a first switching tube, a voltage stabilizing chip, a first resistor, a second resistor, a third resistor, a first capacitor and a second capacitor, wherein the first end of the voltage stabilizing chip is connected to the output end of an input power supply and one end of the first capacitor respectively, and the second end of the first capacitor is grounded; the second end of the voltage stabilizing chip is grounded; a fifth end of the voltage stabilizing chip is an output end and is respectively connected to a first end of the first resistor and a first end of the second capacitor, a second end of the second capacitor is grounded, a second end of the first resistor is respectively connected to a first end of the second resistor and a first end of the third resistor, a second end of the second resistor is connected to a drain electrode of the first switch tube, and a second end of the third resistor is grounded; the fourth end of the voltage stabilizing chip is connected to a first connecting node formed by connecting the first resistor and the second resistor; the source electrode of the first switch tube is grounded; and the grid electrode of the first switching tube is used for receiving a power supply control signal.
In some embodiments, the fifth terminal of the voltage regulation chip outputs a first voltage when the first switch tube is turned on; when the first switch tube is cut off, the fifth end of the voltage stabilizing chip outputs a second voltage.
In some embodiments, the sampling circuit is a sampling resistance based current sampling circuit; wherein the resistance value of the sampling resistor is variable.
In some embodiments, the sampling circuit comprises: the sampling circuit comprises a sampling chip, a second switching tube, a third switching tube, a fourth resistor, a fifth resistor and a sixth resistor, wherein the source electrode of the second switching tube is respectively connected to the first end of the fourth resistor and the output end of a power supply circuit, and the grid electrode of the second switching tube is respectively connected to the second end of the fourth resistor and the collector electrode of the third switching tube; the emitter of the third switching tube is grounded; the drain electrode of the second switch tube is connected to the first end of the fifth resistor, and the second end of the fifth resistor is respectively connected to the first end of the sixth resistor and the sampling chip; and the second end of the sixth resistor is respectively connected to the output end of the power supply circuit and the sampling chip.
In some embodiments, when the fifth terminal of the voltage regulation chip outputs the second voltage, the sampling circuit further includes: the first end of the seventh resistor is connected to the first end of the sixth resistor, the second end of the seventh resistor is connected to the drain electrode of the fourth switch tube, and the source electrode of the fourth switch tube is grounded.
In some embodiments, when the output current of the power supply circuit is less than 1mA, the base of the third switching tube is at a low level, the second switching tube is turned off, and the sampling resistor is the resistance of the sixth resistor; when the output current of the power supply circuit is not less than 1mA, the base of the third switching tube is at a high level, the second switching tube is conducted, and the sampling resistor is the parallel resistance of the sixth resistor and the seventh resistor.
In some embodiments, when the gate of the fourth switching tube is at a high level, the fourth switching tube is turned on, the seventh resistor is a load of a sample chip, and the sampling current is a charging current of the sample chip; when the grid electrode of the fourth switching tube is at a low level, the fourth switching tube is cut off, and the sample chip has no load.
The embodiment of the utility model provides a beneficial effect is: be different from prior art's condition, the embodiment of the utility model provides a can be at the consumption that burns the stage and test sample chip in batches, avoided the bad sample chip that the electric current exceeds standard to get into next production stage, reduced the rework cost.
Drawings
Fig. 1 is a flow chart illustrating a structure of a current testing circuit of a sample chip according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a current testing system of a sample chip according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a test unit according to an embodiment of the present invention;
fig. 4 is a hardware structure diagram of a power supply circuit according to an embodiment of the present invention;
fig. 5 is a hardware structure diagram of a sampling circuit according to an embodiment of the present invention;
fig. 6 is a hardware structure diagram of a sampling circuit when the power supply voltage is 5V according to the embodiment of the present invention;
fig. 7 is a hardware configuration diagram of a sampling circuit according to an embodiment of the present invention when the power supply voltage is 4.2V.
Detailed Description
To facilitate understanding of the present invention, the present invention will be described in more detail with reference to the accompanying drawings and specific embodiments. It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for descriptive purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1, fig. 1 is a flow chart of a structure of a current testing circuit of a sample chip according to an embodiment of the present invention, the circuit includes: a first sub-controller 210, a second sub-controller 220, a third sub-controller 230, and a test unit 300. The first sub-controllers 210 are respectively connected to the 4 second sub-controllers 220 in a serial communication manner, each second sub-controller 220 is respectively connected to two third sub-controllers 230 in a serial communication manner, and each third sub-controller 230 is connected to the test unit 300 in an I2C communication manner.
I2C Bus (Inter-Integrated Circuit Bus) is a simple, bi-directional two-wire synchronous serial Bus commonly used for connection between microcontrollers and peripheral devices. I2C only needs two lines to support one master-multiple slave or multiple master connection, and I2C uses two bidirectional open drain lines, namely an SDA (serial data line) and an SCL (serial clock line), to be matched with a pull-up resistor for connection. The SDA (serial data line) and the SCL (serial clock line) are both bidirectional I/O lines, and the interface circuit is an open-drain output. The power source VCC is connected through a pull-up resistor. When the bus is idle, both lines are high level, the same devices connected with the bus are CMOS devices, and the output stage is also an open drain circuit. The current consumed on the bus is small and therefore the number of devices that extend on the bus is determined primarily by the capacitive load, since each device has a bus interface with a certain equivalent capacitance. The capacitance in the line affects the bus transmission speed. When the capacitance is too large, transmission errors may be caused. Therefore, the load capacity is 400pF, so that the allowable length of the bus and the number of connected devices can be estimated.
Specifically, the first sub-controllers 210 are configured to receive an external sampling signal and transmit the sampling signal to each of the second sub-controllers 220, and each of the second sub-controllers 220 transmits the sampling signal to each of the third sub-controllers 230. After receiving the sampling signal, each third sub-controller 230 controls each test unit 330 to sample the current of the sample chip through the I2C protocol, and transmits the sampled current to the second sub-controller 220 connected thereto. The second sub-controller 220 receives the sampled current and transmits it to the first sub-controller 210 connected thereto. And finally, the data is transmitted to the outside by the first sub-controller 210 for data processing, so that whether the power consumption (current) of the sample chip exceeds the standard or not is analyzed.
In some embodiments, the first sub-controller 210 is an AB5301 chip;
in some embodiments, the second sub-controller 220 is an AB5301 chip;
in some embodiments, the third sub-controller 230 is an AB5312 chip.
Referring to fig. 2, fig. 2 is a flow chart illustrating a structure of a current testing system for a sample chip according to an embodiment of the present invention, the system includes a main control terminal 100, a first sub-controller 210, a second sub-controller 220, a third sub-controller 230, and a testing unit 300. The main control terminal 100 is connected to the first sub-controllers 210 in a serial port communication manner, the first sub-controllers 210 are connected to the 4 second sub-controllers 220 in a serial port communication manner, each second sub-controller 220 is connected to two third sub-controllers 230 in a serial port communication manner, and each third sub-controller 230 is connected to the test unit 300 in an I2C communication manner.
In some embodiments, master control terminal 100 is a computer.
Specifically, the main control terminal 100 issues a sampling instruction to the first sub-controllers 210 through the upper computer software, the first sub-controllers 210 receive the sampling instruction and transmit the sampling signal to each of the second sub-controllers 220, and each of the second sub-controllers 220 transmits the sampling signal to each of the third sub-controllers 230. After receiving the sampling signal, each third sub-controller 230 controls each test unit 330 to sample the current of the sample chip through the I2C protocol, and transmits the sampled current to the second sub-controller 220 connected thereto. The second sub-controller 220 receives the sampled current and transmits it to the first sub-controller 210 connected thereto. And finally, the data is transmitted to the main control terminal 100 by the first sub-controller 210 for data processing, so that whether the power consumption (current) of the sample chip exceeds the standard or not is analyzed.
It should be noted that the current test circuits of two sample chips or the current test circuits of three sample chips may be connected through the main control terminal 100 to form a current test system of a sample chip. Wherein the main control terminal 100 is respectively connected to the first sub-controllers 210 of the respective current test circuits.
Different from the prior art, the method and the device can test the power consumption of the sample chips in batch in the burning stage, avoid the bad sample chips with over-standard current from entering the next production stage, and reduce the rework cost.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a testing unit 300 according to an embodiment of the present invention, the testing unit includes: the sampling circuit comprises a sampling chip 310, three mutually independent sampling circuits 320 and three mutually independent power supply circuits 330, wherein the sampling chip 310 is respectively connected to the three sampling circuits 320, and each sampling circuit 320 is respectively connected to one power supply circuit 330.
Specifically, the power supply circuit 330 provides a current to be sampled, and the power supply circuit 330 is connected to the sampling circuit 320. The sampling chip 310 is connected to the sampling circuit 320, and the sampling chip 310 controls the sampling circuit 320 to obtain the sampling current under the control of the sampling instruction.
In some embodiments, the sampling chip 310 is an INA3221 chip.
Referring to fig. 4, fig. 4 is a hardware structure diagram of a power supply circuit according to an embodiment of the present invention, where the power supply circuit 330 includes: a first switch tube Q1, a voltage stabilizing chip U1, a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1 and a second capacitor C2, wherein,
the first end of the voltage stabilizing chip U1 is respectively connected to the output end of an input power supply and one end of a first capacitor C1, and the second end of the first capacitor C1 is grounded; the second end of the voltage stabilizing chip U1 is grounded;
in some embodiments, the output of the input power supply outputs a voltage of 5.5V.
The fifth end of the voltage stabilizing chip U1 is an output end, and is connected to the first end of the first resistor R1 and the first end of the second capacitor C2, respectively, the second end of the second capacitor C2 is grounded, the second end of the first resistor R1 is connected to the first end of the second resistor R2 and the first end of the third resistor R3, respectively, the second end of the second resistor R2 is connected to the drain of the first switch tube Q1, and the second end of the third resistor R3 is grounded;
the fourth end of the voltage stabilizing chip U1 is connected to a first connecting node formed by connecting the first resistor R1 and the second resistor R2; the source electrode of the first switch tube Q1 is grounded; the grid electrode of the first switch tube Q1 is used for receiving a power supply control signal.
And the third end of the voltage stabilizing chip U1 is connected with a pull-down resistor by default.
In some embodiments, the pull-down resistor has a resistance of 10k ohms.
In some embodiments, the voltage regulator chip U1 has a model number AP2127K-ADJ.
In some embodiments, the first resistor R1 and the second resistor R2 each have a resistance of 10k ohms, the third resistor R3 has a resistance of 2.32k ohms, and the first capacitor C1 and the second capacitor C2 each have a capacitance of 1uF.
In some embodiments, the gate level of the first switch Q1 is controlled to be high or low by the power supply control signal, so as to control the on or off of the first switch Q1. When the grid electrode of the first switch tube Q1 is at a high level, the first switch tube Q1 is turned on, and the fifth end of the voltage stabilizing chip U11 outputs a first voltage, wherein the first voltage is 5V; when the grid of the first switching tube Q1 is at a low level, the first switching tube Q1 is turned off, and the fifth end of the voltage stabilizing chip U1 outputs a second voltage, where the second voltage is 4.2V.
Referring to fig. 5, fig. 5 is a hardware structure diagram of a sampling circuit according to an embodiment of the present invention, the sampling circuit 320 includes: a second switch tube Q2, a third switch tube Q3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6, wherein,
the source of the second switching tube Q2 is connected to the first end of the fourth resistor R4 and the output end of the power supply circuit 330, respectively, and the gate of the second switching tube Q2 is connected to the second end of the fourth resistor R4 and the collector of the third switching tube Q3, respectively; the emitter of the third switching tube Q3 is grounded;
in some embodiments, the base of the third transistor Q3 is internally configured with a pull-down resistor with a resistance of 10k ohms by default;
the drain electrode of the second switching tube Q2 is connected to a first end of a fifth resistor R5, and a second end of the fifth resistor R5 is connected to a first end of a sixth resistor R6 and the sample chip, respectively;
a second end of the sixth resistor R6 is connected to the output end of the power supply circuit 330 and the sampling chip 310, respectively.
In some embodiments, when the output current of the power supply circuit 330 is less than 1mA, the base of the third switching tube Q3 is set to a low level, the second switching tube Q2 is turned off, and the sampling resistor is the resistance of the sixth resistor R6;
when the output current of the power supply circuit 330 is not less than 1mA, the base of the third switching tube is at a high level, the second switching tube is turned on, and the sampling resistor is a parallel resistance of the sixth resistor and the seventh resistor. The resistance value of the sampling resistor is changed by controlling the base level of the third switching tube Q3, so that the working current, the standby current and the shutdown current of the sample chip are tested.
Referring to fig. 6, fig. 6 is a hardware structure diagram of a sampling circuit when the power supply voltage is 5V according to an embodiment of the present invention, where the sampling circuit 320 includes: a second switching tube Q2, a third switching tube Q3 and a fourth resistor R4, wherein a source electrode of the second switching tube Q2 is connected to a first end of the fourth resistor R4 and an output end of the power supply circuit 330, respectively, a gate electrode of the second switching tube Q2 is connected to a second end of the fourth resistor R4 and a collector electrode of the third switching tube Q3, respectively, and a drain electrode of the second switching tube Q2 is connected to the sample chip; the emitter of the third switching tube Q3 is grounded;
it should be noted that, when the voltage regulation chip U1 of the power supply circuit outputs the second voltage, i.e. 4.2V, the sampling circuit adopts the circuit shown in fig. 6.
In some embodiments, the base of the third transistor Q3 is internally configured with a pull-down resistor with a resistance of 10k ohms by default;
referring to fig. 7, fig. 7 is a hardware structure diagram of a sampling circuit when the power supply voltage is 4.2V according to an embodiment of the present invention, where the sampling circuit 320 includes: a second switching tube Q2, a third switching tube Q3, a fourth switching tube Q4, a fourth resistor R4, and a seventh resistor R7, wherein a source of the second switching tube Q2 is connected to a first end of the fourth resistor R4 and an output end of the power supply circuit 330, respectively, and a gate of the second switching tube Q2 is connected to a second end of the fourth resistor R4 and a collector of the third switching tube Q3, respectively; the emitter of the third switching tube Q3 is grounded;
it should be noted that, when the voltage regulation chip U1 of the power supply circuit outputs the first voltage, i.e., 5V, the sampling circuit adopts the circuit shown in fig. 7.
In some embodiments, the base of the third transistor Q3 is internally configured with a pull-down resistor with a resistance of 10k ohms by default;
the drain electrode of the second switch tube Q2 is connected to the first end of the seventh resistor R7 and the sample chip, the second end of the seventh resistor R7 is connected to the drain electrode of the fourth switch tube Q4, and the source electrode of the fourth switch tube Q4 is grounded.
In some embodiments, the gate of the fourth switching transistor Q4 is internally configured with a pull-down resistor with a resistance of 10k ohms by default.
In some embodiments, when the gate of the fourth switching tube Q4 is at a high level, the fourth switching tube Q4 is turned on, the seventh resistor R7 is a load of the sample chip, and the sampling current is a charging current of the sample chip; when the gate of the fourth switching tube Q4 is at a low level, the fourth switching tube Q4 is turned off, and the sample chip has no load. By controlling the high and low levels of the grid electrode of the fourth switching tube Q4, the magnitude of the charging current of the sample chip can be tested when the sample chip is connected into a load.
It should be noted that the preferred embodiments of the present invention are described in the specification and the drawings, but the present invention can be realized in many different forms, and is not limited to the embodiments described in the specification, and these embodiments are not provided as additional limitations to the present invention, and are provided for the purpose of making the understanding of the disclosure of the present invention more thorough and complete. Moreover, the above technical features are combined with each other to form various embodiments which are not listed above, and all the embodiments are regarded as the scope of the present invention; further, modifications and variations will occur to those skilled in the art in light of the foregoing description, and it is intended to cover all such modifications and variations as fall within the true spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A current testing system for a sample chip, comprising: the device comprises a main control terminal, a cascade unit in communication connection with the main control terminal and a plurality of test units in communication connection with the cascade unit;
the main control terminal is used for issuing a sampling instruction and processing data of the sampling current;
the cascade unit comprises a plurality of sub-controllers; a plurality of the sub-controllers are connected in cascade to expand the number of the test channels;
each test unit is provided with a plurality of mutually independent test channels and is used for obtaining sampling current of a sample chip positioned in each test channel;
the sampling instruction issued by the main control terminal is transmitted to the corresponding test unit through the cascade unit; and the sampling current is transmitted to the main control terminal through the cascade unit for data processing.
2. The test system of claim 1, wherein the cascade unit comprises: a first sub-controller, a second sub-controller and a third sub-controller;
wherein the first sub-controller is cascaded with four second sub-controllers; each second sub-controller is cascaded with two third sub-controllers;
the first sub-controllers are in communication connection with the main control terminal, and each third self-controller is in communication connection with one test unit.
3. The test system of claim 1, wherein each of the test units comprises: the device comprises a sampling chip, a plurality of mutually independent sampling circuits and a plurality of mutually independent power supply circuits;
and the sampling circuit is used for acquiring the sampling current of the sample chip.
4. The test system of claim 3, wherein the power supply circuit comprises: a first switch tube, a voltage stabilizing chip, a first resistor, a second resistor, a third resistor, a first capacitor and a second capacitor, wherein,
the first end of the voltage stabilizing chip is respectively connected to the output end of an input power supply and one end of the first capacitor, and the second end of the first capacitor is grounded;
the second end of the voltage stabilizing chip is grounded;
a fifth end of the voltage stabilizing chip is an output end and is respectively connected to a first end of the first resistor and a first end of the second capacitor, a second end of the second capacitor is grounded, a second end of the first resistor is respectively connected to a first end of the second resistor and a first end of the third resistor, a second end of the second resistor is connected to a drain electrode of the first switch tube, and a second end of the third resistor is grounded;
a fourth end of the voltage stabilizing chip is connected to a first connecting node formed by connecting the first resistor and the second resistor;
the source electrode of the first switch tube is grounded;
and the grid electrode of the first switching tube is used for receiving a power supply control signal.
5. The test system of claim 4, wherein:
when the first switch tube is conducted, a fifth end of the voltage stabilizing chip outputs a first voltage;
when the first switch tube is cut off, the fifth end of the voltage stabilizing chip outputs a second voltage.
6. The test system of claim 3, wherein the sampling circuit is a sampling resistance based current sampling circuit;
wherein the resistance value of the sampling resistor is variable.
7. The test system of claim 3, wherein the sampling circuit comprises: a second switch tube, a third switch tube, a fourth resistor, a fifth resistor and a sixth resistor, wherein,
the source electrode of the second switching tube is respectively connected to the first end of the fourth resistor and the output end of the power supply circuit, and the grid electrode of the second switching tube is respectively connected to the second end of the fourth resistor and the collector electrode of the third switching tube;
the emitter of the third switching tube is grounded;
the drain electrode of the second switching tube is connected to the first end of the fifth resistor, and the second end of the fifth resistor is respectively connected to the first end of the sixth resistor and the sampling chip;
and the second end of the sixth resistor is respectively connected to the output end of the power supply circuit and the sampling chip.
8. The test system of claim 7, wherein when the fifth terminal of the regulator chip outputs the second voltage, the sampling circuit further comprises: a fourth switching tube and a seventh resistor, wherein,
the first end of the seventh resistor is connected to the first end of the sixth resistor, the second end of the seventh resistor is connected to the drain electrode of the fourth switching tube, and the source electrode of the fourth switching tube is grounded.
9. The test system of claim 8, wherein when the output current of the power supply circuit is less than 1mA, the base of the third switching tube is at a low level, the second switching tube is turned off, and the sampling resistor is the resistance of the sixth resistor;
when the output current of the power supply circuit is not less than 1mA, the base of the third switching tube is at a high level, the second switching tube is conducted, and the sampling resistor is the parallel resistance of the sixth resistor and the seventh resistor.
10. The test system of claim 9, wherein when the gate of the fourth switching tube is at a high level, the fourth switching tube is turned on, the seventh resistor is a load of a sample chip, and the sampling current is a charging current of the sample chip;
when the grid electrode of the fourth switching tube is at a low level, the fourth switching tube is cut off, and the sample chip has no load.
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