CN217588852U - Bump package structure - Google Patents

Abstract

An embodiment of the utility model provides a lug packaging structure relates to semiconductor package technical field, and lug packaging structure includes chip, weld pad, protective layer, basement conducting layer, first combination conducting layer, leads electrical pillar and welds the cap, and wherein, the basement conducting layer includes multilayer graphene structure. Compared with the prior art, the utility model provides a lug packaging structure and preparation method thereof, graphite alkene is filled in the protection opening to cover the protection opening, its undercut opening that can avoid appearing transition corrosion formation, the structure is more stable simultaneously, has avoided the problem that the electrode atress splits, and dispels the heat, the equal preferred of electric conductive property, has effectively alleviated the potential failure hazard that electromigration and thermophoresis brought.

Description

Bump package structure

Technical Field

The utility model relates to a semiconductor package technical field particularly, relates to a lug packaging structure and.

Background

With the rapid development of the semiconductor industry, the flip chip package structure is widely applied to the semiconductor industry, and the flip chip package utilizes the bumps to electrically connect the chip and the substrate. The bump comprises a copper column, a metal layer (UBM), a protective layer (Polyimide), and a tin Cap (Sn Cap), wherein after the UBM is manufactured, the redundant metal layer needs to be etched and removed. The bottom of the copper pillar bump in the prior art is completely connected with the chip electrode, so that the stress on the copper pillar bump directly acts on the chip electrode, and the problem of chip electrode cracking exists. And under the condition that the copper column lug is subjected to current, due to joule heat effect, metal atoms at the connecting part at the bottom of the copper column bear the influence of an electric field and a thermal field simultaneously, and the electromigration and the thermomigration of an interconnection interface can cause the service life of the interconnection interface to be remarkably reduced due to abnormal activity, thereby causing potential failure hidden danger.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a preparation method of lug packaging structure and lug packaging structure, its undercut opening that can avoid appearing transition corrosion formation, the structure is more stable simultaneously, has avoided the problem that the electrode atress cracked, and dispels the heat, the equal preferred of electric conductive property has effectively alleviated the potential failure hazard that electromigration and thermophoresis brought.

The embodiment of the utility model discloses a can realize like this:

in a first aspect, the present invention provides a bump package structure, including:

the chip comprises a chip, wherein one side of the chip is provided with a welding pad;

the protective layer is arranged on one side of the chip, and a protective opening corresponding to the welding pad is formed in the protective layer;

a base conductive layer disposed in the protective opening;

a first combined conductive layer disposed on the base conductive layer;

a conductive post disposed on the first combined conductive layer;

and a solder cap disposed on the conductive post;

wherein the base conductive layer comprises a multi-layered graphene structure.

In an optional embodiment, the height of the base conductive layer is greater than the depth of the protection opening, and a shielding portion is disposed on the top of the base conductive layer, and the shielding portion extends from the center of the protection opening to the surface of the protection layer and covers the edge of the protection opening.

In an alternative embodiment, the thickness of the shielding is 4-8 μm.

In an optional implementation manner, the first combined conductive layer includes an adhesive layer, a barrier layer, and an infiltration layer, the adhesive layer is disposed on one side of the substrate conductive layer away from the chip, the barrier layer is disposed on one side of the adhesive layer away from the chip, the infiltration layer is disposed on one side of the barrier layer away from the chip, the conductive post is disposed on one side of the infiltration layer away from the chip, the adhesive layer is in contact with the barrier layer and the substrate conductive layer at the same time, so as to improve the adhesion between the barrier layer and the substrate conductive layer, and the infiltration layer is in contact with the barrier layer and the conductive post at the same time, so as to improve the wettability between the barrier layer and the conductive post.

In an optional implementation manner, a surface of one side of the base conductive layer, which is away from the chip, is a flat surface, the adhesive layer covers the surface of the base conductive layer, the barrier layer covers the surface of the base conductive layer, the wetting layer covers the surface of the barrier layer, and at least part of a surface of one side of the adhesive layer, which is away from the chip, is an outward convex arc surface, so that the adhesive layer forms an arc-shaped bump structure.

In an optional embodiment, at least a part of a side surface of the base conductive layer away from the chip is an outward convex arc surface, so that the base conductive layer forms an arc-shaped bump structure, the adhesive layer is arranged at a periphery of the base conductive layer, the barrier layer covers surfaces of the base conductive layer and the adhesive layer, and the wetting layer covers a surface of the barrier layer.

In an optional embodiment, a receiving groove is formed at a periphery of the base conductive layer, the adhesive layer is disposed in the receiving groove, and a thickness of the adhesive layer is the same as a depth of the receiving groove.

In an optional implementation manner, at least a part of a side surface of the base conductive layer away from the chip is an outward convex arc surface, so that the base conductive layer forms an arc-shaped bump structure, the adhesive layer covers the surface of the base conductive layer, the barrier layer covers the surface of the adhesive layer, and the wetting layer covers the surface of the barrier layer.

In an alternative embodiment, a surface of the adhesion layer on a side away from the chip is a flat plane, so that the barrier layer and the wetting layer are planarized.

In an optional embodiment, the base conductive layer includes a first base layer, a second base layer and a third base layer, the first base layer is disposed in the protection opening, the second base layer is disposed on the first base layer, the third base layer is disposed on the second base layer, a side surface of the first base layer, which is away from the chip, is at least partially convex, an arc surface, a side surface of the second base layer, which is away from the chip, is a flat surface, a side surface of the third base layer, which is away from the chip, is at least partially convex, and the first combined conductive layer is disposed on the third base layer.

In an alternative embodiment, the first and third substrate layers each comprise a multilayer graphene structure, the second substrate layer comprises a titanium layer, and the second substrate layer has a titanium carbide layer formed at both side interfaces thereof.

In an alternative embodiment, the first and third substrate layers each comprise a titanium layer, the second substrate layer comprises a multilayer graphene structure, and the second substrate layer has a titanium carbide layer formed at both side interfaces thereof.

In an alternative embodiment, a second combined conductive layer is further disposed on a side of the conductive pillar away from the chip, and the second combined conductive layer is disposed between the conductive pillar and the solder cap.

In an alternative embodiment, the second combined conductive layer includes a first conductive layer and a second conductive layer, the first conductive layer covers the surface of the conductive pillar, the second conductive layer covers the first conductive layer, the solder cap covers the second conductive layer, the second conductive layer is used for blocking atomic diffusion between the solder cap and the conductive pillar, and the first conductive layer is used for improving adhesion between the second conductive layer and the conductive pillar.

In an optional embodiment, a side surface of the conductive pillar away from the chip is at least partially an outer convex arc surface, so that the conductive pillar forms an arc-shaped bump structure.

In a second aspect, the present invention provides a method for manufacturing a bump package structure, for manufacturing the bump package structure according to any one of the foregoing embodiments, the method comprising:

providing a chip with a welding pad;

forming a protective layer on one side of the chip with the welding pad;

forming a groove on the protective layer to form a protective opening corresponding to the welding pad;

forming a base conductive layer in the protection opening;

forming a first combined conductive layer on the base conductive layer;

forming a conductive post on the first combined conductive layer;

forming a solder cap on the conductive post;

wherein the base conductive layer comprises a multi-layered graphene structure.

The utility model discloses beneficial effect includes, for example:

the utility model provides a lug packaging structure and preparation method thereof, it at first forms the protection opening on the protective layer, then sets up the basement conducting layer in the protection opening, sets gradually first combination conducting layer again, leads electrical pillar and welds the cap. The substrate conducting layer comprises a plurality of layers of graphene structures, and the graphene is filled in the protective opening and covers the protective opening, so that the stability and the hydrophobicity of the bottom structure can be enhanced by using the plurality of layers of graphene structures, and when the micro-etching process is carried out, the substrate conducting layer can avoid the undercut problem caused when the UBM layer is removed by the traditional micro-etching process no matter a chemical etching mode or a plasma etching mode is adopted. Moreover, the coefficient of thermal expansion CTE of the graphene material is only 1/10-1/20 of that of copper and aluminum, so that the UBM layer at the bottom of the conductive column can be better prevented from deforming, and a bonding pad at the bottom and a metal structure at the bottom of the conductive column can be protected. The electric conductivity of graphite alkene material is higher than the metal far away to the thermal conductivity is superior, and along with the multilayer graphite alkene structure that graphite alkene increase in size formed, its thermal conductivity and thermal conductivity further promote, have promoted its electric conductivity and heat dispersion by a wide margin, avoid electromigration and thermophoresis can make the life-span of copper post lug show to reduce because of unusual flourishing, and cause the problem of potential inefficacy hidden danger. Meanwhile, the problem that a brittle material layer is damaged due to the fact that a copper column can cause large stress in a packaging body in the traditional technology is solved by utilizing the stability of the graphene, for example, a chip bonding pad at the bottom of the copper column is broken, a UBM metal layer is layered or the fatigue life of a welding spot is reduced, and therefore the stability of the structure is guaranteed. Compared with the prior art, the utility model provides a lug packaging structure and preparation method thereof, it can avoid appearing the undercut opening that transition corrosion formed, and the structure is more stable simultaneously, has avoided the problem that the electrode atress cracked, and heat dissipation, electric conductive property all preferred, has effectively alleviated the potential failure hazard that electromigration and thermophoresis brought.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on these drawings without inventive efforts.

Fig. 1 is a schematic overall view of a bump package structure according to a first embodiment of the present invention;

fig. 2 is a partial schematic view of a bump package structure according to a first embodiment of the present invention;

fig. 3 to fig. 8 are process flow diagrams of a method for manufacturing a bump package structure according to a first embodiment of the present invention;

fig. 9 is a schematic overall view of a bump package structure according to a second embodiment of the present invention;

FIG. 10 is an enlarged partial view of X in FIG. 9;

fig. 11 is an overall schematic view of a bump package structure according to a third embodiment of the present invention;

fig. 12 is a schematic overall view of a bump package structure according to a fourth embodiment of the present invention;

FIG. 13 is a partially enlarged view of XII in FIG. 12;

fig. 14 is an overall schematic view of a bump package structure according to a fifth embodiment of the present invention.

Icon: 100-bump package structure; 110-chip; 120-a bond pad; 130-a protective layer; 131-a protective opening; 140-a base conductive layer; 141-a first base layer; 143-a second substrate layer; 145-a third substrate layer; 150-a first combined conductive layer; 151-an adhesive layer; 153-a barrier layer; 155-a wetting layer; 157-an accommodating recess; 160-conductive column; 170-welding a cap; 180-a second combined conductive layer; 181 — a first conductive layer; 183-second conductive layer.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

In the description of the present invention, it should be noted that, if the directions or positional relationships indicated by the terms "up", "down", "inside", "outside", etc. appear based on the directions or positional relationships shown in the drawings, or the directions or positional relationships that the products of the present invention are usually placed when used, it is only for convenience of describing the present invention and simplifying the description, but not for indicating or implying that the indicated device or element must have a specific direction, be constructed and operated in a specific direction, and therefore, should not be construed as limiting the present invention.

Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.

As disclosed in the background art, when a metal layer UBM is formed in the prior art, since the material of the protection layer is easy to absorb water, etching solution residue is easy to occur on the side wall of the UBM at the bottom of the metal column, and the etching solution is excessively corroded at the moment, so that the undercut opening phenomenon is easy to occur at the bottom of a copper column bump, and the structural strength of the copper column is further influenced, and the copper column bump is easy to fall off. In addition, in the prior art, the bottom of the copper pillar bump is completely connected with the chip electrode, and the contact interface is usually metal-metal contact, so that the stress on the copper pillar bump directly acts on the chip electrode, and the chip electrode cracks. In addition, under the condition that the copper pillar bump is subjected to current, due to joule heat effect, metal atoms at the connection position of the bottom of the copper pillar bear the influence of an electric field and a thermal field at the same time, and the electromigration and the thermomigration of an interconnection interface can cause the service life of the interconnection interface to be remarkably reduced due to abnormal activity, so that potential failure hidden danger is caused.

In order to solve the above problem, the present invention provides a manufacturing method of a bump package structure and a bump package structure, which needs to be described that features in the embodiments of the present invention can be combined with each other under the non-conflicting condition.

First embodiment

Referring to fig. 1 and fig. 2, the present embodiment provides a bump package structure 100, which can avoid an undercut opening formed by transition corrosion, has a more stable structure, avoids the problem of stress cracking of an electrode, has better heat dissipation and electrical conductivity, and effectively alleviates the hidden failure danger caused by electromigration and thermomigration.

The bump package structure 100 provided by this embodiment includes a chip 110, a pad 120, a protection layer 130, a base conductive layer 140, a first combined conductive layer 150, a conductive pillar 160, and a solder cap 170, where the pad 120 is disposed on one side of the chip 110 and electrically connected to a circuit layer inside the chip 110, the protection layer 130 is disposed on one side of the chip 110 having the pad 120, and is provided with a protection opening 131 corresponding to the pad 120, and the size of the protection opening 131 is slightly smaller than that of the pad 120, so that the pad 120 is partially exposed to the protection layer 130. The base conductive layer 140 is disposed in the opening and covers the protection opening 131, the first combined conductive layer 150 is disposed on the base conductive layer 140, the conductive pillar 160 is disposed on the first combined conductive layer 150, and the solder cap 170 is disposed on the conductive pillar 160, wherein the base conductive layer 140 includes a multi-layer graphene structure.

In the bump package structure 100 provided by the present embodiment, the protection opening 131 is formed on the protection layer 130, the base conductive layer 140 is disposed in the protection opening 131, and the first combined conductive layer 150, the conductive pillar 160 and the solder cap 170 are sequentially disposed. The substrate conductive layer 140 includes a multi-layer graphene structure, and since the graphene is filled in the protection opening 131 and covers the protection opening 131, the multi-layer graphene structure can enhance the stability and hydrophobicity of the bottom structure, and when the micro-etching process is performed, the substrate conductive layer 140 can avoid the undercut problem caused when the UBM layer is removed by the conventional micro-etching process, no matter a chemical etching method or a plasma etching method is used. Moreover, the coefficient of thermal expansion CTE of the graphene material is only 1/10-1/20 of copper and aluminum, so that deformation of the UBM layer at the bottom of the conductive pillar 160 can be better avoided, and the bottom pad 120 and the metal structure at the bottom of the conductive pillar 160 can be protected. The electric conductivity of graphite alkene material is higher than the metal far away to the thermal conductivity is superior, and along with the multilayer graphite alkene structure that graphite alkene increase in size formed, its thermal conductivity and thermal conductivity further promote, have promoted its electric conductivity and heat dispersion by a wide margin, avoid electromigration and thermophoresis can make the life-span of copper post lug show to reduce because of unusual flourishing, and cause the problem of potential inefficacy hidden danger. Meanwhile, the problem that a brittle material layer is damaged due to the fact that a copper column causes large stress in a packaging body in the prior art is solved by utilizing the stability of the graphene, for example, a bonding pad of a chip 110 at the bottom of the copper column is broken, a UBM metal layer is layered or the fatigue life of a welding spot is reduced, and therefore the structural stability is guaranteed.

In this embodiment, the pad 120 is an aluminum pad 120, the height of the base conductive layer 140 is greater than the depth of the protection opening 131, and a shielding portion is disposed on the top of the base conductive layer 140, the shielding portion extends from the center of the protection opening 131 to the surface of the protection layer 130 and covers the edge of the protection opening 131. Specifically, the blocking portion is integrally disposed at the top edge of the base conductive layer 140 and extends outward to the surface of the protection layer 130, so that the base conductive layer 140 can completely cover the protection opening 131. By arranging the shielding part, the substrate conductive layer 140 can completely cover the protection opening 131, and the gap between the protection opening 131 and the substrate conductive layer 140 is covered, so that when the substrate conductive layer 140 is formed for etching, the etching solution can be prevented from remaining at the edge of the protection opening 131, the undercut phenomenon of the substrate conductive layer 140 and the upper metal layer thereof is avoided, the connection strength of the whole structure is improved, and the substrate conductive layer 140 is made of graphene, so that the etching solution can be further prevented from being corroded.

In this embodiment, the thickness of the shielding portion is 4 to 8 μm. For example, the thickness of the blocking portion is 6 μm, that is, the height of the base conductive layer 140 is greater than the depth of the protection opening 131 by 6 μm. Meanwhile, the width of the shielding portion may be between 4-10 μm, thereby ensuring that the shielding portion can completely shield the protection opening 131.

In this embodiment, the first combined conductive layer 150 includes an adhesive layer 151, a barrier layer 153, and a wetting layer 155, the adhesive layer 151 is disposed on a side of the substrate conductive layer 140 away from the chip 110, the barrier layer 153 is disposed on a side of the adhesive layer 151 away from the chip 110, the wetting layer 155 is disposed on a side of the barrier layer 153 away from the chip 110, the conductive pillars 160 are disposed on a side of the wetting layer 155 away from the chip 110, the adhesive layer 151 is in contact with both the barrier layer 153 and the substrate conductive layer 140, so as to improve adhesion between the barrier layer 153 and the substrate conductive layer 140, and the wetting layer 155 is in contact with both the barrier layer 153 and the conductive pillars 160, so as to improve wettability between the barrier layer 153 and the conductive pillars 160. Specifically, the barrier layer 153 is used to block diffusion atoms between adjacent layers, and meanwhile, the adhesion layer 151, the barrier layer 153, and the wetting layer 155 are made of conductive metal materials, so that good electrical connection characteristics can be achieved.

In this embodiment, the bonding layer 151 is a titanium layer, and the base conductive layer 140 is a graphene layer, so when the bonding layer 151 and the base conductive layer 140 are combined, titanium carbide (TiC) is generated at the interface, which has the characteristics of being insoluble in water, having high chemical stability, hardly reacting with hydrochloric acid and sulfuric acid, having equivalent carbon atoms and titanium atoms at lattice positions, and combining TiC atoms with strong covalent bonds, and having several characteristics similar to metals, such as high melting point, boiling point and hardness, second only to diamond. And meanwhile, tiC has good heat conduction and electric conductivity, even shows superconductivity when the temperature is extremely low, and the problem that the bonding force between the metal layers is poor only by adopting a graphene structure in the traditional technology is solved by increasing the bonding force between titanium metal and promoting the metal.

In this embodiment, a side surface of the base conductive layer 140 away from the chip 110 is a flat surface, the adhesive layer 151 covers the surface of the base conductive layer 140, the barrier layer 153 covers the surface of the base conductive layer 140, the wetting layer 155 covers the surface of the barrier layer 153, and at least a portion of a side surface of the adhesive layer 151 away from the chip 110 is an outward convex arc surface, so that the adhesive layer 151 forms an arc-shaped bump structure. Specifically, the base conductive layer 140 is a planar structure, and can increase the bottom stress area of the first combined conductive layer 150, so as to improve the structural strength, and meanwhile, the adhesive layer 151 forms an arc-shaped bump structure, so that the contact area between the adhesive layer 151 and the barrier layer 153 is further improved, so as to improve the adhesive property of the adhesive layer 151, and meanwhile, the conductive property of the adhesive layer 151 is also improved, and the conductive effect is better.

In this embodiment, the barrier layer 153 and the wetting layer 155 are both of equal thickness, the barrier layer 153 covers the convex adhesive layer 151, and the wetting layer 155 covers the barrier layer 153. Preferably, the adhesion layer 151 is a titanium layer, the edge thickness is between 4 μm and 6 μm, the material of the barrier layer 153 may be at least one of nickel, vanadium and chromium, the thickness of the barrier layer 153 is 4 μm to 6 μm, the material of the wetting layer 155 is copper, the conductive pillar 160 may also be a copper pillar, and the thickness of the wetting layer 155 is 2 μm to 4 μm, wherein the convex adhesion layer 151 and the arc convex barrier layer 153 may improve the structural strength of the intermediate layer of the combined conductive layer.

In this embodiment, a second combined conductive layer 180 is further disposed on a side of the conductive pillar 160 away from the chip 110, and the second combined conductive layer 180 is disposed between the conductive pillar 160 and the solder cap 170. Specifically, the second combined conductive layer 180 uses a conductive metal material.

In this embodiment, the second combined conductive layer 180 includes a first conductive layer 181 and a second conductive layer 183, the first conductive layer 181 covers the surface of the conductive pillar 160, the second conductive layer 183 covers the first conductive layer 181, the solder cap 170 covers the second conductive layer 183, the second conductive layer 183 is configured to block atomic diffusion between the solder cap 170 and the conductive pillar 160, and the first conductive layer 181 is configured to improve adhesion between the second conductive layer 183 and the conductive pillar 160. Specifically, the first conductive layer 181 is a titanium layer, which can improve adhesion between the second conductive layer 183 and the conductive post 160. The second conductive layer 183 is made of nickel or vanadium alloy, and can play a role of blocking atoms in the tip solder cap 170 from diffusing to the conductive pillar 160. Of course, the first conductive layer 181 may also be made of graphene to improve heat dissipation and electrical conductivity.

In the present embodiment, at least a portion of a side surface of the conductive pillar 160 away from the chip 110 is an outer convex arc surface, so that the conductive pillar 160 forms an arc bump structure. Specifically, the conductive pillar 160 is a copper pillar, and one end of the conductive pillar 160, which is away from the chip 110, is in a convex arc shape, so that the contact area of the first conductive layer 181 can be increased, and the adhesion can be further improved.

It should be noted that in this embodiment, the conductive pillar 160 further forms stopping platforms on two sides of the convex arc surface, and the surfaces of the stopping platforms are disposed along a horizontal plane or inclined upwards from inside to outside, so that the height of the edge of the conductive pillar 160 is greater than or equal to the height of the edge of the convex arc surface. Through setting up the backstop platform, can play the buffer action that ends a class, slow down the phenomenon that welding cap 170 climbed along leading electrical pillar 160 side.

The embodiment further provides a method for manufacturing the bump package structure 100, which is used to manufacture the bump package structure 100, and the method includes:

s1: a chip 110 with a pad 120 is provided.

Referring to fig. 3, specifically, a chip 110 with a pad 120 is first provided, the chip 110 has a circuit layer therein, and the pad 120 is electrically connected to the circuit layer.

S2: a protective layer 130 is formed on the chip 110 at the side having the pad 120.

Referring to fig. 4, specifically, a liquid-like protective material, such as polyimide, is uniformly coated on the surface of the chip 110 by spin coating using a coater, and then is soft-baked and shaped to form a film through a hot plate.

S3: a protection opening 131 corresponding to the pad 120 is formed on the protection layer 130.

Referring to fig. 5, specifically, by using an exposure and development technique, a hole is formed at a predetermined position, and the position of the pad 120 is exposed and sloped, and then the oven is used again to heat and accelerate the curing of the protection layer 130 to a stable state, and then the adhesive residue machine is used to remove the contaminants or residues on the surface of the protection layer 130. Wherein the protection layer 130 may also be silicon nitride or the like.

S4: a base conductive layer 140 is formed in the protective opening 131.

Referring to fig. 6, specifically, a multi-layered graphene secondary structure is coated or otherwise formed on the surface of the protective layer 130 again, wherein a graphene material fills the protective opening 131 and covers the surface of the protective layer 130 to a thickness of 4-8 μm, and then the base conductive layer 140 is cured again using an oven. The base conductive layer 140 includes a multi-layered graphene structure.

S5: a first combined conductive layer 150 is formed on the base conductive layer 140.

Referring to fig. 7, specifically, an adhesion layer 151 is formed on the surface of the base conductive layer 140 by electroplating, and the adhesion layer 151 may be a titanium layer with a thickness of 4-6 μm, and the titanium layer has an extremely high metal adhesion property. Then, a convex arc surface is formed on the bonding layer 151 by plasma etching or chemical etching, and then a barrier layer 153 and a wetting layer 155 are sequentially formed on the bonding layer 151 by electroplating.

S6: forming a conductive pillar 160 on the first combined conductive layer 150;

referring to fig. 8, a protective paste is coated on the surface of the first combined conductive layer 150, the conductive pillar 160 is opened by a photolithography process, and then the conductive pillar 160 is formed by electroplating a copper layer.

After the conductive pillar 160 is formed, a convex arc surface may be formed at the end of the top pillar by plasma etching or chemical etching, and then a plasma desmear (Descum) may be used to remove the excess protective glue, so as to form a copper pillar structure with an arc-shaped bump.

Then, a second combined conductive layer 180 is formed at the end of the conductive pillar 160, wherein the forming process of the second combined conductive layer 180 is the same as that of the first combined conductive layer 150, and is not repeated herein.

S7: solder caps 170 are formed on the conductive posts 160.

Referring to fig. 1 in combination, specifically, after the second combined conductive layer 180 is formed, the solder caps 170 are formed by applying a protective paste, opening, printing, plating, and the like, and the protective paste is removed. The solder cap 170 may be a solder cap, and the process is completed after reflow.

In summary, in the bump package structure 100 provided by the present embodiment, the base conductive layer 140 adopts a multi-layer graphene structure, and the thickness of the base conductive layer 140 filling the opening of the protection layer 130 and exceeding the surface of the protection layer 130 is 4-6 μm, so that the multi-layer graphene structure is formed by increasing the volume of the graphene, the stability and hydrophobicity of the bottom structure are enhanced, and the multi-layer graphene structure has good hydrophobicity and stability due to the graphene material being a mesh-like and multi-layer graphene structure. The base conductive layer 140 is designed at the bottom layer of the conductive pillar 160, and the base conductive layer 140 can avoid the undercut problem generated when the UBM layer is removed by the conventional micro etching process, no matter the micro etching process is a chemical etching process or a plasma etching process. In addition, the CTE of the graphene is only 1/10 to 1/20 of copper and aluminum, so that deformation of the UBM layer at the bottom of the conductive pillar 160 can be better avoided, and the bonding pad 120 and the bottom structure of the chip 110 are protected by stress. In addition, the graphene conductivity is 100 times higher than that of other metals, a multi-layer graphene structure (with good stability) is formed along with the increase of the volume of graphene, the thermal conductivity and the conductivity of the graphene structure are further improved, and the problems that the UBM layer at the bottom of the bump cannot be well cooled and is not conductive in the traditional technology are solved. Meanwhile, in the conventional technology, when the conductive column 160 is loaded with current, due to joule heat effect, metal atoms at the bottom connection of the conductive column 160 bear the influence of an electric field and a thermal field at the same time, electromigration and thermal migration of an interconnection interface can remarkably reduce the service life of the conductive column 160 due to abnormal activity, so that potential failure hidden danger is caused, the problems are solved by strongly utilizing the stability, high thermal conductivity and high electrical conductivity of graphene, and the problem that the conductive column 160 can cause larger stress in a package body to cause damage of a brittle material layer in the conventional technology, such as cracking of a bonding pad of a chip 110 at the bottom of the copper column, delamination of a UBM metal layer or reduction of fatigue life of a welding spot, can be solved.

In the bump package structure 100 provided by this embodiment, the bonding layer 151 adopts an arc bump structure, so that the barrier layer 153 and the wetting layer 155 can be arc-shaped, and the bonding force can be improved while the structural strength is improved, thereby avoiding the phenomenon that the metal layer is easily broken when the wetting layer, the barrier layer 153 and the bonding layer 151 are thin in the conventional technology.

Second embodiment

Referring to fig. 9 and fig. 10, the present embodiment provides a bump package structure 100, the basic structure and principle and the generated technical effect are the same as those of the first embodiment, and for the sake of brief description, reference may be made to the corresponding contents in the first embodiment for parts not mentioned in the present embodiment.

In this embodiment, at least a portion of a surface of the base conductive layer 140 away from the chip 110 is an outward convex surface, so that the base conductive layer 140 forms an arc-shaped bump structure, the adhesive layer 151 is disposed on a periphery of the base conductive layer 140, the barrier layer 153 covers surfaces of the base conductive layer 140 and the adhesive layer 151, and the wetting layer 155 covers a surface of the barrier layer 153. Specifically, the base conductive layer 140 protrudes from the protection layer 130, and the protruding portion has a convex arc shape, and the adhesive layer 151, the barrier layer 153, and the wetting layer 155 are covered on the base conductive layer 140.

In this embodiment, the substrate conductive layer 140 is also a graphene layer, and a bump structure is adopted, so that the contact area can be increased, the bonding force can be increased, and the structural strength can be improved. Compared with the first embodiment, the graphene layer in the embodiment has a larger volume, so that the overall electric conductivity and heat dissipation capability are relatively better.

In the present embodiment, the peripheral edge of the base conductive layer 140 is provided with a receiving groove 157, the adhesive layer 151 is disposed in the receiving groove 157, and the thickness of the adhesive layer 151 is the same as the depth of the receiving groove 157. Specifically, the receiving groove 157 is located at the periphery of the outer convex arc surface of the base conductive layer 140, so that the adhesive layer 151 can be simultaneously contacted with the edge of the base conductive layer 140 and the edge of the barrier layer 153, and the adhesion of the two is improved.

It should be noted that in the present embodiment, the depth of the receiving groove 157 is equal to the thickness of the adhesive layer 151, so that the adhesive layer 151 can be embedded at the edge of the base conductive layer 140 smoothly, and the barrier layer 153 covers the outer convex cambered surfaces of the adhesive layer 151 and the base conductive layer 140 at the same time, thereby greatly improving the structural strength thereof. In addition, in the embodiment, the adhesive layer 151 is a titanium layer, and the bump edge of the base conductive layer 140 is planarized, so that titanium carbide (TiC) is generated at the edge, thereby further avoiding the undercut phenomenon, and meanwhile, the adhesive layer 151 is disposed in the accommodating groove 157, which can reduce the overall thickness of the first conductive combination layer, thereby reducing the bump height.

Third embodiment

Referring to fig. 11, the basic structure and principle of the bump package structure 100 and the resulting technical effects are the same as those of the first embodiment, and for brevity, reference may be made to corresponding contents in the first embodiment where no mention is made in this embodiment.

In this embodiment, at least a portion of a surface of the base conductive layer 140 away from the chip 110 is an outward convex arc surface, so that the base conductive layer 140 forms an arc-shaped bump structure, the adhesive layer 151 covers the surface of the base conductive layer 140, the barrier layer 153 covers the surface of the adhesive layer 151, and the wetting layer 155 covers the surface of the barrier layer 153. Specifically, the base conductive layer 140 protrudes from the protection layer 130, and the protruding portion has a convex arc shape, and the adhesive layer 151, the barrier layer 153, and the wetting layer 155 cover the base conductive layer 140.

In this embodiment, the adhesive layer 151 completely covers the surface of the base conductive layer 140, and a surface of the adhesive layer 151 away from the chip 110 is a flat plane, so as to planarize the barrier layer 153 and the wetting layer 155. Specifically, the bonding layer 151 is an inverted concave structure, one side surface of which is attached to the convex arc surface of the substrate conductive layer 140, and the other side surface of which is planar, so that the barrier layer 153 and the wetting layer 155 are both planar.

In the bump package structure 100 provided by this embodiment, the substrate conductive layer 140 adopts a multi-layer graphene structure, the bonding layer 151 also adopts a titanium layer, and the substrate conductive layer 140 adopts an outer convex arc structure, which can improve the contact area between the bonding layer 151 and the substrate conductive layer 140, thereby improving the bonding force, and the arc surface is completely attached, so that more titanium carbide (TiC) can be generated, thereby improving the overall heat dissipation capability and the conductive property.

Fourth embodiment

Referring to fig. 12 and fig. 13, the present embodiment provides a bump package structure 100, the basic structure and principle thereof and the technical effects thereof are the same as those of the first embodiment, the second embodiment or the third embodiment, and for the sake of brief description, reference may be made to the corresponding contents of the first embodiment, the second embodiment or the third embodiment for the parts not mentioned in the present embodiment.

In this embodiment, the base conductive layer 140 includes a first base layer 141, a second base layer 143, and a third base layer 145, the first base layer 141 is disposed in the protection opening 131, the second base layer 143 is disposed on the first base layer 141, the third base layer 145 is disposed on the second base layer 143, a side surface of the first base layer 141 away from the chip 110 is at least partially a convex arc surface, a side surface of the second base layer 143 away from the chip 110 is a flat surface, a side surface of the third base layer 145 away from the chip 110 is at least partially a convex arc surface, and the first combined conductive layer 150 is disposed on the third base layer 145.

Specifically, in the present embodiment, the first substrate layer 141 protrudes from the protection opening 131, the second substrate layer 143 and the third substrate layer 145 are both located outside the protection opening 131, the second substrate layer 143 completely covers the first substrate layer 141, the third substrate layer 145 completely covers the second substrate layer 143, and a side surface of the third substrate layer 145 away from the chip 110 is also in a shape of a convex arc.

It is noted that the adhesive layer 151 may completely cover the surface of the third substrate layer 145, and the surface of the adhesive layer 151 away from the chip 110 is a flat plane, so as to planarize the barrier layer 153 and the wetting layer 155. Specifically, the adhesive layer 151 has an inverted concave structure, one side surface of which is attached to the convex arc surface of the third substrate layer 145, and the other side surface of which is planar, so that the barrier layer 153 and the wetting layer 155 are both planar.

In addition, the adhesive layer 151 may also be disposed on the periphery of the third substrate layer 145, as disclosed in the second embodiment, a receiving groove 157 is formed on the periphery of the third substrate layer 145, the adhesive layer 151 is disposed in the receiving groove 157, the thickness of the adhesive layer 151 is the same as the depth of the receiving groove 157, and then the barrier layer 153 and the wetting layer 155 are formed on the adhesive layer 151 and the third substrate layer 145. Wherein, a side of the barrier layer 153 away from the chip 110 may be a flat plane.

In the present embodiment, the first and third substrate layers 141 and 145 each include a multi-layered graphene structure, the second substrate layer 143 includes a titanium layer, and titanium carbide layers are formed at both side interfaces of the second substrate layer 143. Specifically, the second substrate layer 143 is an intermediate layer, the intermediate layer is a titanium layer, the upper and lower third substrate layers 145 and the second substrate layer 143 are graphene layers, and the adhesion layer 151 also adopts a titanium layer, so that a multi-layered TiC structure is generated, the structural bonding force is improved, and the undercut phenomenon is further prevented.

The bump package structure 100 provided by the embodiment is formed by staggering multiple titanium layers and graphene layers, so that the electrical conductivity, the thermal conductivity and the structural strength of the whole structure can be improved, a multi-layer TiC structure is generated, the bonding force of the whole structure can be improved, and the undercut phenomenon is further prevented.

Fifth embodiment

Referring to fig. 14, the basic structure and principle of the bump package structure 100 and the technical effects thereof are the same as those of the first, second or third embodiments, and for the sake of brief description, reference may be made to the corresponding contents of the first, second or third embodiments for the sake of brevity.

In this embodiment, the base conductive layer 140 includes a first base layer 141, a second base layer 143, and a third base layer 145, the first base layer 141 is disposed in the protection opening 131, the second base layer 143 is disposed on the first base layer 141, the third base layer 145 is disposed on the second base layer 143, a side surface of the first base layer 141 away from the chip 110 is at least partially a convex arc surface, a side surface of the second base layer 143 away from the chip 110 is a flat surface, a side surface of the third base layer 145 away from the chip 110 is at least partially a convex arc surface, and the first combined conductive layer 150 is disposed on the third base layer 145.

In the present embodiment, the first combined conductive layer 150 is disposed on the third substrate layer 145, and specifically, the first combined conductive layer 150 may only include the barrier layer 153 and the wetting layer 155, the barrier layer 153 is disposed on the third substrate layer 145, the wetting layer 155 is disposed on the barrier layer 153, and the barrier layer 153 completely covers the third substrate layer 145. And the surface of the barrier layer 153 on the side away from the chip 110 is a flat plane, so that the bottoms of the wetting layer 155 and the conductive posts 160 can be planarized.

In this embodiment, the first substrate layer 141 and the third substrate layer 145 both include a titanium layer, the second substrate layer 143 includes a multilayer graphene structure, and titanium carbide layers are formed at both side interfaces of the second substrate layer 143. Specifically, the first substrate layer 141 and the third substrate layer 145 both perform the functions of electrical conduction and adhesion, and the second substrate layer 143 performs the functions of enhancing the electrical conduction and the heat dissipation.

In this embodiment, the first substrate layer 141 is a titanium layer, the first substrate layer 141 protrudes out of the protection opening 131, the edge of the first substrate layer 141 completely covers the protection opening 131 and protrudes by 4-6 μm, and the titanium layer covers the protection opening 131, which improves the bonding force between the bottom of the conductive post 160 and the pad 120 compared with the conventional structure, and the second substrate layer 143 is a graphene structure, which can compensate the poor conductivity and thermal conductivity of the titanium layer, and ensure sufficient heat dissipation capability and conductivity.

In the bump package structure 100 provided in this embodiment, the first substrate layer 141, the second substrate layer 143, and the third substrate layer 145 are sequentially stacked, the second substrate layer 143 is an intermediate layer, the intermediate layer adopts a multi-layer graphene structure, and the third substrate layer 145 and the first substrate layer 141 on the upper and lower sides are both titanium layers, so that a TiC structure of the intermediate layer is generated, the structural bonding force is improved, and the undercut phenomenon is prevented.

The above description is only for the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (15)

1. A bump package structure, comprising:

the chip comprises a chip, wherein a welding pad is arranged on one side of the chip;

the protective layer is arranged on one side of the chip, and a protective opening corresponding to the welding pad is formed in the protective layer;

a base conductive layer disposed in the protective opening and covering the protective opening;

a first combined conductive layer disposed on the base conductive layer;

a conductive post disposed on the first combined conductive layer;

and a solder cap disposed on said conductive post;

wherein the base conductive layer comprises a multi-layered graphene structure.

2. The bump package structure according to claim 1, wherein the height of the base conductive layer is greater than the depth of the protection opening, and a shielding portion is disposed on the top of the base conductive layer, and the shielding portion extends from the center of the protection opening to the surface of the protection layer and covers the edge of the protection opening.

3. The bump package structure according to claim 2, wherein the shielding portion has a thickness of 4-8 μm.

4. The bump package structure according to claim 1, wherein the first combined conductive layer includes an adhesive layer, a blocking layer and a wetting layer, the adhesive layer is disposed on a side of the substrate conductive layer away from the chip, the blocking layer is disposed on a side of the adhesive layer away from the chip, the wetting layer is disposed on a side of the blocking layer away from the chip, the conductive pillar is disposed on a side of the wetting layer away from the chip, the adhesive layer is in contact with the blocking layer and the substrate conductive layer at the same time for improving adhesion between the blocking layer and the substrate conductive layer, and the wetting layer is in contact with the blocking layer and the conductive pillar at the same time for improving wettability between the blocking layer and the conductive pillar.

5. The bump package structure according to claim 4, wherein a side surface of the base conductive layer away from the chip is a flat surface, the adhesive layer covers the surface of the base conductive layer, the barrier layer covers the surface of the base conductive layer, the wetting layer covers the surface of the barrier layer, and at least a portion of a side surface of the adhesive layer away from the chip is an outward convex arc surface, so that the adhesive layer forms an arc bump structure.

6. The bump package structure according to claim 4, wherein at least a portion of a surface of the base conductive layer away from the chip is an outward convex arc surface, so that the base conductive layer forms an arc bump structure, the adhesive layer is disposed on a periphery of the base conductive layer, the barrier layer covers surfaces of the base conductive layer and the adhesive layer, and the wetting layer covers a surface of the barrier layer.

7. The bump package structure according to claim 6, wherein a receiving groove is formed at a periphery of the conductive base layer, the adhesive layer is disposed in the receiving groove, and a thickness of the adhesive layer is the same as a depth of the receiving groove.

8. The bump package structure according to claim 4, wherein at least a portion of a surface of a side of the base conductive layer away from the chip is an outer convex arc surface, so that the base conductive layer forms an arc bump structure, the adhesive layer covers the surface of the base conductive layer, the barrier layer covers the surface of the adhesive layer, and the wetting layer covers the surface of the barrier layer.

9. The bump package structure of claim 8, wherein a surface of the adhesive layer on a side away from the chip is a flat surface, so as to planarize the barrier layer and the wetting layer.

10. The bump package structure according to claim 1, 4 or 6, wherein the base conductive layer includes a first base layer, a second base layer and a third base layer, the first base layer is disposed in the protection opening, the second base layer is disposed on the first base layer, the third base layer is disposed on the second base layer, a side surface of the first base layer away from the chip is at least partially convex, a side surface of the second base layer away from the chip is a flat surface, a side surface of the third base layer away from the chip is at least partially convex, and the first combined conductive layer is disposed on the third base layer.

11. The bump package structure of claim 10, wherein the first and third substrate layers each comprise a multi-layer graphene structure, the second substrate layer comprises a titanium layer, and the second substrate layer has a titanium carbide layer formed at both side interfaces thereof.

12. The bump package structure of claim 10, wherein the first substrate layer and the third substrate layer each comprise a titanium layer, the second substrate layer comprises a multi-layer graphene structure, and the second substrate layer has a titanium carbide layer formed at both side interfaces thereof.

13. The bump package structure according to claim 1, wherein a second combined conductive layer is further disposed on a side of the conductive pillar away from the chip, and the second combined conductive layer is disposed between the conductive pillar and the solder cap.

14. The bump package structure according to claim 13, wherein the second combined conductive layer includes a first conductive layer and a second conductive layer, the first conductive layer covers the surface of the conductive pillar, the second conductive layer covers the first conductive layer, the solder cap covers the second conductive layer, the second conductive layer is used for blocking atomic diffusion between the solder cap and the conductive pillar, and the first conductive layer is used for improving adhesion between the second conductive layer and the conductive pillar.

15. The bump package structure according to claim 14, wherein a side surface of the conductive pillar away from the chip is at least partially convexly curved, so that the conductive pillar forms an arc bump structure.

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