CN217468472U - Semiconductor device, semiconductor device package, lighting apparatus, and backlight unit - Google Patents
Semiconductor device, semiconductor device package, lighting apparatus, and backlight unit Download PDFInfo
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- CN217468472U CN217468472U CN202221420976.0U CN202221420976U CN217468472U CN 217468472 U CN217468472 U CN 217468472U CN 202221420976 U CN202221420976 U CN 202221420976U CN 217468472 U CN217468472 U CN 217468472U
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Abstract
The utility model provides a semiconductor device, semiconductor device packaging body, lighting apparatus and backlight unit, include: the light-emitting structure comprises an N-type layer, a P-type layer and an active layer positioned between the N-type layer and the P-type layer; and an interconnection bump including: a pad electrode on at least one of the N-type layer and the P-type layer, a solder bump bonded to the pad electrode; the porosity of the interconnection bump is less than or equal to 5%. The porosity in the solder ball electrode can be reduced.
Description
Technical Field
The utility model relates to the field of semiconductor technology, particularly, relate to a semiconductor device, semiconductor device packaging body, lighting apparatus and backlight unit.
Background
When a Light Emitting Diode (LED) chip is packaged, solder paste is printed on a pad electrode layer of the chip to form a solder ball electrode, and the solder ball electrode is subjected to backflow, cleaning and height testing, and then is ground, scratched and sorted for shipment. When the solder paste printing and reflow process is carried out, the upper layer metal of the pad electrode and the solder paste form an intermetallic compound, and residual stress generated by phase change in the intermetallic compound forming process can cause cracks of relatively fragile parts of the intermetallic compound, which are in contact with the electrode, so that the solder paste is separated from the pad electrode to form pores.
SUMMERY OF THE UTILITY MODEL
In view of the above, an object of the present invention is to provide a semiconductor device, a semiconductor device package, an illumination apparatus and a backlight unit to reduce porosity in a solder ball electrode.
In a first aspect, an embodiment of the present invention provides a light emitting diode with a solder ball electrode, including: the light-emitting structure comprises an N-type layer, a P-type layer and an active layer positioned between the N-type layer and the P-type layer; and an interconnect bump, comprising: a pad electrode on at least one of the N-type layer and the P-type layer, a solder bump bonded to the pad electrode.
In combination with the first aspect, an embodiment of the present invention provides a first possible implementation manner of the first aspect, wherein a porosity of the interconnection bump is less than or equal to 5%, the pad electrode includes a multi-layer metal layer, an uppermost layer of the multi-layer metal layer is an Au layer, the solder bump is in direct contact with the Au layer, a thickness of the Au layer is
With reference to the first possible implementation manner of the first aspect, an embodiment of the present invention provides a second possible implementation manner of the first aspect, where a porosity of the interconnection bump is less than or equal to 3%, and the interconnection bump is formed by a bump-on-bump process
In combination with the first aspect, embodiments of the present invention provide a third possible implementation manner of the first aspect, wherein the pad electrode includes an under bump metallurgy layer, and an intermetallic compound layer located between the under bump metallurgy layer and the solder bump, and a porosity between the intermetallic compound layer and the solder bump is less than or equal to 5%.
In combination with the third possible implementation manner of the first aspect, the present invention provides a fourth possible implementation manner of the first aspect, wherein the intermetallic compound sequentially includes a Ti layer, a Ni layer, and an Au layer, and the Ti layer has a thickness of
The thickness of the Ni layer is
The thickness of the Au layer is
In combination with the fourth possible implementation manner of the first aspect, the present invention provides a fifth possible implementation manner of the first aspect, wherein a porosity between the intermetallic compound layer and the solder bump is less than or equal to 3%, and the second metal layer is formed by a metal layer or a metal layer
In combination with the third possible implementation manner of the first aspect, the present invention provides a sixth possible implementation manner of the first aspect, wherein the under bump metallurgy layer includes a bonding layer, a metal reflective layer, and a cladding layer, and the solder bump is Sn.
In a second aspect, the embodiments of the present invention further provide a semiconductor device, including:
a light emitting structure having a plurality of electrodes; and the interconnection lug is electrically connected with the electrodes, wherein the interconnection lug comprises a pad electrode positioned on the electrodes and a solder lug bonded to the pad electrode, and the porosity of the interconnection lug is less than or equal to 5%.
In combination with the second aspect, embodiments of the present invention provide a first possible implementation manner of the second aspect, wherein the light emitting structure includes an N-type layer, a P-type layer, and an active layer located between the N-type layer and the P-type layer; the plurality of electrodes are arranged on the same side of the light-emitting structure and comprise a plurality of first N electrodes and a plurality of first P electrodes which are respectively and electrically connected with the N-type layer and the P-type layer;
the pad electrode includes an N-electrode pad and a P-electrode pad electrically connected to the plurality of first N-electrodes and the plurality of first P-electrodes, respectively.
In a third aspect, embodiments of the present application provide a semiconductor device package, including:
a package main body;
a semiconductor device on the package main body; and an encapsulating portion that encapsulates the semiconductor device,
wherein the semiconductor device is as described in any one of the above.
In combination with the third aspect, embodiments of the present invention provide a first possible implementation manner of the third aspect, wherein the encapsulating portion includes at least one phosphor.
In a fourth aspect, an embodiment of the present application provides a lighting device, including:
a housing; and a semiconductor device package as described above.
In a fifth aspect, embodiments of the present application provide a backlight unit including a backlight plate, and the semiconductor device package as described above.
The embodiment of the utility model provides a semiconductor device, semiconductor device packaging body, lighting apparatus and backlight unit, semiconductor device includes: the light-emitting structure comprises an N-type layer, a P-type layer and an active layer positioned between the N-type layer and the P-type layer; and an interconnect bump, comprising: a pad electrode on at least one of the N-type layer and the P-type layer, a solder bump bonded to the pad electrode; the porosity of the interconnection bump is less than or equal to 5%. Thus, the porosity of the interconnection bump is controlled to be less than or equal to 5%, so that the pores formed in the tin are reduced.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on these drawings without inventive efforts.
Fig. 1 is a schematic cross-sectional structural diagram of a semiconductor device according to a first embodiment of the present invention;
fig. 2 is a schematic diagram illustrating a top view structure of a semiconductor device according to a first embodiment of the present invention;
fig. 3 is a schematic diagram illustrating an interconnect bump structure provided in an embodiment of the present invention;
fig. 4 is a schematic cross-sectional structural diagram of a semiconductor device provided in a second embodiment of the present invention;
fig. 5 is a schematic diagram illustrating a top view structure of a semiconductor device according to a second embodiment of the present invention;
fig. 6 is a schematic diagram illustrating an interconnect bump 700 provided by a second embodiment of the present invention;
fig. 7 is a schematic view of another structure of an interconnection bump 700 according to a second embodiment of the present invention;
fig. 8 is a schematic structural diagram of a semiconductor device package according to an embodiment of the present invention;
fig. 9 is a schematic diagram illustrating a structure of a backlight unit according to an embodiment of the present invention;
fig. 10 is a schematic view of another structure of a backlight unit according to an embodiment of the present invention;
fig. 11 is an exploded schematic view of a lighting device provided in an embodiment of the present invention;
fig. 12 is a schematic view illustrating another exploded structure of the lighting device according to the embodiment of the present invention.
The attached drawings are marked as follows:
100: a substrate; 200: a light emitting structure; 210: an N-type layer; 220: an active layer; 230: a P-type layer; 300: a barrier layer; 400: a transparent conductive layer; 500: an electrode; 510: a first N electrode; 520: a first P electrode; 530: a second N electrode; 540: a second P electrode; 600: an insulating layer; 700: an interconnection bump; 701: an Au layer; 704: a Ti layer; 705: a Ni layer; 702: a metal reflective layer; 703: a coating layer; 710: a pad electrode; 711: an N-type pad electrode; 712: a P-type pad electrode; 720: a solder bump; 721: an N-type solder bump; 722: a P-type solder bump; 800: a protective layer; 810: a through hole; 7100: a under bump metallurgy layer; 7200: an intermetallic compound layer; 1000: a semiconductor device; 2000: mounting a substrate; 7000: an encapsulating portion; 2100: a first circuit pattern; 2200: a second circuit pattern; 3000: a first backlight unit; 3001: a first light source; 4000: a second backlight unit; 4002: a substrate; 4001: a second light source; 4003: a light guide plate; 4004: a reflective layer; 5000: an illumination device; 5010: a light emitting module; 5020: a drive unit; 5030: a connection unit; 5040: an outer housing; 5050: an inner housing; 5060: a cover unit; 5011: a semiconductor device; 5012: a circuit substrate; 5041: a heat dissipation plate; 5042: a heat sink; 6000: a lighting device; 6010: a light emitting module; 6020: a main body unit; 6030: a cover unit; 6040: a terminal unit; 6012: a substrate; 6011: a semiconductor device; 6021: recessing; 6022: heat dissipation fins; 6023: fastening the groove; 6031: a protruding portion; 6041: and an electrode pin.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the drawings in the embodiments of the present invention are combined to clearly and completely describe the technical solutions in the embodiments of the present invention, and obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. The components of embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiment of the present invention, all other embodiments obtained by the person skilled in the art without creative work belong to the protection scope of the present invention.
Embodiments of the present invention provide a semiconductor device, a semiconductor device package, a lighting device, and a backlight unit, which are described below by way of example.
Fig. 1 is a schematic cross-sectional structural diagram of a semiconductor device according to a first embodiment of the present invention;
fig. 2 is a schematic diagram illustrating a top view structure of a semiconductor device according to a first embodiment of the present invention;
fig. 3 is a schematic diagram illustrating an interconnect bump structure according to an embodiment of the present invention.
Referring to fig. 1 to 3, the semiconductor device includes: a light emitting structure 200 including an N-type layer 210, a P-type layer 230, and an active layer 220 between the N-type layer 210 and the P-type layer 230; and
an interconnect bump (not shown) comprising: a pad electrode 710 on at least one electrode 500 of the N-type layer 210 and the P-type layer 230,
a solder bump 720 bonded to the pad electrode 710;
the porosity of the interconnection bump is less than or equal to 5%.
In the embodiment of the present invention, as an optional embodiment, the pad electrode 710 includes a plurality of metal layers, the uppermost metal layer is an Au layer, the solder bump 720 directly contacts with the Au layer, and the Au layer has a thickness of
The embodiment of the utility model provides an in, pad electrode 710 the superiors metal level be gold (Au), and Au and solder bump 720 form the AuSn alloy, controls the reaction that forms the AuSn alloy through the thickness of control gold layer to porosity to in the tin ball electrode is controlled. In the embodiment of the utility model, the thickness that sets up the Au layer is
Within the thickness range, the reaction of gold and tin can be effectively reduced, so that holes formed in the tin in the reflow process are reduced, electric leakage caused by the holes is reduced, the electrical property of the LED chip is optimized, the adhesion force of the solder bump 720 and the pad electrode 710 can be guaranteed, and the solder bump 720 is prevented from falling off from the pad electrode 710.
In the embodiment of the utility model, as an optional embodiment, the porosity of the interconnecting lug is less than or equal to 3 percent,
in the embodiment of the present invention, as an optional embodiment, the semiconductor device further includes:
a barrier layer 300 deposited on the P-type layer 230;
a transparent conductive layer 400 deposited on the barrier layer 300 and the P-type layer 230;
a first N electrode 510 deposited on the N-type layer 210;
a first P electrode 520 deposited on the transparent conductive layer 400 at a position corresponding to the barrier layer 300;
an insulating layer 600 deposited on the N-type layer 210, the substrate 100, the first N-electrode 510, the transparent conductive layer 400, and the first P-electrode 520;
a P-type pad electrode 712 deposited on the insulating layer 600 and electrically connected to the first P-electrode 520;
an N-type pad electrode 711 deposited on the insulating layer 600 and electrically connected to the first N-electrode 510;
a P-type solder bump 722 deposited on the P-type pad electrode 712; and the number of the first and second groups,
an N-type solder bump 721 is deposited on the N-type pad electrode 711.
Fig. 4 is a schematic cross-sectional structural diagram of a semiconductor device provided in a second embodiment of the present invention;
fig. 5 is a schematic diagram illustrating a top view structure of a semiconductor device according to a second embodiment of the present invention;
fig. 6 is a schematic diagram illustrating an interconnect bump 700 provided by a second embodiment of the present invention;
fig. 7 is a schematic view of another structure of the interconnection bump 700 according to the second embodiment of the present invention.
As shown in fig. 4 to 7, the semiconductor device of this embodiment includes:
a light emitting structure 200 having a plurality of electrodes 500; and an interconnection bump 700 electrically connected to the plurality of electrodes 500, wherein the interconnection bump 700 includes a pad electrode 710 on the electrode 500, and a solder bump 720 bonded to the pad electrode 710, and a porosity of the interconnection bump 700 is less than or equal to 5%.
In the embodiment of the present invention, as an optional embodiment, the light emitting structure 200 includes an N-type layer 210, a P-type layer 230, and an active layer 220 located between the N-type layer 210 and the P-type layer 230; the plurality of electrodes 500 are on the same side of the light emitting structure 200, and include a plurality of first N electrodes 510 and a plurality of first P electrodes 520 electrically connected to the N-type layer 210 and the P-type layer 230, respectively;
the pad electrode 710 includes an N-type pad electrode 711 and a P-type pad electrode 712 electrically connected to the plurality of first N electrodes 510 and the plurality of first P electrodes 520, respectively.
In the embodiment of the present invention, as an optional embodiment, the semiconductor device of this embodiment further includes:
a barrier layer 300 deposited on the P-type layer 230;
a transparent conductive layer 400 deposited on the barrier layer 300 and the P-type layer 230;
a second N electrode 530 on the first N electrode 510;
a second P electrode 540 on the first P electrode 520;
an insulating layer 600 deposited on the N-type layer 210, the substrate 100, the first N-electrode 510, the transparent conductive layer 400, and the first P-electrode 520;
a protective layer 800 deposited on the second P electrode 540 and the second N electrode 530;
a P-type solder bump 722 deposited on the P-type pad electrode 712; and the number of the first and second groups,
an N-type solder bump 721 is deposited on the N-type pad electrode 711.
In the embodiment of the present invention, as an optional embodiment, the pad electrode 710 includes the under bump metallurgy layer 7100, and the intermetallic compound layer 7200 located between the under bump metallurgy layer 7100 and the solder bump 720, and the porosity between the intermetallic compound layer 7200 and the solder bump 720 is less than or equal to 5%.
In the embodiment of the present invention, as an optional embodiment, the intermetallic compound layer 7200 sequentially includes a Ti layer 704, a Ni layer 705, and an Au layer 701, and the thickness of the Ti layer 704 is
Ni layer 705 thickness of
Au layer 701 has a thickness of
In the embodiment of the present invention, as an optional embodiment, the porosity between the intermetallic compound layer 7200 and the solder bump 720 is less than or equal to 3%,
in the embodiment of the present invention, as an optional embodiment, the under bump metallurgy layer 7100 includes a bonding layer, a metal reflection layer 702 and a cladding layer 703, and the solder bump 720 is Sn. As an alternative embodiment, the adhesive layer is an Au layer 701.
Fig. 8 shows a schematic structural diagram of a semiconductor device package according to an embodiment of the present invention. As shown in fig. 8, the semiconductor device package includes:
a package main body (not shown in the drawings);
a semiconductor device 1000 on the package main body; and an encapsulating portion 7000 encapsulating the semiconductor device 1000,
wherein semiconductor device 1000 is as arbitrarily described above.
The encapsulated portion 7000 includes at least one phosphor.
In an embodiment of the present invention, the semiconductor device package includes: semiconductor device 1000, mounting substrate 2000, and encapsulating portion 7000. Among them, the semiconductor device 1000 may be mounted on the mounting substrate 2000 to be electrically connected to the first and second circuit patterns 2100 and 2200. The N-type and P- type pad electrodes 711 and 712 of the semiconductor device are electrically connected to the first and second circuit patterns 2100 and 2200 through the N-type and P-type solder bumps 721 and 722, respectively.
In the embodiment of the present invention, the semiconductor device can be encapsulated by the encapsulating portion 7000, and in this way, a Chip On Board (COB) type package structure can be provided. As an alternative embodiment, the mounting substrate 2000 may be provided as a substrate such as a Printed Circuit Board (PCB), a Metal Core Printed Circuit Board (MCPCB), a Multilayer Printed Circuit Board (MPCB), or a Flexible Printed Circuit Board (FPCB), and the structure of the mounting substrate 2000 may be applied in various different ways.
In the embodiment of the present invention, as another alternative embodiment, the wavelength conversion material may be contained in the encapsulating portion 7000. Wherein the wavelength conversion material may include at least one of phosphors that emit light upon excitation by light generated by the semiconductor device to emit light having a wavelength different from that of the light generated by the semiconductor device. Thus, the emission of light can be controlled to have different colors, including white light.
Fig. 9 is a schematic diagram illustrating a structure of a backlight unit according to an embodiment of the present invention;
fig. 10 is a schematic view of another structure of the backlight unit according to the embodiment of the present invention.
As an alternative embodiment, as shown in fig. 9 and 10, the first light source 3001 in the first backlight unit 3000 may emit light upward in a direction in which a Liquid Crystal Display (LCD) device is disposed. In the second backlight unit 4000, the second light source 4001 mounted on the substrate 4002 may emit light in a lateral direction, so that the emitted light may be incident on the light guide plate 4003 to be converted into a form of a surface light source. Light that has passed through the light guide plate 4003 may be dissipated upward, and a reflective layer 4004 may be disposed under the light guide plate 4003 to improve light extraction efficiency.
Fig. 11 shows an exploded schematic view of a lighting device provided by an embodiment of the present invention. As shown in fig. 11, the illumination apparatus of this embodiment includes:
a housing; and a semiconductor device package as described above.
In an embodiment of the utility model provides an in, lighting apparatus 5000 is bulb type illuminator, include: a light emitting module 5010, a driving unit 5020, and an external connection unit 5030. As another alternative embodiment, the lighting apparatus 5000 may further include: outer structures of the outer housing 5040, inner housing 5050, and cover unit 5060.
In the embodiment of the present invention, the optical module 5010 may include a semiconductor device 5011 having the same or similar structure as the semiconductor device 100 and a circuit substrate 5012 on which the semiconductor device 5011 is mounted. In the exemplary embodiment, an example is illustrated in which a single semiconductor device 5011 is mounted on a circuit substrate 5012; however, a plurality of semiconductor devices 5011 may be mounted on the circuit substrate 5012 as needed. As another alternative, the semiconductor device 5011 may not be directly mounted on the circuit substrate 5012, and may be mounted on the circuit substrate 5012 after being manufactured in the form of a package as shown in fig. 8.
In an embodiment of the present invention, the external case 5040 may serve as a heat dissipating unit, and may include a heat dissipating plate 5041 directly contacting the light emitting module 5010 to improve a heat dissipating effect and a heat sink 5042 surrounding a side surface of the external case 5040.
In the embodiment of the present invention, the cover unit 5060 may be mounted on the light emitting module 5010, and may have a convex lens shape. The drive unit 5020 can be mounted in the inner housing 5050 and can be connected to an external connection unit 5030 such as a socket structure to supply power from the outside. As an alternative embodiment, the driving unit 5020 may convert power into a suitable current source for driving the semiconductor device 5011 of the light emitting module 5010 and may provide the converted current source. For example, the driving unit 5020 may be configured as an alternating current-direct current (AC-DC) converter or a rectifier circuit assembly.
Fig. 12 is a schematic view illustrating another exploded structure of the lighting device according to the embodiment of the present invention. As shown in fig. 12, the illumination apparatus of this embodiment includes:
the backlight unit comprises a backlight plate and the semiconductor device package body.
In the embodiment of the present invention, as an optional embodiment, the lighting apparatus 6000 is a bar-type lamp, and may include a light emitting module 6010, a main body unit 6020, a cover unit 6030, and a terminal unit 6040. Among others, the light emitting module 6010 may include a substrate 6012 and a plurality of semiconductor devices 6011 mounted on the substrate 6012. The semiconductor device 6011 may be the semiconductor device of fig. 5 or the semiconductor device package of fig. 8, and the light emitting module 6010 may be mounted and fixed on one surface of the body unit 6020 using the recess 6021, and heat generated from the light emitting module 6010 may be dissipated outward. As an alternative embodiment, the body unit 6020 may include a heat sink as a kind of support structure, and may include a plurality of heat dissipation fins 6022 for dissipating heat provided on both lateral surfaces of the body unit 6020 while protruding therefrom.
The cover unit 6030 may be fastened to the fastening groove 6023 of the body unit 6020 and may have a semicircular curved surface to allow light to be uniformly dissipated outward. A protruding portion 6031 that engages with the fastening groove 6023 of the housing 6020 may be formed on the bottom surface of the cover unit 6030 along the length direction of the body unit 6020.
In the embodiment of the present invention, as an alternative embodiment, a terminal unit 6040 may be provided in the open end portion of the body unit 6020 along the length direction of the body unit 6020, and power may be supplied to the light emitting module 6010. The terminal unit 6040 may include an electrode pin 6041 protruding outward.
In the embodiment of the utility model, through the experimental verification of X-ray board, the porosity data that the test obtained are shown in Table 1.
TABLE 1
As can be seen from Table 1, when the surface layer Au is thick (not less than
) When the tin paste is used, the mutual solubility of AuSn is increased, so that bubbles in the tin paste are increased, and the porosity is higher; au is thinner (smaller than) on the surface layer
) When used, the solder paste has a low porosity. The thickness of the surface layer Au is
The porosity may be made less than 5%. Therefore, the porosity of the contact interface between the tin paste and the Au layer in the tin ball electrode can be effectively reduced by proportioning the thickness of the gold layer in the tin ball electrode structure.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus once an item is defined in one figure, it need not be further defined and explained in subsequent figures, and moreover, the terms "first", "second", "third", etc. are used merely to distinguish one description from another and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present application, and are used for illustrating the technical solutions of the present application, but not limiting the same, and the scope of the present application is not limited thereto, and although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope disclosed in the present application; such modifications, changes or substitutions do not depart from the spirit and scope of the embodiments of the present application. Are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (13)
1. A semiconductor device, comprising: the light-emitting structure comprises an N-type layer, a P-type layer and an active layer positioned between the N-type layer and the P-type layer; and
an interconnect bump, comprising: a pad electrode on at least one of the N-type layer and the P-type layer,
a solder bump bonded to the pad electrode,
the pad electrode comprises a plurality of metal layers, the uppermost metal layer is an Au layer, and the thickness of the Au layer is
2. The semiconductor device according to claim 1, wherein: the porosity of the interconnection bump is less than or equal to 5%.
3. The semiconductor device according to claim 2, wherein: the interconnected bump has a porosity of less than or equal to3 percent of Au layer with thickness less than or equal to
4. The semiconductor device according to claim 1, wherein: the pad electrode comprises an under bump metallurgy layer and an intermetallic compound layer positioned between the under bump metallurgy layer and the solder bump, and the porosity between the intermetallic compound layer and the solder bump is less than or equal to 5%.
5. The semiconductor device according to claim 4, wherein: the intermetallic compound comprises a Ti layer, a Ni layer and an Au layer in sequence, wherein the Ti layer is thick
The thickness of the Ni layer is
The thickness of the Au layer is
6. The semiconductor device according to claim 5, wherein: the porosity between the intermetallic compound layer and the solder bump is less than or equal to 3%, and the thickness of the Au layer is less than or equal to
7. The semiconductor device according to claim 4, wherein: the under bump metallurgy layer comprises an adhesive layer, a metal reflecting layer and a coating layer, and the solder bump is Sn.
8. A semiconductor device, comprising:
a light emitting structure having a plurality of electrodes; and the interconnection lug is electrically connected with the electrodes, wherein the interconnection lug comprises a pad electrode positioned on the electrodes and a solder lug bonded to the pad electrode, and the porosity of the interconnection lug is less than or equal to 5%.
9. A semiconductor device according to claim 8, characterized in that: the light-emitting structure comprises an N-type layer, a P-type layer and an active layer positioned between the N-type layer and the P-type layer; the plurality of electrodes are arranged on the same side of the light-emitting structure and comprise a plurality of first N electrodes and a plurality of first P electrodes which are respectively and electrically connected with the N-type layer and the P-type layer;
the pad electrode includes an N-electrode pad and a P-electrode pad electrically connected to the plurality of first N-electrodes and the plurality of first P-electrodes, respectively.
10. A semiconductor device package, comprising:
a package main body;
a semiconductor device on the package main body; and an encapsulating portion that encapsulates the semiconductor device,
wherein the semiconductor device is as set forth in any one of claims 1 to 9.
11. The semiconductor device package of claim 10, wherein the encapsulation portion comprises at least one phosphor.
12. An illumination device, comprising:
a housing; and a semiconductor device package as recited in claim 10.
13. A backlight unit comprising a backlight plate and the semiconductor device package according to claim 10.
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| CN202221420976.0U CN217468472U (en) | 2022-06-07 | 2022-06-07 | Semiconductor device, semiconductor device package, lighting apparatus, and backlight unit |
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| CN202221420976.0U CN217468472U (en) | 2022-06-07 | 2022-06-07 | Semiconductor device, semiconductor device package, lighting apparatus, and backlight unit |
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