CN217426348U - Drive circuit of large display screen and display screen - Google Patents
Drive circuit of large display screen and display screen Download PDFInfo
- Publication number
- CN217426348U CN217426348U CN202221014266.8U CN202221014266U CN217426348U CN 217426348 U CN217426348 U CN 217426348U CN 202221014266 U CN202221014266 U CN 202221014266U CN 217426348 U CN217426348 U CN 217426348U
- Authority
- CN
- China
- Prior art keywords
- display screen
- module
- interface
- driving
- control unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Control Of El Displays (AREA)
Abstract
The utility model discloses a drive circuit of a large display screen and a display screen, which comprises a processing module and a drive module connected with the processing module; the display memory module is connected to the driving module; the processing module is used for transmitting image data to be displayed to the video memory module through the driving module; and the driving module is used for refreshing the image data in the display memory module on a display screen. An object of the utility model is to provide a drive circuit and display screen of big display screen, through a display memory module of extension on drive module to solve under the MCU mode because of showing the not enough problem that only is applicable to than little display screen of memory capacity.
Description
Technical Field
The utility model relates to a display screen drive technical field especially relates to a drive circuit and display screen of big display screen.
Background
The LCD screen can be divided into MCU mode, RGB mode, SPI mode, MDDI mode, and other modes according to different interfaces, and the MCU mode and the RGB mode are more commonly used.
The control mode of the MCU mode is as shown in fig. 1, a CPU (processor) is externally connected to a driver chip, the driver chip includes a GRAM (graphics primitive), the CPU transmits an image to be displayed to the GRAM of the driver chip, and the driver chip refreshes data of the GRAM on an LCD screen.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a drive circuit and display screen of big display screen, through a display memory module of extension on drive module to solve under the MCU mode because of showing the not enough problem that only is applicable to than little display screen of memory capacity.
The utility model discloses a following technical scheme realizes:
a first aspect of an embodiment of the present application provides a driving circuit of a large display screen, including a processing module and a driving module connected to the processing module; the display device also comprises a display memory module which is connected with the driving module;
the processing module is used for transmitting image data to be displayed to the video memory module through the driving module;
and the driving module is used for refreshing the image data in the display memory module on a display screen.
The control mode of the MCU mode is as shown in fig. 1, a CPU (processor) is externally connected with a driving chip, the driving chip includes a GRAM (graphics primitive), the CPU transmits an image to be displayed to the GRAM of the driving chip, and the driving chip refreshes data of the GRAM on an LCD screen. Based on this, for making the MCU mode can be applicable to big display screen, this application embodiment has provided the drive circuit of big display screen, through expand a video memory module on drive module to solve under the MCU mode because of the not enough problem that only is applicable to comparatively little display screen of video memory capacity.
Optionally, the driving module includes a first interface unit, a data buffer unit, a video memory control unit, a data flow control unit, and a second interface unit;
the input end of the first interface unit is connected with the output end of the processing module, the output end of the first interface unit is connected with the input end of the data flow control unit, and the output end of the data flow control unit is used for connecting the display screen, the video memory control unit and the input end of the data cache unit; the output end of the video memory control unit is connected with the input end of the video memory module; the output end of the data cache unit is connected with the input end of the second interface unit, and the output end of the second interface unit is connected with the input end of the display screen.
Optionally, the video memory module is configured as an SDRAM memory or an SRAM memory.
Optionally, the first interface unit is a UART interface, a CAN interface, or a 1553B interface.
Optionally, the second interface unit is an RGB interface, an LVDS interface, or an MIPI interface.
Optionally, the processing module and the driving module are integrated on one processing chip.
By integrating the processing module and the driving module on one processing chip, the circuit complexity of the circuit structure can be reduced.
Optionally, the processing chip is configured as an SOPC chip.
Optionally, the model of the SOPC chip is SM9B100 MAL.
A second aspect of the embodiments of the present application provides a display screen, which includes a display panel and a large display screen driving circuit as described above, wherein an input end of the display panel is connected to an output end of the driving module.
Optionally, the interface of the display panel is an RGB interface.
Compared with the prior art, the utility model, following advantage and beneficial effect have:
1. by expanding a video memory module on the driving module, the problem that the MCU mode is only suitable for a smaller display screen due to insufficient video memory capacity is solved;
2. different types of driving interfaces are arranged on the driving module to increase the universality of the driving circuit, and display screens with different interface types can be driven.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 is a schematic diagram of the MCU driving mode;
fig. 2 is a schematic structural diagram of the driving circuit of the present invention;
fig. 3 is a schematic circuit connection diagram of the driving circuit of the present invention;
fig. 4 is a schematic diagram of the working flow of the driving circuit of the present invention;
fig. 5 is a schematic diagram of the circuit connection between the display screen and the driving circuit of the present invention.
Detailed Description
To make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the following examples and drawings, and the exemplary embodiments and descriptions thereof of the present invention are only used for explaining the present invention, and are not intended as limitations of the present invention.
Example 1
A driving circuit of a large display screen, as shown in fig. 2 and 3, comprises a processing module (corresponding to the CPU in fig. 2 and 3) and a driving module (corresponding to the FPGA in fig. 2 and 3) connected with the processing module; the display memory module is connected to the driving module;
the processing module is used for transmitting image data to be displayed to the video memory module through the driving module;
and the driving module is used for refreshing the image data in the display memory module on the display screen.
The MCU mode is controlled as shown in fig. 1, a CPU (processor) is externally connected to a driver chip, the driver chip includes a GRAM (graphics primitive), the CPU transmits an image to be displayed to the GRAM of the driver chip, and the driver chip refreshes data of the GRAM on an LCD screen. Based on this, for making the MCU mode can be applicable to big display screen, this application embodiment has provided the drive circuit of big display screen, through expand a video memory module on drive module to solve under the MCU mode because of the not enough problem that only is applicable to comparatively little display screen of video memory capacity.
Specifically, the driving module in this embodiment includes a first interface unit, a data buffer unit, a video memory control unit, a data flow control unit, and a second interface unit;
the input end of the first interface unit is connected with the output end of the processing module, and the output end of the first interface unit is connected with the input end of the data flow control unit and used for the data flow control unit to communicate with the processor core and receive image data;
the data flow control unit is used for controlling the whole driving process (receiving image data, storing the image data into the video memory module and refreshing the image data in the video memory module on the display screen), so that the output end of the data flow control unit is used for being connected with the input ends of the display screen, the video memory control unit and the data cache unit;
the video memory control unit is used for controlling the data read-write process of the video memory module, so that the output end of the video memory control unit is connected with the input end of the video memory module;
and the data cache unit is used for matching the image data reading speed in the display memory module with the image data refreshing speed of the LCD display screen, so that the output end of the data cache unit is connected with the input end of the second interface unit, and the output end of the second interface unit is connected with the input end of the display screen.
In order to increase the versatility of the driving circuit, the following steps are performed: the driving module CAN be suitable for different types of processing modules and display screens, and the first interface unit is set to be a UART interface, a CAN interface or/and a 1553B interface; the second interface unit is set as an RGB interface, an LVDS interface or/and an MIPI interface.
Further, in order to reduce the circuit complexity of the driving circuit structure, the processing module and the driving module are integrated on one processing chip in the embodiments of the present application. Preferably, the processing chip is set as an SOPC chip, and the SOPC chip combines the advantages of the SOC, the FPGA and the CPLD. The system basically comprises the common contents of an SOC chip, including a core (core), a memory, a peripheral interface (including a high-speed peripheral and a low-speed peripheral), a bus, a clock module, an interrupt module, a bus and the like; and enough on-chip programmable logic resources such as CPLDs and FPGAs are also included, and the CPLDs and the FPGAs are connected through buses such as EMIF (external memory interface) buses. For example, an SOPC chip SM9B100MAL of national microelectronics, an internal processor core (core) is SM926, a 100 ten-thousand-gate FPGA is embedded, the two chips communicate with each other through a memory bus controlled by MEMCTL, the internal circuit not only comprises a 720kbit RAM, but also comprises an AHB bus, storage interfaces such as SDRAM, SRAM, FLASH and the like, and communication interfaces such as UART, CAN, 1553B and the like, and the circuit structure provided by the embodiment of the application CAN be completely suitable.
Furthermore, the type and type of the video memory module can be set according to actual needs, for example, the video memory module can be set to be an SDRAM memory, an SRAM memory or other memories.
In this embodiment, the video memory module is set as an SDRAM chip with controllable video memory size, so that the circuit interface can be applied to LCD screen display designs of various sizes, and the extensibility of the circuit structure is increased, that is, when the circuit interface is specifically used, the model of the SDRAM chip can be reasonably selected according to the size of an image to be expected to be stored, and the embodiment is not particularly limited.
The working principle of the present application is explained as follows:
as shown in fig. 4, during operation, the FPAG monitors the state of the processor Core (CPU), and if there is an image data update (the CPU transmits the image data to the FPGA), the data flow control unit suspends reading data from the video memory, and controls the video memory control unit to change the SDRAM memory to the write mode, so as to receive the updated image data; and if no image updating data exists, controlling the SDRAM to be in a reading mode, enabling the LCD screen control pin by the data flow control unit, and continuously refreshing the data in the SDRAM memory on the LCD screen by the data cache unit.
Example 2
The embodiment provides a display screen, which comprises a display panel and a driving circuit of the large display screen provided by the embodiment 1, wherein the output end of the display panel is connected with the input end of the driving module.
Specifically, the present embodiment is a 7-inch display screen driving circuit based on an SOPC chip SM9B100MAL, and the circuit connection relationship is as shown in fig. 5, where the internal main processor is an ARM926, and the SOPC chip internally includes a 100W gate FPGA (self-contained configuration chip). The SDRAM0 is used for data processing and storage during operation of the ARM926 and is irrelevant to display screen driving; the FPGA is used for expanding an RGB display screen interface, and when the LCD display screen interface is used specifically, an R signal line, a G signal line, a B signal line, a DE control pin, an HS control pin, a YS control pin and the like of the LCD display screen are connected with an IO pin of the FPGA; the video memory module has two options:
selecting 1: the SRAM0 is used as a driving video memory; the advantages are that: the FPGA control program is simple, and the image data stored in the SRAM can be read all the time without monitoring the state of a processor (the reason is that the SRAM is an asynchronous dual-port SRAM and supports one-end writing and the other-end reading). The disadvantages are as follows: SRAM is expensive and has a limit on capacity (18 Mbit here);
selecting 2: SDRAM1 serves as a video memory. The advantages are that: the price is cheap, and the capacity is great, can be used to bigger screen. If the display efficiency is pursued, the double SDRAM can be used as the double video memories, and when the image is updated in the processor, the video memories are switched to realize seamless switching of the images of the display screen. The disadvantages are that: the control is relatively cumbersome.
In the specific implementation process, the setting mode is not limited to the two setting modes, and corresponding selection can be performed according to requirements.
When the device works, the FPAG monitors the state of a processor Core (CPU), if image data are updated (the CPU transmits the image data to the FPGA), the data flow control unit suspends the reading of the data from the video memory, and simultaneously controls the video memory control unit to change an SDRAM memory into a writing mode so as to receive the updated image data; and if no image updating data exists, controlling the SDRAM to be in a reading mode, enabling the LCD screen control pin by the data flow control unit, and continuously refreshing the data in the SDRAM memory on the LCD screen by the data cache unit.
It should be noted that the above specific logic processing process is the prior art, and the present application does not relate to an improvement point of a program, and the improvement point of the present application lies in that, by mounting an SDRAM chip on an FPGA as an LCD screen display memory, a problem that the MCU mode is only applicable to a relatively small display screen due to insufficient display memory capacity is solved.
In the description of the present invention, it should be noted that the terms "first" and "second" are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it is also to be noted that, unless otherwise explicitly specified or limited, the term "connected" is to be interpreted broadly, for example, as a fixed connection, a detachable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present invention, and are not intended to limit the technical solution of the present invention, and the protection scope of the present invention is not limited thereto, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: those skilled in the art can still modify or easily conceive of changes in the technical solutions described in the foregoing embodiments or make equivalent substitutions for some technical features within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the present invention. Are all covered by the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A drive circuit of a large display screen comprises a processing module and a drive module connected with the processing module, and is characterized by further comprising a display memory module, wherein the display memory module is connected with the drive module; the processing module is used for transmitting image data to be displayed to the video memory module through the driving module; and the driving module is used for refreshing the image data in the display memory module on a display screen.
2. The driving circuit of claim 1, wherein the driving module comprises a first interface unit, a data buffer unit, a video memory control unit, a data flow control unit, and a second interface unit; the input end of the first interface unit is connected with the output end of the processing module, the output end of the first interface unit is connected with the input end of the data flow control unit, and the output end of the data flow control unit is used for connecting the display screen, the video memory control unit and the input end of the data cache unit; the output end of the video memory control unit is connected with the input end of the video memory module; the output end of the data cache unit is connected with the input end of the second interface unit, and the output end of the second interface unit is connected with the input end of the display screen.
3. The driving circuit of claim 1, wherein the display memory module is configured as an SDRAM memory or an SRAM memory.
4. The driving circuit of a large display screen according to claim 2, wherein the first interface unit comprises a UART interface, a CAN interface and a 1553B interface.
5. The driving circuit for large display screen according to claim 2, wherein the second interface unit comprises an RGB interface, an LVDS interface and an MIPI interface.
6. The driving circuit for large display screen according to any one of claims 1 to 5, wherein the processing module and the driving module are integrated on a single processing chip.
7. The driving circuit for large display screen according to claim 6, wherein the processing chip is configured as an SOPC chip.
8. The driving circuit of a large display screen according to claim 7, wherein the model of the SOPC chip is SM9B100 MAL.
9. A display screen comprising a display panel, characterized by further comprising a driving circuit of the large display screen according to any one of claims 1 to 8, wherein the input end of the display panel is connected with the output end of the driving module.
10. A display screen according to claim 9, wherein the interface of the display panel is an RGB interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221014266.8U CN217426348U (en) | 2022-04-27 | 2022-04-27 | Drive circuit of large display screen and display screen |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221014266.8U CN217426348U (en) | 2022-04-27 | 2022-04-27 | Drive circuit of large display screen and display screen |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217426348U true CN217426348U (en) | 2022-09-13 |
Family
ID=83184226
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221014266.8U Active CN217426348U (en) | 2022-04-27 | 2022-04-27 | Drive circuit of large display screen and display screen |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217426348U (en) |
-
2022
- 2022-04-27 CN CN202221014266.8U patent/CN217426348U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9123308B2 (en) | Display memory, driver circuit, display, and portable information device | |
| EP1359510B1 (en) | Data processing system and data processor | |
| EP2972761B1 (en) | Display co-processing | |
| US9240165B2 (en) | Display driver integrated circuit including first-in-first-out (FIFO) memories configured to receive display data from a distributor and output the display data to graphics memories a display system having the same, and a display data processing method thereof | |
| CN201788657U (en) | Liquid crystal display (LCD) controller based on Nios II soft-core central processing unit (CPU) | |
| CN110827777B (en) | Display panel driving device and configuration method thereof | |
| US8120599B2 (en) | Method of automatically recovering bit values of control register and LCD drive integrated circuit for performing the same | |
| CN105096877A (en) | Display panel display control method, device and circuit | |
| CN217426348U (en) | Drive circuit of large display screen and display screen | |
| US20240021239A1 (en) | Hardware Acceleration System for Data Processing, and Chip | |
| JP5115548B2 (en) | Semiconductor integrated circuit device | |
| US7102645B2 (en) | Graphics display controller providing enhanced read/write efficiency for interfacing with a RAM-integrated graphics display device | |
| JP2003108056A (en) | Display memory, driver circuit, and display device | |
| JP4916156B2 (en) | Semiconductor integrated circuit device | |
| CN203773915U (en) | Silicon-based liquid crystal display screen driving chip | |
| CN115101025A (en) | LCD control circuit supporting virtual frame buffering and control method thereof | |
| JP2004334151A (en) | Drive system of display | |
| US7366927B2 (en) | Method and device for handling requests for changing system mode | |
| EP1628282A1 (en) | Display controller with DRAM graphics memory | |
| CN215416630U (en) | System for realizing MIPI read-write | |
| CN113312020A (en) | Screen refreshing method for handheld device and handheld device | |
| CN219154365U (en) | Display system and vehicle | |
| JP2003122335A (en) | Display controller | |
| CN201146022Y (en) | Graphical display control apparatus | |
| JP2007011130A (en) | Lcd display controller |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |