CN217307779U - Time-of-flight image sensor pixel circuit and image sensor - Google Patents
Time-of-flight image sensor pixel circuit and image sensor Download PDFInfo
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- CN217307779U CN217307779U CN202220316061.9U CN202220316061U CN217307779U CN 217307779 U CN217307779 U CN 217307779U CN 202220316061 U CN202220316061 U CN 202220316061U CN 217307779 U CN217307779 U CN 217307779U
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Abstract
The utility model relates to a time-of-flight image sensor pixel circuit and image sensor, the pixel circuit includes photosensitive element, a plurality of reading control units and correction unit; the plurality of reading control units comprise a plurality of corresponding floating diffusion points and are used for respectively reading and controlling the charge signals transmitted by the photosensitive elements; one end of the correction unit is connected to the high-level voltage signal, and the other end of the correction unit is connected to the floating diffusion points corresponding to the plurality of reading control units; the correcting unit is used for resetting all the floating diffusion points to re-integrate when the potential of at least one floating diffusion point is lower than a preset voltage in the integration period, so that the interference of over-strong background light on the pixel circuit of the time-of-flight image sensor can be effectively reduced, and the charge signals transmitted by the photosensitive element can be read out smoothly.
Description
Technical Field
The application relates to the technical field of image sensors, in particular to a time-of-flight image sensor pixel circuit and an image sensor.
Background
The image sensor is an important component of a digital camera, and can be classified into a CCD (Charge Coupled Device) image sensor and a CMOS (complementary metal Oxide Semiconductor) image sensor according to the difference of elements. The CMOS image sensor has advantages of low power consumption, low cost, easy standardized production, etc., and is widely used in various fields.
A Time of flight (TOF) image sensor device, which is mainly applied to a system for acquiring a 3D image, measures a distance from an imaging target to an image sensing device by sensing a Time when light reaches an object from a light source and is reflected back to an image sensor based on an optical Time of flight, and can obtain a high-precision depth image by using each pixel of the Time of flight image sensor for distance measurement.
Specifically, when the image sensor receives strong background light, the voltage of a Floating Diffusion (FD) node in the pixel circuit of the image sensor drops sharply due to the interference of the strong background light, and when the voltage of the Floating Diffusion node drops below the turn-on voltage of the readout circuit, the readout circuit in the pixel circuit of the image sensor cannot be turned on normally, and the charge signal transmitted by the photodiode cannot be read out, thereby causing the failure of the entire pixel circuit.
Disclosure of Invention
In order to overcome at least the above-mentioned deficiencies of the prior art, it is an object of the present application to provide a time-of-flight image sensor pixel circuit and an image sensor.
In a first aspect, an embodiment of the present application provides a time-of-flight image sensor pixel circuit, where the time-of-flight image sensor pixel circuit includes a photosensitive element, a plurality of reading control units, and a correction unit;
the reading control units comprise a plurality of floating diffusion points and are used for respectively reading and controlling the charge signals transmitted by the photosensitive elements; one end of the correction unit is connected with a high-level voltage signal, and the other end of the correction unit is connected with the plurality of floating diffusion points; wherein the correction unit is used for resetting all the floating diffusion points simultaneously to re-integrate when the potential of at least one floating diffusion point is lower than a preset voltage during integration;
in a possible implementation manner, one end of the correction unit is connected to a high-level voltage signal, and the other end of the correction unit is connected to the plurality of floating diffusion points; the correction unit comprises a plurality of switching transistors and a logic judgment module; the first end of the switching transistor is connected with the high-level voltage signal; the second end of the switch transistor is connected with the floating diffusion point, and the control end of the switch transistor is connected with the logic judgment module; the logic judgment module is composed of at least one logic circuit and is used for outputting a control signal to enable the switch transistor to be conducted to reset all the floating diffusion points to re-integrate when the potential of at least one floating diffusion point is lower than the preset voltage;
in a possible implementation manner, the logic judgment module comprises at least two inverters and a nor gate circuit, wherein the inverters are connected with the floating diffusion point, the inverters are connected into the input end of the nor gate circuit, and the output end of the nor gate circuit is connected with the switching transistor;
in a possible implementation manner, the logic judgment module includes an inverter and a nand gate circuit, wherein an input end of the nand gate circuit is connected to the floating diffusion point, an output end of the nand gate circuit is connected to an input end of the inverter, and an output end of the inverter is connected to the switching transistor;
in a possible implementation manner, the logic judgment module only includes an and gate circuit, wherein an input end of the and gate circuit is connected to the floating diffusion point, and an output end of the and gate circuit is connected to the switching transistor;
in one possible implementation, the first switching transistor and the second switching transistor are P-type transistors;
in a possible implementation manner, the logic judgment module comprises at least two inverters and an or gate circuit, wherein the inverters are connected with the floating diffusion point, the inverters are connected into the input end of the or gate circuit, and the output end of the or gate circuit is connected with the switching transistor;
in one possible implementation manner, the logic judgment module only comprises a NAND gate circuit, wherein the input end of the NAND gate circuit is connected to the floating diffusion point, and the output end of the NAND gate circuit is connected with the switching transistor;
in a possible implementation manner, the nand gate circuit is formed by serially connecting at least one control transistor group and a bias transistor, the control transistor group comprises two serially connected control transistors, a control end of the bias transistor is connected with a bias voltage, the control transistor group is connected to the high-level voltage signal through the bias transistor, and the control transistor and the bias transistor are both N-type transistors;
in one possible implementation, the first switching transistor and the second switching transistor are N-type transistors;
in one possible implementation, the read control unit includes a reset transistor, a transmission transistor, and a signal output module; one end of the reset transistor is connected with the high-level voltage signal, and the other end of the reset transistor is connected with the floating diffusion point so as to reset the voltage of the floating diffusion point according to a reset control signal; the first end of the signal output module is connected with the high-level voltage signal, and the control end of the signal output module is respectively connected with the reset transistor and the floating diffusion point, so that the voltage signal input from the floating diffusion point is amplified and output;
in a possible implementation manner, the reading control unit includes a first reading control unit and a second reading control unit, and the first reading control unit and the second reading control unit are mirror-symmetric with respect to the photosensitive element;
in a possible implementation manner, the reading control unit further includes a third reading control unit and a fourth reading control unit, and the first reading control unit, the second reading control unit, the third reading control unit, and the fourth reading control unit are mirror-symmetric with respect to the photosensitive element;
in one possible implementation, the reset transistor is an N-type transistor;
in one possible implementation manner, the signal output module includes a source follower transistor, a first end of the source follower transistor is connected with the high-level voltage signal, a control end of the source follower transistor is connected to the floating diffusion point, a second end of the reset transistor and the correction unit, and a second end of the source follower transistor is connected with a corresponding output end;
in one possible implementation, the signal output module includes a row selection transistor, and the source follower transistor is connected in series with the row selection transistor and connected to the corresponding output terminal through the row selection transistor;
in a possible implementation manner, the pixel circuit further includes a dual conversion gain control module, the dual conversion gain control module is connected between the reset transistor and the floating diffusion point, the dual conversion gain control module at least includes a dual conversion gain control transistor and a capacitor, and the dual conversion gain control module is configured to implement switching between a low conversion gain mode and a high conversion gain mode;
in a possible implementation manner, the pixel circuit further includes a pixel reset transistor, a first end of the pixel reset transistor is connected to a ground signal, a second end of the pixel reset transistor is connected to a second end of the photosensitive element, a control end of the pixel reset transistor is connected to a pixel reset signal, and the pixel reset transistor is configured to perform charge clearing on the photosensitive element before the photosensitive element transmits a charge signal.
In a possible implementation manner, the reading control unit further includes a storage capacitor, a first plate of the storage capacitor is connected to the floating diffusion point, a second plate of the storage capacitor is connected to a ground signal, and the storage capacitor is configured to receive and store the charges generated by the photosensitive element after the correction unit corrects and resets the potential of at least one floating diffusion point lower than the preset voltage;
in a possible implementation manner, the preset voltage is a starting voltage of the signal output module;
in a second aspect, embodiments of the present application further provide a time-of-flight image sensor, which employs the aforementioned time-of-flight image sensor pixel circuit.
In one possible implementation, the time-of-flight image sensor includes a first chip and a second chip, wherein: the photosensitive element and the transmission transistor are arranged on the first chip; the device structure of the reading control unit except the transmission transistor and the correction unit are arranged on a second chip; the first chip and the second chip are arranged in a stacked mode, and the first chip and the second chip are electrically connected;
in one possible implementation, the first chip is further provided with a pixel reset transistor;
based on any one of the above aspects, the time-of-flight image sensor pixel circuit, the driving method thereof, and the image sensor provided in the embodiments of the present application have the following beneficial effects: when the electric potential of at least one floating diffusion point is lower than the preset voltage in the integration period, all the floating diffusion points are reset simultaneously to re-integrate, and then when the background light is too strong, the interference of the too strong background light to the pixel circuit of the time-of-flight image sensor is effectively reduced, so that the charge signal transmitted by the photosensitive element can be normally conducted and smoothly read out.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that need to be called in the embodiments are briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a schematic diagram of a pixel circuit of an image sensor in the prior art;
FIG. 2 is a schematic diagram of a pixel circuit of a time-of-flight image sensor according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of another time-of-flight image sensor pixel circuit provided in an embodiment of the present application;
FIG. 4 is a schematic diagram of a pixel circuit of a time-of-flight image sensor provided by an embodiment of the present application;
FIG. 5 is a schematic diagram of a pixel circuit of a time-of-flight image sensor according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a pixel circuit of a time-of-flight image sensor according to an embodiment of the present application;
FIG. 7 is a schematic view of another time-of-flight image sensor pixel circuit provided in an embodiment of the present application;
FIG. 8 is a schematic diagram of a pixel circuit of a time-of-flight image sensor according to an embodiment of the present application;
FIG. 9 is a schematic diagram of a pixel circuit of a further time-of-flight image sensor according to an embodiment of the present application;
FIG. 10 is a timing diagram of a pixel circuit of a time-of-flight image sensor according to an embodiment of the present disclosure;
FIG. 11 is a timing diagram of another time-of-flight image sensor pixel circuit provided in an embodiment of the present application;
fig. 12 is a schematic view of a time-of-flight image sensor according to an embodiment of the present application.
Detailed Description
In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it should be understood that the drawings in the present application are for illustrative and descriptive purposes only and are not used to limit the scope of protection of the present application. Additionally, it should be understood that the schematic drawings are not necessarily drawn to scale. The flowcharts used in this application illustrate operations implemented according to some of the embodiments of the present application. It should be understood that the operations of the flow diagrams may be performed out of order, and that steps without logical context may be reversed in order or performed concurrently. In addition, one skilled in the art, under the guidance of the present disclosure, may add one or more other operations to, or remove one or more operations from, the flowchart.
In addition, the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
As described in the background art, when the image sensor receives strong background light, the voltage of a Floating Diffusion (FD) node in the pixel circuit of the image sensor drops sharply due to the interference of the strong background light, and when the voltage of the Floating Diffusion point drops below the turn-on voltage of the readout circuit, the readout circuit in the pixel circuit of the image sensor cannot be turned on normally, and the charge signal transmitted by the photodiode cannot be read out, thereby causing the whole pixel circuit to fail. Fig. 1 illustrates a pixel circuit of a conventional image sensor in the prior art, in which RST0 is a reset transistor, TX0 is a transfer transistor, PD0 is a photodiode, FD0 is a floating diffusion point, and Pixout is a second terminal, and the voltage level of the floating diffusion point FD0 is proportional to the voltage level of the second terminal Pixout; RST0 is a control signal of a reset transistor RST0, TX0 is a control signal of a transfer transistor TX0, when RST0 is at a high level, the reset transistor RST0 is turned on, the reset transistor RST0 outputs a reset signal to the floating diffusion point FD0 and the second end Pixout, and the reset signal of the floating diffusion point FD0 or the second end Pixout is sampled to be used as a reset sampling signal value Vrst; when TX0 is at a high level, the transfer transistor TX0 is turned on, the transfer transistor TX0 outputs the charge signal of the photodiode PD0 to the floating diffusion point FD0 and the second terminal Pixout, and the charge signal of the floating diffusion point FD0 or the second terminal Pixout is sampled as the photoelectron sampling signal value Vfd. The difference value between the reset sampling signal value Vrst and the photoelectron sampling signal value Vfd is an image signal, and the larger the charge signal is, the stronger the light is, and the larger the difference value between the reset sampling signal value Vrst and the photoelectron sampling signal value Vfd is. When the background light is too strong, the photodiode PD0 receives an incident signal from the external light and also receives a part of the background light signal, and the background light is too strong, which tends to saturate the output of the photodiode PD0, but the photo-generated charge of the incident signal is actually very little in the charge signal actually output by the photodiode PD0, so that the voltages of the floating diffusion point FD0 and the second terminal Pixout will drop rapidly after reset, the reset sampling signal value Vrst will also drop rapidly, and when the voltage of the floating diffusion point FD0 drops below the turn-on voltage of the readout circuit, the readout circuit in the pixel circuit of the image sensor will not be turned on normally; since the difference between the reset sampling signal value Vrst and the photoelectron sampling signal value Vfd, which are image signals, is greatly reduced due to such a difference, the charge signal transferred from the photodiode FD0 may not be read.
In order to solve the above technical problem, the present application provides a time-of-flight image sensor pixel circuit, where a pixel array of the time-of-flight image sensor includes a plurality of pixel circuits arranged in rows and columns. Referring to fig. 2, fig. 2 shows a time-of-flight image sensor pixel circuit provided in an embodiment of the present application, which includes a photosensitive element PD, a first reading control unit RC1, a second reading control unit RC2, and a correction unit CLB; the photosensitive element PD generally has a unidirectional conductive characteristic, and is used for accumulating charges generated by a photoelectric effect to respond to received light so as to convert an optical signal into an electrical signal, and the photosensitive element PD may be any photosensitive structure for converting a visible light signal into an electrical signal (i.e., optical charge), such as any one of a photodiode, a grating, or a photoconductor, as a better implementation, the photosensitive element PD in this embodiment is a photodiode; the photosensitive element PD has a first terminal and a second terminal, wherein the second terminal is connected to the first read control unit RC1 and the second read control unit RC2, respectively, and the first terminal is connected to the ground signal GND; further, the second end of the photosensitive element PD may be a cathode and the first end may be an anode.
The first reading control unit RC1 and the second reading control unit RC2 are respectively connected to the photosensitive element PD, each of which includes a floating diffusion point, a reset transistor, a transfer transistor, and a signal output module, and are all configured to perform reading control on a charge signal transferred by the photosensitive element PD.
One end of the reset transistor is connected with the high-level voltage signal, and the other end of the reset transistor is connected with the floating diffusion point so as to reset the voltage of the floating diffusion point according to the reset control signal; the first end of the signal output module is connected with a high-level voltage signal, and the control end of the signal output module is respectively connected with the reset transistor and the floating diffusion point, so that the voltage signal input from the floating diffusion point is amplified and output.
The following is specifically described with reference to fig. 2: the first read control unit RC1 includes a first floating diffusion point FDA, a first reset transistor RSTA, a first transfer transistor TXA, and a first signal output module; one end of the first reset transistor RSTA is connected with a high-level voltage signal VDD, and the other end of the first reset transistor RSTA is connected with a first floating diffusion point FDA; the first end of the first signal output module is connected with a high-level voltage signal VDD, and the control end of the first signal output module is connected with the first reset transistor RSTA and the first floating diffusion point FDA; the first reset transistor RSTA is used for resetting the voltage of the first floating diffusion point FDA according to a reset control signal RSTA, and the first signal output module is used for amplifying and outputting a voltage signal input from the first floating diffusion point FDA; the first transfer transistor TXA connects the photo sensor PD to the first floating diffusion point FDA to ensure that when the transfer signal pga is inputted, the first transfer transistor TXA is turned on to transfer the accumulated charges of the photo sensor PDA to the first floating diffusion point FDA.
With reference to fig. 2, the second read control unit RC2 includes a second floating diffusion point FDB, a second reset transistor RSTB, a second transmission transistor TXB, and a second signal output module; one end of the second reset transistor RSTB is connected to the high level voltage signal VDD, and the other end of the second reset transistor RSTB is connected to the second floating diffusion point FDB; the first end of the second signal output module is connected with a high-level voltage signal VDD, and the control end of the second signal output module is connected with the second reset transistor RSTB and the second floating diffusion point FDB; the second reset transistor RSTB is used for resetting the voltage of the second floating diffusion point FDB according to a reset control signal RSTB, and the second signal output module is used for amplifying and outputting a voltage signal input from the second floating diffusion point FDB; the second transfer transistor TXB connects the photo sensing element PD to the second floating diffusion point FDB to ensure that when the transfer signal pgb is input, the first transfer transistor TXB is turned on to transfer the accumulated charges of the photo sensing element PDB to the second floating diffusion point FDB.
It is understood that the first read control unit RC1 and the second read control unit RC2 are mirror-symmetrical about the photosensitive element PD.
Alternatively, the reset transistor may be a P-type transistor; in some embodiments, it may also be an N-type transistor. The hole mobility of the P-type transistor is low, and the transconductance of the P-type transistor is smaller than that of the N-type transistor under the condition that the geometric dimension of the MOS transistor is equal to the absolute value of the working voltage; however, the absolute value of the threshold voltage of the P-type transistor is generally higher, a higher working voltage is required, the voltage and polarity of the power supply are not compatible with the logic circuit of the bipolar transistor, the logic swing is large, the charging and discharging process is long, and the transconductance of the device is small, so that the working speed of the N-type transistor is higher than that of the P-type transistor.
Further, the correction unit CLB is connected to the high-level voltage signal VDD, the first read control unit RC1, and the second read control unit RC2, respectively; one end of the correction unit CLB is connected to the high-level voltage signal VDD, the other end of the correction unit CLB is connected to the first floating diffusion point FDA and the second floating diffusion point FDB, and the correction unit CLB is configured to reset the first floating diffusion point FDA and the second floating diffusion point FDB to re-integrate when at least one of a potential of the first floating diffusion point FDA and a potential of the second floating diffusion point FDB is lower than a preset voltage during integration.
Specifically, the correction unit CLB includes a first switching transistor CSTA, a second switching transistor CSTB, and a logic judgment module. The first terminal of the first switching transistor CSTA and the first terminal of the second switching transistor CSTB are both connected to the high-level voltage signal VDD; the second end of the first switching transistor CSTA is connected to the first floating diffusion point FDA, and the control end is connected with the logic judgment module; the second switch transistor CSTB has a second terminal connected to the second floating diffusion point FDB, and a control terminal connected to the logic determination module. The first switching transistor CSTA and the second switching transistor CSTB are the same type of transistor; because the control ends of the first switching transistor CSTA and the second switching transistor CSTB are both connected to the logic judgment module, and the first switching transistor CSTA and the second switching transistor CSTB are transistors of the same type, when the logic judgment module outputs a signal, the first switching transistor CSTA and the second switching transistor CSTB can be turned on or off at the same time according to the signal output by the logic judgment module; the first switch transistor CSTA conducts a high-level voltage signal VDD and a first floating diffusion point FDA when receiving a control signal output by the logic judgment module, so that the first floating diffusion point FDA is reset again; the second switch transistor CSTB conducts the high-level voltage signal VDD and the second floating diffusion point FDB when receiving the control signal output by the logic determination module, thereby resetting the second floating diffusion point FDB again; the first end of the logic judgment module is respectively connected with the first floating diffusion point FDA and the second floating diffusion point FDB, the second end of the logic judgment module is respectively connected with the first switch transistor CSTA and the second switch transistor CSTB, and the logic judgment module is used for controlling the first switch transistor CSTA and the second switch transistor CSTB to simultaneously perform secondary resetting on the first floating diffusion point FDA and the second floating diffusion point FDB respectively so as to perform integration again when at least one of the electric potential of the first floating diffusion point FDA and the electric potential of the second floating diffusion point FDB is lower than a preset voltage.
It is understood that the preset voltage is usually the turn-on voltage of the signal output module. In other words, when at least one of the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB is lower than the turn-on voltage of the signal output module, the logic decision module controls the first switching transistor CSTA and the second switching transistor CSTB to simultaneously perform a second reset on the first floating diffusion point FDA and the second floating diffusion point FDB, respectively, to re-integrate. Specifically, at least one of the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB is lower than the turn-on voltage of the signal output block, either one of the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB is lower than the turn-on voltage of the signal output block, or both the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB are lower than the turn-on voltage of the signal output block. Through the arrangement, the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB can be ensured to be in a state higher than the starting voltage (namely preset voltage) of the signal output module, the interference of the over-strong background light on the pixel circuit of the time-of-flight image sensor is effectively reduced, and under the premise, the signal output module can be normally conducted and can smoothly read out the charge signal transmitted by the photosensitive element.
The pixel circuit of the time-of-flight image sensor further includes a pixel reset transistor AB, referring to fig. 2, the pixel reset transistor AB is connected to the photosensitive element PD, and is configured to perform charge clearing operation on the photosensitive element PD before the photosensitive element PD transmits a charge signal. Specifically, a first end of the pixel reset transistor AB is connected to the ground signal GND, a second end of the pixel reset transistor AB is connected to a second end of the photosensitive element PD, a control end of the pixel reset transistor AB is controlled by the pixel reset signal AB, the pixel reset transistor AB is controlled to be turned on by the pixel reset signal AB before the photosensitive element PD transmits a charge signal, and the second end of the photosensitive element PD is turned on by the reset transistor AB and the ground signal GND at the moment, so that redundant charges are grounded and cleared by the ground signal GND before the photosensitive element PD reads in the charge signal through the ground signal GND, and the voltage and charge clearing operation on the photosensitive element PD is completed.
Further, the signal output module includes a source follower transistor and a row select transistor. The first end of the source electrode following transistor is connected with a high-level voltage signal, the control end of the source electrode following transistor is connected to the floating diffusion point, and the second end of the source electrode following transistor can be connected with a corresponding output end, and also can be connected with the row selecting transistor in series and connected with the corresponding output end through the row selecting transistor; meanwhile, the control end of the source follower transistor is also connected with the second end of the reset transistor and the correction unit CLB; in some embodiments, the source follower transistor is connected to the row selection transistor, and the charge signal output by the first floating diffusion point or the second floating diffusion point can be led in by the source follower transistor, amplified and then led out to the corresponding output end through the row selection transistor.
The following is specifically described with reference to fig. 2:
the first signal output module comprises a first source follower transistor SFA and a first row selection transistor RSA, wherein the first end of the first source follower transistor SFA is connected with a high-level voltage signal VDD, the second end of the first source follower transistor SFA can be directly connected with a corresponding output end, and can also be connected with the first end of the first row selection transistor RSA, so that the first source follower transistor SFA and the first row selection transistor RSA can be connected in series, the control end of the first source follower transistor SFA is connected to a first floating diffusion point FDA, and meanwhile, the first source follower transistor SFA and the second end of the first reset transistor RSTA are connected with a correction unit CLB, namely the second end of the first switch transistor CSTA and the logic judgment module are connected; the second end of the first row selection transistor RSA is connected with the corresponding output end, so that the first source follower transistor SFA can connect the high-level voltage signal VDD with the first row selection transistor RSA; the second signal output module comprises a second source follower transistor SFB and a second row selection transistor RSB, wherein the first end of the second source follower transistor SFB is connected with a high-level voltage signal VDD, the second end of the second source follower transistor SFB can be directly connected with a corresponding output end or connected with the first end of the second row selection transistor RSB, so that the second source follower transistor SFB and the second row selection transistor RSB can be connected in series, the control end of the second source follower transistor SFB is connected to the first floating diffusion point FDB, and meanwhile, the second source follower transistor SFB is also connected with the second end of the first reset transistor RSTB and the correction unit CLB, namely the second end of the first switch transistor CSTB is connected with the logic judgment module; the second terminal of the second row selection transistor RSB is connected to the corresponding output terminal, so that the second source follower transistor SFB can connect the high-level voltage signal VDD to the second row selection transistor RSB.
It should be noted that fig. 2 is only a typical example of the pixel circuit of the time-of-flight image sensor provided in the present application, and actually, the signal output module may also include only a source follower transistor, that is, only a first source follower transistor SFA and a second source follower transistor SFB, through which the charge signal transferred by the floating diffusion point can be amplified and directly derived, and similarly, other amplifying devices with different gains may be adopted instead of the row selecting transistor shown in fig. 2, for example, a junction field effect transistor or a differential amplifier, as long as the voltage signal input from the floating diffusion point can be amplified and output, and this embodiment of the present application does not specifically limit this.
In the pixel circuit of the image sensor with time of flight provided by the present application, the logic determination module is composed of at least one logic circuit, and is configured to output a control signal to turn on the first switching transistor CSTA and the second switching transistor CSTB to reset the first floating diffusion point FDA and the second floating diffusion point FDB when at least one of a potential of the first floating diffusion point FDA and a potential of the second floating diffusion point FDB is lower than a preset voltage. Fig. 2 shows one logic judgment module structure, which includes two inverters and a nor gate, and the following is specifically described: in the time-of-flight image sensor pixel circuit shown in fig. 2, the logic decision module includes a first inverter INVA connected to the first floating diffusion point FDA, a second inverter INVB connected to the second floating diffusion point FDB, and a NOR circuit NOR having an output terminal connected to both the first switching transistor CSTA and the second switching transistor CSTB.
Further, in the time-of-flight image sensor pixel circuit shown in fig. 2, the first switching transistor CSTA, the second switching transistor CSTB, the first reset transistor RSTA, and the second reset transistor RSTB are P-type transistors. Therefore, when the potential of at least one of the first floating diffusion point FDA and the second floating diffusion point FDB is lower than the turn-on voltage of the signal output module, the logic determining module may detect whether the voltage of the first floating diffusion point FDA and the second floating diffusion point FDB is lower than the turn-on voltage of the signal output module when receiving the voltage of the first floating diffusion point FDA and the second floating diffusion point FDB, and if the voltage of the first floating diffusion point FDA and the second floating diffusion point FDB is lower than the turn-on voltage of the signal output module, the logic determining module controls the first switching transistor CSTA and the second switching transistor CSTB to be turned on, and the high-level voltage signal VDD simultaneously resets the first floating diffusion point FDA and the second floating diffusion point FDB through the first switching transistor CSTA and the second switching transistor CSTB; the following cases can be specifically classified:
in a first case, when the potentials of the first floating diffusion point FDA and the second floating diffusion point FDB are both higher than the turn-on voltage of the signal output module, the first floating diffusion point FDA and the second floating diffusion point FDB both output high level signals, the high level signal output from the first floating diffusion point FDA is converted into a low level signal through the first inverter INVA and the high level signal output from the second floating diffusion point FDB is converted into a low level signal through the second inverter INVB and the NOR circuit NOR, and since the voltage signals received by the NOR circuit NOR are both low level signals, the high level signal is output to the first switching transistor CSTA and the second switching transistor CSTB, as described above, the first switching transistor CSTA and the second switching transistor CSTB are both P-type transistors, and the P-type transistor is turned on when the control terminal receives a low level signal, therefore, when the control terminal of the first switching transistor CSTA and the control terminal of the second switching transistor CSTB both receive a high level signal, the first switching transistor CSTA and the second switching transistor CSTB both maintain a turn-off state, and the potential of the first floating diffusion point FDA and the second floating diffusion point FDB are not reset for a second time;
in the second case, when any one of the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB is lower than the turn-on voltage of the signal output module, for example, the potential of the first floating diffusion point FDA is lower than the turn-on voltage of the signal output module, the first floating diffusion point FDA outputs a low level signal, the second floating diffusion point FDB outputs a high level signal, the low level signal output from the first floating diffusion point FDA is converted into a high level signal by the first inverter INVA, the high level signal output from the second floating diffusion point FDB is converted into a low level signal by the second inverter INVB, and since the voltage signal received by the NOR gate circuit NOR has both a low level signal and a high level signal, the low level signal is output to the first switching transistor CSTA and the second switching transistor CSTB, as described above, the first switch transistor CSTA and the second switch transistor CSTB are both P-type transistors, and the P-type transistors are conducted when the control ends receive low level signals, so that when the control ends of the first switch transistor CSTA and the second switch transistor CSTB both receive the low level signals, the first switch transistor CSTA and the second switch transistor CSTB are both in a conducting state, and a high level voltage signal VDD is written into the first floating diffusion point FDA and the second floating diffusion point FDB through the first switch transistor CSTA and the second switch transistor CSTB respectively to simultaneously perform secondary reset on the first floating diffusion point FDA and the second floating diffusion point FDB;
in the third case, when both the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB are lower than the turn-on voltage of the signal output module, the first floating diffusion point FDA and the second floating diffusion point FDB both output low level signals, the low level signal output from the first floating diffusion point FDA is converted into a high level signal by the first inverter INVA and is input to the NOR circuit NOR, and the low level signal output from the second floating diffusion point FDB is converted into a high level signal by the second inverter INVB and is input to the NOR circuit NOR, since the voltage signals received by the NOR circuit NOR are high level signals, low level signals are output to the first switching transistor CSTA and the second switching transistor CSTB, as described above, the first switching transistor CSTA and the second switching transistor CSTB are P-type transistors, and the P-type transistors are turned on when the control terminal receives a low level signal, therefore, when the control terminal of the first switch transistor CSTA and the control terminal of the second switch transistor CSTB both receive the low level signal, the first switch transistor CSTA and the second switch transistor CSTB are both in a conductive state, and the high level voltage signal VDD is written into the first floating diffusion point FDA and the second floating diffusion point FDB through the first switch transistor CSTA and the second switch transistor CSTB respectively to perform secondary reset on the first floating diffusion point FDA and the second floating diffusion point FDB at the same time.
In the time-of-flight image sensor pixel circuit provided by the present application, as shown in fig. 3, the logic determination module may further include an inverter and a nand gate, specifically: the logic judgment module comprises an inverter INV and a NAND gate circuit NAND, wherein the input end of the NAND gate circuit NAND is connected to the first floating diffusion point FDA and the second floating diffusion point FDB, the output end of the NAND gate circuit NAND is connected to the input end of the inverter INV, and the output end of the inverter INV is simultaneously connected with the first switch transistor CSTA and the second switch transistor CSTB.
In the time-of-flight image sensor pixel circuit shown in fig. 3, the first switching transistor CSTA, the second switching transistor CSTB, the first reset transistor RSTA, and the second reset transistor RSTB are P-type transistors, as in the embodiment shown in fig. 2. Therefore, when the potential of at least one of the first floating diffusion point FDA and the second floating diffusion point FDB is lower than the turn-on voltage of the signal output module, the logic determination module may detect whether the voltage of the first floating diffusion point FDA and the second floating diffusion point FDB is lower than the turn-on voltage of the signal output module when receiving the voltage of the first floating diffusion point FDA and the second floating diffusion point FDB, and control the first switching transistor CSTA and the second switching transistor CSTB to be turned on if the voltage of the first floating diffusion point FDA and the second floating diffusion point FDB is lower than the turn-on voltage of the signal output module, and the high-level voltage signal VDD simultaneously resets the first floating diffusion point FDA and the second floating diffusion point FDB through the first switching transistor CSTA and the second switching transistor CSTB. The specific case is as follows:
in the first case, when the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB are both higher than the turn-on voltage of the signal output module, the first floating diffusion point FDA and the second floating diffusion point FDB both output a high level signal to the NAND gate circuit NAND, and because the voltage signal received by the NAND gate circuit NAND is a high level signal, a low level signal is output to the inverter INV, and the inverter INV converts the low level signal output by the NAND gate circuit NAND into a high level signal and outputs the high level signal to the first switching transistor CSTA and the second switching transistor CSTB; as described above, the first switching transistor CSTA and the second switching transistor CSTB are both P-type transistors, and the P-type transistors are turned on when the control terminal receives a low level signal, so that when the control terminal of the first switching transistor CSTA and the control terminal of the second switching transistor CSTB both receive a high level signal, the first switching transistor CSTA and the second switching transistor CSTB both maintain the off state, and the potential of the first floating diffusion point FDA and the second floating diffusion point FDB are not reset for the second time;
in the second case, when any one of the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB is lower than the turn-on voltage of the signal output module, for example, when the potential of the first floating diffusion point FDA is lower than the turn-on voltage of the signal output module, the first floating diffusion point FDA outputs a low level signal to the NAND gate circuit NAND, and the second floating diffusion point FDB outputs a high level signal to the NAND gate circuit NAND; as described above, the first switch transistor CSTA and the second switch transistor CSTB are both P-type transistors, and the P-type transistors are turned on when the control terminal receives a low level signal, so that when the control terminal of the first switch transistor CSTA and the control terminal of the second switch transistor CSTB both receive a low level signal, the first switch transistor CSTA and the second switch transistor CSTB are both in a turned-on state, and the high level voltage signal VDD is written into the first floating diffusion point FDA and the second floating diffusion point FDB through the first switch transistor CSTA and the second switch transistor CSTB respectively to perform secondary reset on the first floating diffusion point FDA and the second floating diffusion point FDB at the same time;
in a third situation, when both the electric potential of the first floating diffusion point FDA and the electric potential of the second floating diffusion point FDB are lower than the turn-on voltage of the signal output module, the first floating diffusion point FDA and the second floating diffusion point FDB both output low level signals to the NAND gate circuit NAND, and because the voltage signals received by the NAND gate circuit NAND are both low level signals, high level signals are output to the inverter INV, and the inverter INV converts the high level signals output by the NAND gate circuit NAND into low level signals and outputs the low level signals to the first switching transistor CSTA and the second switching transistor CSTB; as described above, the first switch transistor CSTA and the second switch transistor CSTB are both P-type transistors, and the P-type transistors are turned on when the control terminal receives the low level signal, so that when the control terminal of the first switch transistor CSTA and the control terminal of the second switch transistor CSTB both receive the low level signal, the first switch transistor CSTA and the second switch transistor CSTB are both in a turned-on state, and the high level voltage signal VDD is written into the first floating diffusion point FDA and the second floating diffusion point FDB through the first switch transistor CSTA and the second switch transistor CSTB, respectively, to perform the secondary reset on the first floating diffusion point FDA and the second floating diffusion point FDB at the same time.
Therefore, the number of devices in the logic decision block can be reduced by changing the internal configuration of the logic decision block and replacing the internal configuration with an inverter and a nand gate circuit without changing the transistor type of the first switching transistor CSTA and the second switching transistor CSTB shown in fig. 2 to P-type transistors, thereby simplifying the internal configuration of the logic decision block.
In the pixel circuit of the time-of-flight image sensor provided by the present application, as shown in fig. 4, the logic determination module may only include one and gate circuit, specifically: the logic decision block includes an AND circuit AND, wherein an input terminal of the AND circuit AND is connected to the first floating diffusion point FDA AND the second floating diffusion point FDB, AND an output terminal of the AND circuit AND is simultaneously connected to the first switching transistor CSTA AND the second switching transistor CSTB.
In the pixel circuit of the time-of-flight image sensor provided in this embodiment, the first switching transistor CSTA, the second switching transistor CSTB, the first reset transistor RSTA, and the second reset transistor RSTB are P-type transistors. Further, the specific situations of the pixel circuit of the time-of-flight image sensor shown in fig. 4 controlling the first reset transistor RSTA and the second reset transistor RSTB to perform the secondary reset can be classified into the following:
in the first case, when both the potential of the first floating diffusion point FDA AND the potential of the second floating diffusion point FDB are higher than the turn-on voltage of the signal output module, both the first floating diffusion point FDA AND the second floating diffusion point FDB output high level signals to the AND circuit AND, because both the voltage signals received by the AND circuit AND are high level signals, output high level signals to the first switching transistor CSTA AND the second switching transistor CSTB; as described above, the first switching transistor CSTA and the second switching transistor CSTB are both P-type transistors, and the P-type transistors are turned on when the control terminal receives a low level signal, so that when the control terminal of the first switching transistor CSTA and the control terminal of the second switching transistor CSTB both receive a high level signal, the first switching transistor CSTA and the second switching transistor CSTB both maintain the off state, and the potential of the first floating diffusion point FDA and the second floating diffusion point FDB are not reset for the second time;
in a second case, when any one of the potential of the first floating diffusion point FDA AND the potential of the second floating diffusion point FDB is lower than the turn-on voltage of the signal output block, for example, the potential of the first floating diffusion point FDA is lower than the turn-on voltage of the signal output block, the first floating diffusion point FDA outputs a low level signal to the AND circuit AND, the second floating diffusion point FDB outputs a high level signal to the AND circuit AND, AND since one of the voltage signals received by the AND circuit AND is a low level signal, outputs a low level signal to the first switching transistor CSTA AND the second switching transistor CSTB; the first switch transistor CSTA and the second switch transistor CSTB are both in a conducting state, and the high-level voltage signal VDD performs secondary reset on the first floating diffusion point FDA and the second floating diffusion point FDB through the first switch transistor CSTA and the second switch transistor CSTB respectively;
in a third case, when both the potential of the first floating diffusion point FDA AND the potential of the second floating diffusion point FDB are lower than the turn-on voltage of the signal output module, both the first floating diffusion point FDA AND the second floating diffusion point FDB output low level signals to the AND circuit AND, because both the voltage signals received by the AND circuit AND are low level signals, output low level signals to the first switching transistor CSTA AND the second switching transistor CSTB; the first switching transistor CSTA and the second switching transistor CSTB are both in a conductive state, and the high-level voltage signal VDD simultaneously resets the first floating diffusion point FDA and the second floating diffusion point FDB through the first switching transistor CSTA and the second switching transistor CSTB, respectively.
Therefore, on the premise that the transistor types of the first switching transistor CSTA and the second switching transistor CSTB shown in fig. 2 and 3 are not changed to P-type transistors, the internal configuration of the logic determination module is changed to be simplified to include only one and circuit, so that the number of devices of the logic determination module can be reduced, and the internal configuration of the logic determination module can be simplified.
Fig. 5 shows another logic determination module structure provided in the embodiment of the present application, which includes two inverters and an or gate circuit, and the following description specifically describes: the logic judgment module comprises a first inverter INVA, a second inverter INVB and an OR gate circuit OR, wherein the first inverter INVA is connected with a first floating diffusion point FDA, the second inverter INVB is connected with a second floating diffusion point FDB, the first inverter INVA and the second inverter INVB are connected into the input end of the OR gate circuit OR in parallel, and the output end of the OR gate circuit OR is simultaneously connected with a first switching transistor CSTA and a second switching transistor CSTB.
Further, in the time-of-flight image sensor pixel circuit shown in fig. 5, the switching transistor and the reset transistor may be different types of transistors, respectively, or may be the same type of transistor; specifically, the first switching transistor CSTA and the second switching transistor CSTB are N-type transistors, and the first reset transistor RSTA and the second reset transistor RSTB may be either P-type transistors or N-type transistors. Here, as an exemplary embodiment, the first and second switching transistors CSTA and CSTB may be N-type transistors, and the first and second reset transistors RSTA and RSTB may be P-type transistors. The specific situations of the pixel circuit of the time-of-flight image sensor shown in fig. 5 for controlling the first reset transistor RSTA and the second reset transistor RSTB to perform the secondary reset can be classified into the following cases:
in a first case, when the potentials of the first floating diffusion point FDA and the second floating diffusion point FDB are both higher than the turn-on voltage of the signal output module, the first floating diffusion point FDA and the second floating diffusion point FDB both output high level signals, the high level signal output by the first floating diffusion point FDA is converted into a low level signal through the first inverter IVA and the high level signal output by the second floating diffusion point FDB is converted into a low level signal through the second inverter IVB, and the high level signal output by the second floating diffusion point FDB is converted into a low level signal through the second inverter IVB When the control terminal of the second switching transistor CSTB receives a low level signal, the first switching transistor CSTA and the second switching transistor CSTB are both kept in a turned-off state, and the potential of the first floating diffusion point FDA and the second floating diffusion point FDB are not reset for the second time;
in the second case, when any one of the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB is lower than the turn-on voltage of the signal output module, for example, the potential of the first floating diffusion point FDA is lower than the turn-on voltage of the signal output module, the first floating diffusion point FDA outputs a low level signal, the second floating diffusion point FDB outputs a high level signal, the low level signal output from the first floating diffusion point FDA is converted into a high level signal input OR gate OR by the first inverter INVA, the high level signal output from the second floating diffusion point FDB is converted into a low level signal input OR gate OR by the second inverter INVB, and since the voltage signal received by the OR gate OR has both the low level signal and the high level signal, the high level signal is output to the first switching transistor CSTA and the second switching transistor CSTB, as described above, the first switch transistor CSTA and the second switch transistor CSTB are both N-type transistors, and the N-type transistors are conducted when the control end receives a high-level signal, so that when the control end of the first switch transistor CSTA and the control end of the second switch transistor CSTB both receive the high-level signal, the first switch transistor CSTA and the second switch transistor CSTB are both in a conducting state, and a high-level voltage signal VDD is written into the first floating diffusion point FDA and the second floating diffusion point FDB through the first switch transistor CSTA and the second switch transistor CSTB respectively to simultaneously perform secondary resetting on the first floating diffusion point FDA and the second floating diffusion point FDB;
in the third case, when both the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB are lower than the turn-on voltage of the signal output module, the first floating diffusion point FDA and the second floating diffusion point FDB both output low level signals, the low level signal output by the first floating diffusion point FDA is converted into a high level signal by the first inverter INVA and is input to the OR gate OR, the low level signal output by the second floating diffusion point FDB is converted into a high level signal by the second inverter INVB, and since the voltage signal received by the OR gate OR is a high level signal, a high level signal is output to the first switching transistor CSTA and the second switching transistor CSTB, as described above, the first switching transistor CSTA and the second switching transistor CSTB are both N-type transistors, and the N-type transistor is turned on when the control terminal receives a high level signal, therefore, when the control terminal of the first switch transistor CSTA and the control terminal of the second switch transistor CSTB both receive the high level signal, the first switch transistor CSTA and the second switch transistor CSTB are both in a conducting state, and the high level voltage signal VDD is written into the first floating diffusion point FDA and the second floating diffusion point FDB through the first switch transistor CSTA and the second switch transistor CSTB respectively to perform the secondary reset on the first floating diffusion point FDA and the second floating diffusion point FDB at the same time.
It is understood that the P-type transistors employed in the embodiments of the present application may be referred to as PMOS without objection; the N-type transistor employed in the embodiment of the present application may be referred to as NMOS without objection. Further, since the P-type transistor has low hole mobility, the transconductance of the P-type transistor is smaller than that of the N-type transistor under the condition that the geometric size of the MOS transistor and the absolute value of the operating voltage are equal; in addition, the absolute value of the threshold voltage of the P-type transistor is generally high, a higher working voltage is required, and the voltage and polarity of the power supply are not compatible with the logic circuit of the bipolar transistor. Therefore, the PMOS has large logic swing, long charging and discharging process and small transconductance of the device, so the working speed is lower compared with that of the NMOS. In the pixel circuit of the time-of-flight image sensor shown in fig. 5, the first switching transistor CSTA and the second switching transistor CSTB in the logic determination module are replaced by N-type transistors from the P-type transistors in the foregoing embodiments, which is beneficial to quickly respond when the first floating diffusion point FDA and the second floating diffusion point FDB both output low-level signal voltages and output high-level voltage signals VDD to the first floating diffusion point FDA and the second floating diffusion point FDB for secondary reset in time, so as to improve the operating speed of the pixel circuit of the time-of-flight image sensor provided by the present application.
In the pixel circuit of the time-of-flight image sensor provided by the present application, as shown in fig. 6, the logic determination module may include only one nand gate, specifically: the logic judgment module only comprises a NAND gate circuit NAND, wherein the input end of the NAND gate circuit NAND is connected to the first floating diffusion point FDA and the second floating diffusion point FDB, and the output end of the NAND gate circuit NAND is simultaneously connected with the first switching transistor CSTA and the second switching transistor CSTB.
In the pixel circuit of the time-of-flight image sensor provided in this embodiment, the switch transistor and the reset transistor may be different types of transistors, or may be the same type of transistors; specifically, the first switching transistor CSTA and the second switching transistor CSTB are N-type transistors, and the first reset transistor RSTA and the second reset transistor RSTB may be either P-type transistors or N-type transistors. Here, as an exemplary embodiment, the first switching transistor CSTA and the second switching transistor CSTB may be N-type transistors, and the first reset transistor RSTA and the second reset transistor RSTB may be P-type transistors. Further, the specific situations of the pixel circuit of the time-of-flight image sensor shown in fig. 6 for controlling the first reset transistor RSTA and the second reset transistor RSTB to perform the secondary reset can be classified into the following cases:
in the first case, when the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB are both higher than the turn-on voltage of the signal output module, the first floating diffusion point FDA and the second floating diffusion point FDB both output a high level signal to the NAND gate circuit NAND, and output a low level signal to the first switching transistor CSTA and the second switching transistor CSTB because the voltage signals received by the NAND gate circuit NAND are both high level signals; as described above, the first switch transistor CSTA and the second switch transistor CSTB are both N-type transistors, and the N-type transistors are turned on when the control terminal receives a low level signal, so that when the control terminal of the first switch transistor CSTA and the control terminal of the second switch transistor CSTB both receive a high level signal, the first switch transistor CSTA and the second switch transistor CSTB both maintain the off state, and the potential of the first floating diffusion point FDA and the second floating diffusion point FDB are not reset for the second time;
in the second case, when any one of the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB is lower than the turn-on voltage of the signal output module, for example, the potential of the first floating diffusion point FDA is lower than the turn-on voltage of the signal output module, the first floating diffusion point FDA outputs a low level signal to the NAND gate circuit NAND, and the second floating diffusion point FDB outputs a high level signal to the NAND gate circuit NAND; the first switch transistor CSTA and the second switch transistor CSTB are both in a conducting state, and the high-level voltage signal VDD simultaneously resets the first floating diffusion point FDA and the second floating diffusion point FDB through the first switch transistor CSTA and the second switch transistor CSTB, respectively;
in a third case, when both the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB are lower than the turn-on voltage of the signal output module, both the first floating diffusion point FDA and the second floating diffusion point FDB output low level signals to the NAND gate circuit NAND, and because both the voltage signals received by the NAND gate circuit NAND are low level signals, output high level signals to the first switching transistor CSTA and the second switching transistor CSTB; the first switching transistor CSTA and the second switching transistor CSTB are both in a conductive state, and the high-level voltage signal VDD simultaneously resets the first floating diffusion point FDA and the second floating diffusion point FDB through the first switching transistor CSTA and the second switching transistor CSTB, respectively.
Therefore, on the premise of not changing the transistor types of the first switching transistor CSTA and the second switching transistor CSTB shown in fig. 5 to be N-type transistors, on one hand, the internal structure of the logic determination module can be simplified to include only one NAND gate NAND by changing the internal structure of the logic determination module, so that the number of devices in the logic determination module can be reduced, and the internal structure of the logic determination module can be simplified, and on the other hand, when both the first floating diffusion point FDA and the second floating diffusion point FDB output low-level signal voltages, the logic determination module can respond faster and simultaneously output high-level voltage signals VDD to the first floating diffusion point FDA and the second floating diffusion point FDB for secondary reset, so as to improve the operating speed of the pixel circuit of the time-of-flight image sensor provided by the present application.
As a preferred embodiment, in order to further increase the operating speed of the pixel circuit of the time-of-flight image sensor, all the transistors in the logic determination circuit (i.e., NAND gate circuit NAND) disclosed in fig. 6 may be replaced by N-type transistors. Referring to fig. 7, an embodiment of the present invention further provides a time-of-flight image sensor pixel circuit, where all transistors forming a logic determination circuit in a logic determination module are N-type transistors, specifically, as shown in fig. 7, the logic determination circuit (i.e., NAND gate circuit NAND) is formed by connecting at least one control transistor group and a bias transistor in series, where: the control transistor group comprises a first logic control transistor LGTA with a control end connected to the first floating diffusion point FDA and a second logic control transistor LGTB with a control end connected to the second floating diffusion point FDB, and the first logic control transistor LGTA and the second logic control transistor LGTB are connected in series and jointly form a control transistor group; a first terminal of the first logic control transistor LGTA is connected to a ground signal GND, a second terminal of the first logic control transistor LGTA is connected to a first terminal of the second logic control transistor LGTB, and a second terminal of the second logic control transistor LGTB is connected to both a control terminal of the first switching transistor CSTA and a control terminal of the second switching transistor CSTB; the logic judgment circuit further comprises a bias transistor LGTC connected in series with the control transistor group, wherein a control end of the bias transistor LGTC is connected with a bias voltage signal Vbias, a first end of the control end of the bias transistor LGTC is connected with a high-level voltage signal VDD, and a second end of the control end of the bias transistor LGTC is simultaneously connected with a control end of the first switch transistor CSTA and a control end of the second switch transistor CSTB. It is understood that the number of the control transistor groups is at least one, and may also be multiple, and it is known that the logic control transistors included therein are paired and connected in series regardless of the number of the control transistor groups.
Further, the first logic control transistor LGTA, the second logic control transistor LGTB, and the bias transistor LGTC are all N-type transistors, and since the bias transistor LGTC is an N-type transistor, in order to ensure that it is turned on, the bias voltage signal Vbias connected to the control terminal thereof should be a preset positive bias signal. Accordingly, the specific situations of the pixel circuit of the time-of-flight image sensor shown in fig. 7 for controlling the first reset transistor RSTA and the second reset transistor RSTB to perform the secondary reset can be classified into the following cases:
in a first case, when the first floating diffusion point FDA and the second floating diffusion point FDB are both higher than the turn-on voltage of the signal output module, the first floating diffusion point FDA and the second floating diffusion point FDB both output high level signals, the high level signal output from the first floating diffusion point FDA is input to the first logic control transistor LGTA and the high level signal output from the second floating diffusion point FDB is input to the second logic control transistor LGTB, and when the first logic control transistor LGTA and the second logic control transistor LGTB both receive high level signals, the control terminal of the first switching transistor CSTA and the control terminal of the second switching transistor CSTB both receive low level signals transmitted by the ground signal GND, and since the first switching transistor CSTA and the second switching transistor CSTB are both N-type transistors, both the first switching transistor CSTA and the second switching transistor CSTB are turned on only under the premise of high level signal transmission, at this time, the first switching transistor CSTA and the second switching transistor CSTB are not turned on and do not perform secondary reset on the first floating diffusion point FDA and the second floating diffusion point FDB because of the low level signal transmitted by the ground signal GND received by the first switching transistor CSTA and the second switching transistor CSTB;
in a second case, when any one of the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB is lower than the turn-on voltage of the signal output block, for example, the potential of the first floating diffusion point FDA is lower than the turn-on voltage of the signal output block, the first floating diffusion point FDA outputs a low level signal to the first logic control transistor LGTA, and since the first logic control transistor LGTA is an N-type transistor, the first logic control transistor LGTA is not turned on by receiving the low level signal, and further, since the first logic control transistor LGTA is connected in series with the second logic control transistor LGTB, the low level signal transmitted by the ground signal GND cannot be output; meanwhile, a forward bias signal preset at the control terminal of the bias transistor LGTC turns on the bias transistor LGTC, and a high-level signal transmitted by the high-level voltage signal VDD is transmitted to the control terminal of the first switching transistor CSTA and the control terminal of the second switching transistor CSTB through the bias transistor LGTC; the first switch transistor CSTA and the second switch transistor CSTB are both in a conducting state, and the high-level voltage signal VDD simultaneously resets the first floating diffusion point FDA and the second floating diffusion point FDB through the first switch transistor CSTA and the second switch transistor CSTB, respectively;
in the third case, when both the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB are lower than the turn-on voltage of the signal output module, the first floating diffusion point FDA outputs a low level signal to the first logic control transistor LGTA, and the second floating diffusion point FDB outputs a low level signal to the second logic control transistor LGTB; meanwhile, a forward bias signal preset at the control terminal of the bias transistor LGTC turns on the bias transistor LGTC, and a high-level signal transmitted by the high-level voltage signal VDD is transmitted to the control terminal of the first switching transistor CSTA and the control terminal of the second switching transistor CSTB through the bias transistor LGTC, thereby simultaneously resetting the first floating diffusion point FDA and the second floating diffusion point FDB for the second time.
Through the arrangement, the internal structure of the logic judgment module can be simplified, and the working speed of the pixel circuit of the time-of-flight image sensor provided by the application can be further improved.
As an alternative embodiment, as shown in fig. 8, the present application provides a time-of-flight image sensor pixel circuit further comprising a dual conversion gain control module connected between the reset transistor and the floating diffusion point, wherein the dual conversion gain control module comprises at least one dual conversion gain control transistor and a capacitor, and the dual conversion gain control module is configured to switch between a low conversion gain mode and a high conversion gain mode, so as to control the exposure dynamic range of the time-of-flight image sensor. Specifically, the dual conversion gain control module comprises a first dual conversion gain control module and a second dual conversion gain control module; the first dual conversion gain control module comprises a first dual conversion gain control transistor DCGA and a capacitor Cdcga, the first dual conversion gain control transistor DCGA is connected between a first reset transistor RSTA and a first floating diffusion point FDA in series, and the lower pole plate of the capacitor Cdcga is connected between the first dual conversion gain control transistor DCGA and the first reset transistor RSTA; the second dual conversion gain control module includes a second dual conversion gain control transistor DCGB and a capacitor Cdcgb, the first dual conversion gain control transistor DCGB is connected in series between the first reset transistor RSTB and the first floating diffusion point FDB, and a lower plate of the capacitor Cdcgb is connected between the first dual conversion gain control transistor DCGB and the first reset transistor RSTB; furthermore, the upper plates of the capacitor Cdcga and the capacitor Cdcgb are connected to a voltage VCA, which may be a high-level voltage signal VDD or a ground signal GND or other specified voltage value; the capacitance Cdcga and the capacitance Cdcgb may be device capacitances or parasitic capacitances to ground of the connection point of the reset transistor and the dual conversion gain transistor. By the arrangement, the conversion gain can be improved by a smaller integral capacitor under the condition of low illumination so as to improve the sensitivity; under the condition of high illumination, the storage charge is promoted by a larger integral capacitor, the conversion gain is reduced to improve the dynamic range, and then on the basis of ensuring that the logic judgment module performs secondary reset on the first floating diffusion point FDA and the second floating diffusion point FDB when the potential of the first floating diffusion point FDA or the potential of the second floating diffusion point FDB is lower than the starting voltage of the reading circuit, the size of the dynamic range is controlled, so that the interference of over-strong background light on the pixel circuit of the time-of-flight image sensor is further reduced, and the signal output module can be ensured to be normally conducted and smoothly read out the charge signal transmitted by the photosensitive element.
Optionally, in the pixel circuit of the time-of-flight image sensor provided by the present application, each of the first reading control unit and the second reading control unit includes a storage capacitor, a first plate of the storage capacitor is connected to a floating diffusion point, a second plate of the storage capacitor is connected to a ground signal, and the storage capacitor is configured to receive and store charges generated by the photosensitive element after the floating diffusion point of the correction unit is corrected to be lower than a preset voltage and reset to a higher potential. Specifically, the first read control unit RC1 further includes a storage capacitor CA, a first plate of the storage capacitor CA is connected to the floating diffusion point FDA, and a second plate of the storage capacitor CA is connected to the ground signal GND; the second reading control unit RC2 further includes a storage capacitor CB, a first plate of the storage capacitor CB is connected to the floating diffusion point FDB, and a second plate of the storage capacitor CB is connected to the ground signal GND; the first storage capacitor C1 and the second storage capacitor C2 are each configured to receive and store electric charges generated by the photosensitive element PD after the correction unit CLB corrects and resets the electric potentials lower than a preset voltage (typically, a turn-on voltage of the readout circuit) in the first floating diffusion point FDA and the second floating diffusion point FDB to a higher electric potential.
Referring to fig. 9, fig. 9 shows another time-of-flight image sensor pixel circuit of the present application, which further includes a third read control unit RC3 and a fourth read control unit RC 4; the second ends of the photosensitive elements are connected to the third and fourth reading control units RC3 and RC4, respectively.
The third read control unit RC3 and the fourth read control unit RC4 are respectively connected to the photosensitive element PD, each of which includes a floating diffusion point, a reset transistor, a transfer transistor, and a signal output module, and each of which is configured to read and control a charge signal transferred by the photosensitive element PD.
The following is specifically described with reference to fig. 9: the third read control unit RC3 includes a third floating diffusion point FDC, a third reset transistor RSTC, a third transfer transistor TXC, and a third signal output block; one end of a third reset transistor RSTC is connected with a high-level voltage signal VDD, and the other end of the third reset transistor RSTC is connected with a third floating diffusion point FDC; the first end of the third signal output module is connected with a high-level voltage signal VDD, and the control end of the third signal output module is connected with a third reset transistor RSTC and a third floating diffusion point FDC; the third reset transistor RSTC is configured to reset a voltage of the third floating diffusion point FDC according to the reset control signal RSTC, and the third signal output module is configured to amplify and output a voltage signal input from the third floating diffusion point FDC; the third transfer transistor TXC connects the photo-sensing element PD to the third floating diffusion point FDC to ensure that when the transfer signal pgc is input, the third transfer transistor TXC is turned on to transfer the accumulated charge of the photo-sensing element PDA to the third floating diffusion point FDC.
With reference to fig. 9, the fourth read control unit RC4 includes a fourth floating diffusion FDD, a fourth reset transistor RSTD, a fourth transmission transistor TXD, and a fourth signal output block; one end of a fourth reset transistor RSTD is connected to the high-level voltage signal VDD, and the other end of the fourth reset transistor RSTD is connected to a fourth floating diffusion point FDD; the first end of the fourth signal output module is connected with a high-level voltage signal VDD, and the control end of the second signal output module is connected with a fourth reset transistor RSTD and a fourth floating diffusion point FDD; the fourth reset transistor RSTD is configured to reset a voltage of the fourth floating diffusion point FDD according to a reset control signal RSTD, and the fourth signal output module is configured to amplify and output a voltage signal input from the fourth floating diffusion point FDD; the fourth transfer transistor TXD couples the photo-sensing element PD to the fourth floating diffusion point FDD to ensure that when transfer signal pgd is input, the first transfer transistor TXB is turned on to transfer the accumulated charge from the photo-sensing element PDB to the fourth floating diffusion point FDD.
Alternatively, the reset transistor may be a P-type transistor; in some embodiments, it may also be an N-type transistor.
Further, the correction unit CLB is connected to the high-level voltage signal VDD, the third read control unit RC3, and the fourth read control unit RC4, respectively; one end of the correction unit CLB is connected to the high-level voltage signal VDD, the other end of the correction unit CLB is connected to the third floating diffusion point FDC and the fourth floating diffusion point FDD, and the correction unit CLB is configured to reset all the floating diffusion points at the same time to re-integrate when at least one of the potential of the first floating diffusion point FDA, the potential of the second floating diffusion point FDB, the potential of the third floating diffusion point FDC, and the potential of the fourth floating diffusion point FDD is lower than a preset voltage during integration.
Specifically, the correction unit CLB further includes a third switching transistor CSTC, a fourth switching transistor CSTD, and a logic judgment module. The first end of the third switching transistor CSTC and the first end of the fourth switching transistor CSTD are both connected to the high-level voltage signal VDD; the second end of the third switching transistor CSTC is connected to the third floating diffusion point FDC, and the control end is connected with the logic judgment module; a second terminal of the fourth switching transistor CSTD is connected to the fourth floating diffusion FDD, and a control terminal is also connected to the logic determination module. The third switching transistor CSTC and the fourth switching transistor CSTD are the same type of transistor; because the control ends of the third switching transistor CSTC and the fourth switching transistor CSTD are both connected to the logic judgment module, and the third switching transistor CSTC and the fourth switching transistor CSTD are the same type of transistor, when the logic judgment module outputs a signal, the third switching transistor CSTC and the fourth switching transistor CSTD can be switched on or switched off simultaneously according to the signal output by the logic judgment module; the third switching transistor CSTC conducts the high-level voltage signal VDD and the third floating diffusion point FDC when receiving the control signal output by the logic judgment module, thereby resetting the third floating diffusion point FDC again; when receiving the control signal output by the logic judgment module, the fourth switching transistor CSTD switches on the high-level voltage signal VDD and the fourth floating diffusion point FDD, thereby resetting the fourth floating diffusion point FDD again; the first end of the logic judgment module is respectively connected with the third floating diffusion point FDC and the fourth floating diffusion point FDD, the second end of the logic judgment module is respectively connected with the third switching transistor CSTC and the fourth switching transistor CSTD, and the logic judgment module is used for resetting all the floating diffusion points to re-integrate when at least one of the electric potential of the first floating diffusion point FDA, the electric potential of the second floating diffusion point FDB, the electric potential of the third floating diffusion point FDC and the electric potential of the fourth floating diffusion point FDD is lower than a preset voltage. The arrangement can ensure that the electric potentials of all the floating diffusion points can be in a state higher than the starting voltage (namely, the preset voltage) of the signal output module, effectively reduce the interference of over-strong background light on the pixel circuit of the time-of-flight image sensor, and under the premise, the signal output module can be normally conducted and can smoothly read out the charge signals transmitted by the photosensitive element.
Further, the third signal output module and the fourth signal output module each include a source follower transistor and a row select transistor. The first end of the source electrode following transistor is connected with a high-level voltage signal, the control end of the source electrode following transistor is connected to the floating diffusion point, and the second end of the source electrode following transistor can be connected with a corresponding output end, and also can be connected with the row selecting transistor in series and connected with the corresponding output end through the row selecting transistor; meanwhile, the control end of the source follower transistor is also connected with the second end of the reset transistor and the correction unit CLB; in some embodiments, the source follower transistor is connected to the row selection transistor, so that the charge signal output by the floating diffusion point is led in by the source follower transistor, amplified and then led out to the corresponding output end through the row selection transistor.
In the embodiment of the present application, in the correction unit CLB, the logic determination module includes an inverter and an nor circuit as an example, and actually, the internal configuration of the logic determination module may be the same as that described above, and the logic circuit and the adjacent transistor type are adjusted to implement a change of different structures, which is not limited in the embodiment of the present application, and specifically: the logic judgment module further comprises a third inverter INVC and a fourth inverter INVD, wherein the third inverter INVC is connected with a third floating diffusion point FDC, the fourth inverter INVD is connected with a fourth floating diffusion point FDD, the third inverter INVC and the fourth inverter INVD are parallelly connected to the input end of the NOR gate circuit NOR, and the output end of the NOR gate circuit NOR is simultaneously connected with a third switching transistor CSTC and a fourth switching transistor CSTD.
In the time-of-flight image sensor pixel circuit shown in fig. 9, the third switching transistor CSTC, the fourth switching transistor CSTD, the third reset transistor RSTC, and the fourth reset transistor RSTD are P-type transistors. Therefore, when the potential of at least one floating diffusion point of the first floating diffusion point FDA, the second floating diffusion point FDB, the third floating diffusion point FDC, and the fourth floating diffusion point FDD is lower than the turn-on voltage of the signal output module, the logic determining module may detect whether the voltages of the first floating diffusion point FDA, the second floating diffusion point FDB, the third floating diffusion point FDC, and the fourth floating diffusion point FDD are lower than the turn-on voltage of the signal output module when receiving the voltages of the first floating diffusion point FDA, the second floating diffusion point FDB, the third floating diffusion point FDC, and the fourth floating diffusion point FDD, and control the first switching transistor CSTA, the second switching transistor CSTB, the third switching transistor CSTC, and the fourth switching transistor CSTD to be turned on if the voltages are lower than the turn-on voltage of the signal output module, and the high-level voltage signal VDD passes through the first switching transistor CSTA, the second switching transistor CSTB, the fourth switching transistor CSTD, The third switching transistor CSTC and the fourth switching transistor CSTD simultaneously reset the first floating diffusion point FDA, the second floating diffusion point FDB, the third floating diffusion point FDC, and the fourth floating diffusion point FDD, respectively. The specific case is as follows:
in a first case, when the potential of the first floating diffusion point FDA, the potential of the second floating diffusion point FDB, the potential of the third floating diffusion point FDC, and the fourth floating diffusion point FDD are all higher than the turn-on voltage of the signal output module, the first floating diffusion point FDA, the second floating diffusion point FDB, the third floating diffusion point FDC, and the fourth floating diffusion point FDD all output high level signals, and the low level signals output from the floating diffusion points are converted into high level signals by inverters to be input to the NOR circuit NOR, and since the voltage signals received by the NOR circuit NOR are all low level signals, high level signals are output to the first switching transistor CSTA, the second switching transistor CSTB, the third switching transistor CSTC, and the fourth switching transistor CSTD, as described above, which are all P-type transistors, the P-type transistor is turned on when the control terminal receives a low level signal, so that when the control terminal of the first switch transistor CSTA and the control terminal of the second switch transistor CSTB both receive a high level signal, the first switch transistor CSTA, the second switch transistor CSTB, the third switch transistor CSTC and the fourth switch transistor CSTD all maintain a turned-off state, and the potential of all floating diffusion points is not reset for the second time;
in the second case, when any one of the potential of the first floating diffusion point FDA, the potential of the second floating diffusion point FDB, the potential of the third floating diffusion point FDC, and the fourth floating diffusion point FDD is lower than the turn-on voltage of the signal output module, for example, the potential of the first floating diffusion point FDA is lower than the turn-on voltage of the signal output module, the rest is higher than the turn-on voltage of the signal output module, the low level signal outputted from the floating diffusion point is converted into the high level signal by the inverter and inputted to the NOR circuit NOR, and the NOR circuit NOR receives the voltage signal having both the low level signal and the high level signal, and outputs the low level signal to the first switching transistor CSTA, the second switching transistor CSTB, the third switching transistor CSTC, and the fourth switching transistor CSTD, which are all of the P-type transistor as described above, the P-type transistor is turned on when the control terminal receives a low level signal, so that when the control terminal of the first switch transistor CSTA and the control terminal of the second switch transistor CSTB both receive the low level signal, the first switch transistor CSTA, the second switch transistor CSTB, the third switch transistor CSTC and the fourth switch transistor CSTD are all in a turned-on state, and a high level voltage signal VDD is written into the first floating diffusion point FDA, the second floating diffusion point FDB, the third floating diffusion point FDC and the fourth floating diffusion point FDD through the first switch transistor CSTA, the second switch transistor CSTB, the third switch transistor CSTC and the fourth switch transistor CSTD respectively to perform secondary reset on all floating diffusion points at the same time;
in the third case, when the potential of the first floating diffusion point FDA, the potential of the second floating diffusion point FDB, the potential of the third floating diffusion point FDC, and the fourth floating diffusion point FDD are all lower than the turn-on voltage of the signal output module, the first floating diffusion point FDA and the second floating diffusion point FDB both output low level signals, the high level signals output from the floating diffusion points are converted into high level signals by the inverters to be input to the NOR circuit NOR, and since the voltage signals received by the NOR circuit NOR are all high level signals, low level signals are output to the first switching transistor CSTA, the second switching transistor CSTB, the third switching transistor CSTC, and the fourth switching transistor CSTD, as described above, the first switching transistor CSTA, the second switching transistor CSTB, the third switching transistor CSTC, and the fourth switching transistor CSTD are all P-type transistors, and the P-type transistors are turned on when the control terminal receives the low level signals, therefore, when the control terminal of the first switch transistor CSTA and the control terminal of the second switch transistor CSTB both receive the low level signal, the first switch transistor CSTA, the second switch transistor CSTB, the third switch transistor CSTC, and the fourth switch transistor CSTD are all in the on state, and the high level voltage signal VDD is written into the first floating diffusion point FDA, the second floating diffusion point FDB, the third floating diffusion point FDC, and the fourth floating diffusion point FDD through the first switch transistor CSTA, the second switch transistor CSTB, the third switch transistor CSTC, and the fourth switch transistor CSTD, respectively, to perform the secondary reset on all the floating diffusion points at the same time.
It is to be understood that fig. 9 shows the pixel circuit structure when the number of the reading control units is 4, and in fact, fig. 9 is only an example of the embodiment of the present application, and the number of the reading control units in the pixel circuit in the present application may not be limited.
Further, as shown in fig. 2, the first read control unit RC1 and the second read control unit RC2 are mirror-symmetrical about the photosensitive element PD; in some embodiments, such as the pixel circuit shown in fig. 9, the third read control unit RC3 and the fourth read control unit RC4 are mirror images of each other with the photosensitive element PD as a center. The purpose of setting up like this can utilize the structure space of time of flight image sensor pixel circuit to the at utmost to promote the efficiency of manufacture craft, meanwhile, make the evenly distributed of sensitization district, promote sensitization efficiency.
The embodiment of the application also provides a driving method of the pixel circuit of the time-of-flight image sensor. Fig. 10 is a timing diagram of a pixel circuit of a time-of-flight image sensor provided in an embodiment of the present application when a strong background light is irradiated, and in combination with the pixel circuit of the time-of-flight image sensor shown in fig. 2, a specific implementation manner is as follows:
in a first period t1, which is also called a precharge period, the high level voltage signal VDD turns on the reset transistors RSTA and RSTB, and the high level voltage signal VDD resets the signal output block and the floating diffusion point through the reset transistors RSTA and RSTB. Taking fig. 2 as an example, the reset control signal rst (including the RSTA and RSTB signals) is set to a low level, since the first reset transistor RSTA and the second reset transistor RSTB are both P-type transistors in fig. 2, the high-level voltage signal VDD resets the signal output block and the floating diffusion point through the first reset transistor RSTA and the second reset transistor RSTB, and since the high-level voltage signal VDD is a stable high-level signal, in the embodiment of the present application, the reset operation can also be substantially understood as applying a reference voltage to the signal output block and precharging the floating diffusion point to make it be stable at a preset potential.
In some embodiments, the pixel circuit of the time-of-flight image sensor further includes a pixel reset transistor AB, so that when the signal output module and the floating diffusion point are reset in the embodiments of the present application, the pixel reset transistor AB is turned on, and the ground signal GND provides a low level, so that the photosensitive element PD is cleared and reset. Therefore, in the first stage t1, the pixel reset signal AB may be set to a level signal corresponding to the reset control signal rst, the level signal of the pixel reset signal AB is determined according to the type of the pixel reset transistor AB, and if the pixel reset transistor AB is a P-type transistor, the pixel reset signal AB is a low level signal; if the pixel reset transistor AB is an n-type transistor, the pixel reset signal AB is a high level signal. Here, as an example, the pixel reset transistor AB is an n-type transistor, the pixel reset signal AB is a high level signal, and the ground signal GND provides a low level signal to clear the reset of the photosensitive element PD because the input terminal of the photosensitive element PD is grounded.
A second phase t2, also called the trim phase, in which the reset transistors RSTA and RSTB are turned off, the transfer transistors TXA and TXB are turned on and transfer the charge accumulated by the photosensitive element PD to the first floating diffusion point FDA and the second floating diffusion point FDB; if at least one of the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB is lower than a preset voltage (typically, a turn-on voltage of the signal output module), the correction unit CLB simultaneously applies a high-level signal from the high-level voltage signal VDD to the first floating diffusion point FDA and the second floating diffusion point FDB, turns on the transfer transistors TXA and TXB again, and transfers charges accumulated in the photosensitive element PD to the first floating diffusion point FDA and the second floating diffusion point FDB, respectively; and if the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB are both higher than the preset voltage, writing the charges accumulated by the photosensitive element PD into the signal output module.
As shown in fig. 2, at this stage, the reset control signal rst (including the RSTA and RSTB signals) is set to a high level, and the first reset transistor RSTA and the second reset transistor RSTB are turned off in advance; the transfer signals pga and pgb are alternately set to a high level, and the first transfer transistor TXA of the first read control unit RC1 and the second transfer transistor TXB of the second read control unit RC2 are alternately turned on during exposure of the photosensitive element PD to alternately transfer the charges accumulated in the photosensitive element PD to the first floating diffusion point FDA and the second floating diffusion point FDB, respectively. It is understood that the potential of the first floating diffusion point FDA and/or the potential of the second floating diffusion point FDB is pulled down when a strong background light enters the pixel circuit through exposure of the photosensitive element PD; in detail, as shown in the portion circled by the black frame, when the potential of the first floating diffusion point FDA and/or the potential of the second floating diffusion point FDB is lower than a preset voltage (typically, a turn-on voltage of the readout circuit), the start correction unit CLB simultaneously applies a high level signal from the high level voltage signal VDD to the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB, so that the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB are reset, the first transfer transistor TXA and the second transfer transistor TXB are turned on again, and charges accumulated in the photosensitive element PD are transferred to the first floating diffusion point FDA and the second floating diffusion point FDB, respectively; when the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB are both higher than a predetermined voltage, the charges accumulated in the photosensitive element PD are written into the signal output module.
In a third phase t3, which is also called a read phase, the pass transistors TXA and TXB are turned off and the signal output module is turned on to transmit the image signal. As shown in fig. 2, the row selection signal RS is set to a high level, the transmission signal pga and the transmission signal pgb are alternately set to a low level, the first transmission transistor TXA is turned off from the second transmission transistor TXB of the second read control unit RC2, the first source follower transistor SFA, the second source follower transistor SFB, the first row selection transistor RSA, and the second row selection transistor RSB are turned on to transmit the picture signals, and the transmission of the picture signals starts.
According to the timing sequence of the present application, in the second stage t2, when the potential of the first floating diffusion point FDA and/or the potential of the second floating diffusion point FDB is lower than a preset voltage (typically, the turn-on voltage of the readout circuit), the calibration unit CLB is activated to control the first reset transistor RSTA and the second reset transistor RSTB to simultaneously apply a high level signal from the high level voltage signal VDD to the potential of the first floating diffusion point FDA and the potential of the second floating diffusion point FDB, so that the potentials of the first floating diffusion point FDA and the second floating diffusion point FDB are reset until the potentials of the first floating diffusion point FDA and the second floating diffusion point FDB are both higher than the preset voltage, thereby completing the adaptive adjustment.
Fig. 11 is another timing diagram of a time-of-flight image sensor pixel circuit provided in the embodiment of the present application when the background light is strongly irradiated, and corresponds to the time-of-flight image sensor pixel circuit shown in fig. 9. It is worth noting that:
since the difference between the pixel circuit of the time-of-flight image sensor shown in fig. 9 and the pixel circuit of the time-of-flight image sensor shown in fig. 2 is that a pair of read control units is added, fig. 11 can be analogized by the driving method on the basis of fig. 10 in another timing chart of the pixel circuit of the time-of-flight image sensor provided in the embodiment of the present application when the background light is stronger, but the difference between the two timing charts is that:
in fig. 10, the transmission transistor TXA and the transmission transistor TXB respectively correspond to a driving signal pga and a driving signal pgb, and if the duration of each time the photosensitive element PD transmits the photo-charge signal is T, the time interval between the driving signal pga and the driving signal pgb is T/2; in fig. 11, if the duration of time for which the photo-charge signal is transmitted by each photo-sensing element PD is T, the time interval between the driving signal pga and the driving signal on is T/4, and the time interval between the driving signal pgb and the driving signal pgc and the time interval between the driving signal pgc and the driving signal pgd on is T/4, for the driving signal pga, the driving signal pgb, the driving signal pgc and the driving signal pgd corresponding to the transmission transistor TXA, the transmission transistor TXB, the transmission transistor TXC and the transmission transistor TXD respectively.
In addition, an embodiment of the present application further provides an image sensor, which employs the time-of-flight image sensor pixel circuit provided by the foregoing embodiment, and includes a first chip and a second chip, where the photosensitive element and the transfer transistor are disposed on the first chip; in some embodiments, the first chip is further provided with a pixel reset transistor; the device structure of the first reading control unit except the transmission transistor, the device structure of the second reading control unit except the transmission transistor and the correction unit are arranged on the second chip.
It can be understood that, in the time-of-flight image sensor pixel circuit provided by the present application, the pixel circuit needs to be formed on a Wafer (Wafer), a plurality of pixel circuits and image sensors cooperate to achieve the photoelectric efficiency together, and the Wafer after packaging can constitute an image sensor chip.
As shown in fig. 12, the time-of-flight image sensor pixel circuit provided by the present application is formed on two chips, namely, a first chip a and a second chip B, and covers the first chip a and the second chip B simultaneously, wherein: the first chip a includes a photo sensor PD, a first transfer transistor TXA and a second transfer transistor TXB, which are connected to each other, and in some other embodiments of the present application, the first chip a further includes a pixel reset transistor AB; the second chip B includes the remaining device structures of the first read control unit RC1 except for the first transfer transistor TXA, the remaining device structures of the second read control unit RC2 except for the second transfer transistor TXB, and the entire device structures of the correction unit CLB. In some embodiments, the first chip a and the second chip B are stacked, and the first chip a and the second chip B are electrically connected. It is understood that the electrical connection may be a metal wire connection, or a conductive wire connection made of a doped semiconductor material, which is not limited in the embodiments of the present application. The significance of the arrangement is that the first chip A and the second chip B which are provided with the photosensitive element PD, the first transmission transistor TXA and the second transmission transistor TXB are stacked and electrically connected, the first chip A can be used as an independent pixel, and in the same surface area, compared with a scheme that the first chip A and the second chip B are arranged in parallel, the size of the pixel in the first chip A can be reduced as much as possible, the occupation ratio of a photosensitive area is favorably improved, so that the pixel resolution is better, and the operation speed and the work efficiency of the pixel circuit of the time-of-flight image sensor provided by the embodiment of the application are further improved.
In summary, the embodiments of the present application provide a time-of-flight image sensor pixel circuit, and provide a driving method thereof and an image sensor including the time-of-flight image sensor pixel circuit according to a working state of the time-of-flight image sensor pixel circuit, which can effectively reduce interference of too strong background light to the time-of-flight image sensor pixel circuit, so as to normally conduct and smoothly read out a charge signal transmitted by a photosensitive element.
The embodiments described above are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the application, but is merely representative of selected embodiments of the application. Based on this, the protection scope of the present application shall be subject to the protection scope of the claims. Moreover, all other embodiments that can be made available by a person skilled in the art without making any inventive step based on the embodiments of the present application shall fall within the scope of protection of the present application.
Claims (23)
1. A pixel circuit of a time-of-flight image sensor is characterized by comprising a photosensitive element, a plurality of reading control units and a correction unit;
the plurality of reading control units comprise a plurality of floating diffusion points and are used for respectively performing reading control on the charge signals transmitted by the photosensitive elements; one end of the correction unit is connected with a high-level voltage signal, and the other end of the correction unit is connected with the plurality of floating diffusion points;
wherein the correction unit is used for resetting all the floating diffusion points simultaneously to re-integrate when the potential of at least one floating diffusion point is lower than a preset voltage during integration.
2. The pixel circuit according to claim 1, wherein one end of the correction unit is connected to a high level voltage signal, and the other end is connected to the plurality of floating diffusion points; the correction unit comprises a plurality of switching transistors and a logic judgment module; the first end of the switching transistor is connected with the high-level voltage signal; the second end of the switch transistor is connected with the floating diffusion point, and the control end of the switch transistor is connected with the logic judgment module; the logic judgment module is composed of at least one logic circuit and is used for outputting a control signal to enable the switch transistor to be conducted to reset all the floating diffusion points to re-integrate when the potential of at least one floating diffusion point is lower than the preset voltage.
3. The pixel circuit according to claim 2, wherein the logic decision module comprises at least two inverters and a nor gate, wherein the inverters are connected to the floating diffusion point, the inverters are connected to an input terminal of the nor gate, and an output terminal of the nor gate is connected to the switching transistor.
4. The pixel circuit according to claim 2, wherein the logic decision module comprises an inverter and a nand gate, wherein an input of the nand gate is connected to the floating diffusion point, an output of the nand gate is connected to an input of the inverter, and an output of the inverter is connected to the switching transistor.
5. The pixel circuit of claim 2, wherein the logic decision block comprises only an and circuit, wherein an input of the and circuit is connected to the floating diffusion and an output of the and circuit is connected to the switching transistor.
6. A pixel circuit according to any one of claims 4 or 5, wherein the switching transistor is a P-type transistor.
7. The pixel circuit according to claim 2, wherein the logic decision module comprises at least two inverters and an or gate circuit, wherein the inverters are connected to the floating diffusion point, the inverters are connected to an input end of the or gate circuit, and an output end of the or gate circuit is connected to the switching transistor.
8. The pixel circuit according to claim 2, wherein the logic decision block comprises only a nand gate circuit, wherein an input terminal of the nand gate circuit is connected to the floating diffusion point, and an output terminal of the nand gate circuit is connected to the switching transistor.
9. The pixel circuit according to claim 8, wherein the nand gate circuit is formed by serially connecting at least a control transistor group and a bias transistor, the control transistor group comprises two serially connected control transistors, a control terminal of the bias transistor is connected with a bias voltage, the control transistor group is connected to the high level voltage signal through the bias transistor, and the control transistor and the bias transistor are both N-type transistors.
10. A pixel circuit according to any one of claims 7-9, wherein the switching transistor is an N-type transistor.
11. The pixel circuit according to claim 1, wherein the reading control unit includes a reset transistor, a transfer transistor, and a signal output block; one end of the reset transistor is connected with the high-level voltage signal, and the other end of the reset transistor is connected with the floating diffusion point so as to reset the voltage of the floating diffusion point according to a reset control signal; the first end of the signal output module is connected with the high-level voltage signal, and the control end of the signal output module is connected with the reset transistor and the floating diffusion point respectively, so that the voltage signal input from the floating diffusion point is amplified and output.
12. The pixel circuit according to claim 11, wherein the read control unit includes a first read control unit and a second read control unit, and the first read control unit and the second read control unit are mirror-symmetrical about the photosensitive element.
13. The pixel circuit according to claim 12, wherein the read control unit further includes a third read control unit and a fourth read control unit, and the first read control unit, the second read control unit, the third read control unit, and the fourth read control unit are mirror-symmetric about the photosensitive element.
14. A pixel circuit as claimed in any one of claim 12 or claim 13, wherein the reset transistor is an N-type transistor.
15. The pixel circuit according to claim 11, wherein the signal output module includes a source follower transistor, a first terminal of the source follower transistor is connected to the high-level voltage signal, a control terminal of the source follower transistor is connected to the floating diffusion, a second terminal of the reset transistor, and the correction unit, and a second terminal of the source follower transistor is connected to a corresponding output terminal.
16. The pixel circuit of claim 15, wherein the signal output module comprises a row select transistor, the source follower transistor being connected in series with the row select transistor, the corresponding output terminal being connected through the row select transistor.
17. The pixel circuit of claim 11, further comprising a dual conversion gain control module connected between the reset transistor and the floating diffusion, the dual conversion gain control module comprising at least one dual conversion gain control transistor and a capacitor, the dual conversion gain control module configured to enable switching between a low conversion gain mode and a high conversion gain mode.
18. The pixel circuit according to claim 11, further comprising a pixel reset transistor, wherein a first terminal of the pixel reset transistor is connected to a ground signal, a second terminal of the pixel reset transistor is connected to a second terminal of the photosensitive element, a control terminal of the pixel reset transistor is connected to a pixel reset signal, and the pixel reset transistor is configured to clear charge of the photosensitive element before the photosensitive element transmits a charge signal.
19. The pixel circuit according to claim 11, wherein the read control unit further comprises a storage capacitor, a first plate of the storage capacitor is connected to the floating diffusion point, a second plate of the storage capacitor is connected to a ground signal, and the storage capacitor is configured to receive and store the charges generated by the photosensitive element after the correction unit corrects and resets at least one of the floating diffusion points when the potential of the correction unit is lower than the preset voltage.
20. The pixel circuit according to claim 11, wherein the predetermined voltage is a turn-on voltage of the signal output module.
21. A time-of-flight image sensor employing a time-of-flight image sensor pixel circuit as claimed in any one of claims 11 to 20.
22. The time-of-flight image sensor of claim 21, comprising a first chip and a second chip, wherein: the photosensitive element and the transmission transistor are arranged on the first chip; the device structure of the reading control unit except the transmission transistor and the correction unit are arranged on a second chip; the first chip and the second chip are stacked, and the first chip and the second chip are electrically connected.
23. The time-of-flight image sensor of claim 22, in which the first chip is further provided with a pixel reset transistor.
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| CN202220316061.9U CN217307779U (en) | 2022-02-16 | 2022-02-16 | Time-of-flight image sensor pixel circuit and image sensor |
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| CN202220316061.9U CN217307779U (en) | 2022-02-16 | 2022-02-16 | Time-of-flight image sensor pixel circuit and image sensor |
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