CN217283402U - Radio frequency unit forward transmission interface architecture and base station - Google Patents

Abstract

The utility model discloses a radio frequency unit biography interface framework and basic station relates to wireless communication technical field to solve RRU and can only bear a baseband board, lead to the higher problem of construction cost of basic station. The radio frequency unit forward interface architecture comprises: the first RRU comprises a first FPGA, a first ASIC, at least two first optical ports and at least one second optical port; the first FPGA comprises a plurality of first high-speed interfaces, and is connected with the first ASIC through part of the first high-speed interfaces; the first end of each first optical port is connected with a baseband board, and the second end of each first optical port is connected with a first FPGA through a first high-speed interface; and the first end of each second optical port is used for being connected with the RRU of the next stage, and the second end of each second optical port is connected with the first FPGA through a first high-speed interface. The embodiment of the utility model provides an in one RRU can bear two at least baseband boards to the construction cost of basic station has been reduced.

Description

Radio frequency unit forward transmission interface architecture and base station

Technical Field

The utility model relates to a wireless communication technology field especially relates to a radio frequency unit fronthaul interface framework and basic station.

Background

At present, in a fifth Generation mobile communication technology (5th-Generation, 5G) system, two modes, namely, a Distributed Radio Access Network (drain) and a Centralized Radio Access Network (CRAN), are mainly established for a base station. In the two modes of the drain and the CRAN, indoor baseband processing units (BBUs) are all uniformly placed in a centralized machine room, each BBU may include a plurality of baseband boards, and a Remote Radio Unit (RRU) is placed at a position close to or even infinitely close to the Radio Unit.

In the prior art, a network is usually established by cascading three levels of RRUs, and each RRU is internally provided with an Application Specific Integrated Circuit (ASIC), a transceiver, a radio frequency device, and the like. Currently, ASICs in RRU devices are all two-port devices. Due to the limitation of the ASIC structure, the existing RRUs are also two optical interface devices, and one optical interface needs to be connected to the next stage of RRU, so that only one optical interface can be connected to the baseband board, resulting in that one RRU can only be connected to one baseband board. This results in a high construction cost of the base station.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a radio frequency unit fronthaul interface framework and basic station to solve RRU and can only bear a baseband board, lead to the higher problem of construction cost of basic station.

In a first aspect, an embodiment of the present invention provides a radio frequency unit fronthaul interface architecture, including:

the first RRU comprises a first FPGA, a first ASIC, at least two first optical ports and at least one second optical port, wherein the first FPGA is used for carrying out merging or separation processing on data;

the first FPGA comprises a plurality of first high-speed interfaces, and is connected with the first ASIC through part of the first high-speed interfaces;

the first end of each first optical port is connected with a baseband board, and the second end of each first optical port is connected with the first FPGA through one first high-speed interface;

and a first end of each second optical port is used for being connected with a subsequent stage of RRU, and a second end of each second optical port is connected with the first FPGA through one first high-speed interface.

Optionally, the radio frequency unit forwarding interface architecture further includes: at least one second RRU;

each second RRU comprises a second FPGA, a second ASIC, at least two third optical ports and at least one fourth optical port, which are used for merging or separating data;

the second FPGA comprises a plurality of second high-speed interfaces, and is connected with the second ASIC through part of the second high-speed interfaces;

the first end of at least one third optical port is connected with a previous stage of RRU, and the second end of each third optical port is connected with the second FPGA through one second high-speed interface;

the first end of at least one fourth optical port is used for being connected with a subsequent stage of RRU, and the second end of each fourth optical port is connected with the second FPGA through one second high-speed interface.

Optionally, the first RRU is cascaded with the at least one second RRU.

Optionally, the number of the first light ports is two or three.

Optionally, the at least one second RRU comprises two second RRUs; the two second RRUs are a third RRU and a fourth RRU; the first RRU, the third RRU and the fourth RRU are sequentially cascaded together.

Optionally, the first RRU includes two first optical ports, where one of the first optical ports is connected to the first baseband board through a first end thereof, and the other first optical port is connected to the second baseband board through a first end thereof.

Optionally, the first RRU further includes a second optical port, the third RRU includes two third optical ports and a fourth optical port, and the fourth RRU includes two third optical ports and a fourth optical port;

one of the second optical ports in the first RRU is connected to any one of the third optical ports in the third RRU, and one of the fourth optical ports in the third RRU is connected to any one of the third optical ports in the fourth RRU.

Optionally, the first RRU further includes two second optical ports, the third RRU includes two third optical ports and two fourth optical ports, and the fourth RRU includes two third optical ports and two fourth optical ports;

the two second optical ports in the first RRU are respectively connected with the two third optical ports in the third RRU, and the two fourth optical ports in the third RRU are respectively connected with the two third optical ports in the fourth RRU.

Optionally, the first ASIC includes two ASIC interfaces, at least one of the two ASIC interfaces being connected to two of the plurality of first high speed interfaces.

In a second aspect, an embodiment of the present invention further provides a base station, which includes at least two baseband boards and the foregoing radio frequency unit forwarding interface framework, and each of the first ends of the first optical ports is connected to one of the baseband boards.

In the embodiment of the present invention, the radio frequency unit fronthaul interface architecture may include a first RRU, where the first RRU includes a first FPGA, a first ASIC, at least two first optical interfaces, and at least one second optical interface, which are used for merging or separating data; the first FPGA comprises a plurality of first high-speed interfaces, and is connected with the first ASIC through part of the first high-speed interfaces; the first end of each first optical port is connected with one baseband board, and the second end of each first optical port is connected with the first FPGA through a first high-speed interface; and the first end of each second optical port is used for being connected with the RRU of the next stage, and the second end of each second optical port is connected with the first FPGA through a first high-speed interface. Therefore, the data can be received by the first ASIC without the limitation of the number of ASIC interfaces of the first ASIC by the combination and separation processing of the data by the first FPGA. Thus, the first RRU may be provided with at least two first optical ports, thereby connecting at least two baseband boards. Through the arrangement, the number of the first RRUs required by connecting the plurality of baseband boards is reduced, so that the structure of the radio frequency unit fronthaul interface framework is simplified, the construction cost of the radio frequency unit fronthaul interface framework is reduced, and the construction cost of the base station is further reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments of the present invention will be briefly described below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.

Fig. 1 is a schematic structural diagram of a radio frequency unit forwarding interface architecture according to an embodiment of the present invention;

fig. 2 is a second schematic structural diagram of a radio frequency unit forwarding interface architecture according to an embodiment of the present invention;

fig. 3 is a third schematic structural diagram of a radio frequency unit forwarding interface architecture according to an embodiment of the present invention;

fig. 4 is a fourth schematic structural diagram of a radio frequency unit forwarding interface architecture according to an embodiment of the present invention;

fig. 5 is a fifth schematic structural diagram of a radio frequency unit forwarding interface architecture according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, of the embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts all belong to the protection scope of the present invention.

Referring to fig. 1-2, fig. 1 is a first schematic structural diagram of a radio frequency unit forwarding interface architecture provided by an embodiment of the present invention, and fig. 2 is a second schematic structural diagram of the radio frequency unit forwarding interface architecture provided by the embodiment of the present invention. As shown in fig. 1 and fig. 2, the radio frequency unit forwarding interface architecture may include:

a first RRU, which may include a first Field Programmable Gate Array (FPGA) for merging or separating data, a first ASIC, at least two first optical ports, and at least one second optical port;

the first FPGA comprises a plurality of first high-speed interfaces, and is connected with the first ASIC through part of the first high-speed interfaces;

the first end of each first optical port is connected with one baseband board, and the second end of each first optical port is connected with the first FPGA through a first high-speed interface;

the first end of each second optical port is used for being connected with a rear-stage RRU, and the second end of each second optical port is connected with the first FPGA through a first high-speed interface.

It should be understood that the first optical port described above may be used for photoelectric conversion or electro-optical conversion of data, i.e. the first optical port may convert data in the form of electrical signals and data in the form of optical signals to each other. The second optical port may also be used for performing optical-to-electrical conversion or electrical-to-optical conversion on data, that is, the second optical port may perform interconversion between data in the form of an electrical signal and data in the form of an optical signal. The first FPGA is used for merging or separating data. The first ASIC is used to perform digital intermediate frequency functions.

It will be appreciated that for the first optical ports, two ports are provided for each first optical port, wherein a first end of the first optical port is for connection with the baseband board and a second end of the first optical port is for connection with the first high speed interface. For the second optical ports, each second optical port is provided with two ports, wherein a first end of the second optical port is used for being connected with the RRU of the next stage, and a second end of the second optical port is used for being connected with the first high-speed interface. In some embodiments, the RRU of the next stage may also be referred to as the RRU of the next stage, and the RRU of the previous stage may also be referred to as the RRU of the previous stage.

It should be understood that the structure of the first optical port is not limited thereto. For example, in some embodiments, the first optical port is an optical module interface. Furthermore, the first optical port is an optical module interface of 10G. The structure of the second optical port is not limited herein. For example, in some embodiments, the second optical port is an optical module interface. Furthermore, the second optical port is a 10G optical module interface. In a specific implementation, the first optical port and the second optical port have the same structure.

It should be understood that the connection manner of the first end of the first optical port and the base band plate is not limited herein. In both the DRAN and CRAN modes, the RRU is typically located remotely from the baseband board. Thus, in some embodiments, the first end of the first optical port is connected to the baseband board, typically by an optical fiber.

It should be understood that the structure of the first ASIC is not limited thereto. Optionally, in some embodiments, the first ASIC may include two ASIC interfaces, at least one of the two ASIC interfaces being connected with two of the plurality of first high speed interfaces.

It should be understood that in some embodiments, either one of the two ASIC interfaces is simultaneously connected with both first high speed interfaces. In other embodiments, one of the two ASIC interfaces is connected to one of the plurality of first high speed interfaces and the other ASIC interface is connected to the other of the plurality of first high speed interfaces.

It should be understood that the structure of the ASIC interface is not limited thereto. For example, in some embodiments, the ASIC interface is a Serializer-Deserializer (SERDES) interface. Further, the ASIC interface is a SERDES interface of 25G.

In the present embodiment, as shown in fig. 1 and 2, the first ASIC includes two ASIC interfaces and is connected to two first high-speed interfaces of the first FPGA through one of the ASIC interfaces. Therefore, in this embodiment, only by processing the RRU in the related art, the first FPGA is added to obtain the first RRU. Through the arrangement, the construction cost of the radio frequency unit forward transmission interface framework is reduced.

It should be understood that the structure of the first FPGA is not limited thereto. The first FPGA comprises a plurality of first high-speed interfaces, and the first FPGA is connected with the first ASIC through part of the first high-speed interfaces. In this embodiment, it can be considered that each of the first high-speed interfaces is provided with two ends, one end is connected to the first ASIC, and the other end is connected to the second end of the first optical port or the second end of the second optical port.

It should be understood that the structure of the first high-speed interface of the first FPGA is not limited thereto. For example, in some embodiments, the first high speed interface is a SERDES interface. Further, the first high-speed interface is a 10G SERDES interface.

It should be understood that in some embodiments, the first FPGA being coupled to the first ASIC via a portion of the first high speed interface can be understood that the portion of the first high speed interface of the first FPGA and the first ASIC are configured to communicate between the portion of the first high speed interface of the first FPGA and the first ASIC via the transmission of signals. Part of the first high-speed interface of the first FPGA and the first ASIC may be connected in wired communication or in wireless communication.

Further, in other embodiments, the first FPGA is coupled to the first ASIC via a portion of the first high speed interface. It can be understood that a part of the first high-speed interface of the first FPGA interacts with the ASIC interface through signal transmission, and communication is formed between the part of the first high-speed interface of the first FPGA and the ASIC interface.

It should be understood that in some embodiments, the first high speed interface is connected to the second end of the first optical port. It can be understood that the first high-speed interface of the first FPGA and the second end of the first optical port interact through signal transmission to form communication between the first FPGA and the first optical port. The first FPGA and the first optical port can be in wired communication connection or in wireless communication connection.

It should be understood that, in some embodiments, the connection between the first high-speed interface and the second end of the second optical port may be understood as that the first high-speed interface of the first FPGA and the second end of the second optical port perform communication between the first FPGA and the second optical port through transmission and interaction of signals. The first FPGA and the second optical port can be in wired communication connection or in wireless communication connection.

It should be understood that, in a specific implementation, the first RRU may further include a transceiver, a radio frequency device, and the like, where the radio frequency device may be a radio frequency link, the transceiver is connected to the first ASIC, and the radio frequency device is connected to the transceiver or the first ASIC.

Optionally, in some embodiments, the number of first light ports is two or three.

As shown in fig. 1, in some embodiments, the number of the base band plates is two, the number of the first light ports is two, and the number of the second light ports is two. In other embodiments, as shown in fig. 2, the number of the base band plates is three, the number of the first light ports is three, and the number of the second light ports is one. In still other embodiments, as shown in fig. 3, the number of the base band plates is two, the number of the first light ports is two, and the number of the second light ports is one. Although fig. 1-3 illustrate the number of the first optical ports as two and three, the present invention is not limited thereto, and the number of the first optical ports may be adjusted based on actual requirements when being implemented, for example, the number of the first optical ports may be four or five, and so on. It should be understood that, although fig. 1-3 show one or two second optical ports, the present invention is not limited thereto, and the number of second optical ports can be adjusted based on actual requirements when the present invention is implemented.

It should be understood that the capacity of the first RRU is predetermined, and in general, the first RRU can handle the number of at least one cell in units of cells. In a specific implementation, the size of data that can be processed by the first RRU is limited due to the capacity of the first RRU, that is, the number of cells corresponding to the first RRU is limited. In some embodiments, the capacity of the RRU may also be referred to as RRU resources. The cell corresponding to the first RRU is the same as the cells carried by the at least two baseband boards. For example, in some embodiments, at least two baseband boards are used to carry data for cell 1 and cell 2, and the first RRU is used to correspondingly process data for cell 1 and cell 2.

The following describes the present application with reference to a process of uplink data or downlink data. Downlink data may be understood as data sent by the baseband board to the RRU. Uplink data may be understood as data sent by the RRU to the baseband board.

When processing downlink data signals, each baseband board carries data corresponding to a corresponding target cell and sends the data to the first RRU through a corresponding first optical port. First, after receiving data sent by a baseband board, a first optical port performs photoelectric conversion on the received data. Since the optical fiber connection is used between the baseband board and the first optical port, the first optical port needs to convert data in the form of optical signals into data in the form of electrical signals. And then the first optical port sends the converted data to the first FPGA. Because the number of the baseband boards is at least two, the at least two first optical ports receive the data sent by the corresponding baseband boards. The first FPGA can receive data sent by at least two first optical ports, so that the first FPGA combines data sent by different first optical ports, and sends the combined data to the first ASIC for processing. Since the target cell corresponds to the first RRU, the data corresponding to the target cell will complete the data processing operation in the first RRU.

When processing the uplink data signal, the first ASIC may obtain data corresponding to each target cell, and send the obtained data to the first FPGA, and the first FPGA may receive data corresponding to at least two target cells, so that the first FPGA needs to separate the received data, that is, separate data corresponding to target cells corresponding to different baseband boards. And according to the corresponding relation between the first optical port and the baseband board, the first FPGA sends the separated data to the corresponding first optical port. The plurality of first optical ports can perform electro-optical conversion on the received data, that is, convert data in an electrical signal form into data in an optical signal form, and send the converted data to the corresponding baseband board.

In the embodiment of the present invention, the radio frequency unit fronthaul interface architecture may include a first RRU, where the first RRU includes a first FPGA, a first ASIC, at least two first optical interfaces, and at least one second optical interface, which are used for merging or separating data; the first FPGA comprises a plurality of first high-speed interfaces, and is connected with the first ASIC through part of the first high-speed interfaces; the first end of each first optical port is connected with one baseband board, and the second end of each first optical port is connected with the first FPGA through a first high-speed interface; and the first end of each second optical port is used for being connected with the RRU of the next stage, and the second end of each second optical port is connected with the first FPGA through a first high-speed interface. Therefore, the data can be received by the first ASIC without the limitation of the number of ASIC interfaces of the first ASIC by the combination and separation processing of the data by the first FPGA. Thus, the first RRU may be provided with at least two first optical ports to connect at least two baseband boards. Through the arrangement, the number of the first RRUs required by connecting the plurality of baseband boards is reduced, so that the structure of the radio frequency unit fronthaul interface framework is simplified, the construction cost of the radio frequency unit fronthaul interface framework is reduced, and the construction cost of the base station is further reduced.

In this embodiment, since the baseband board carries the same number of cells in use as the number of cells corresponding to the first RRU. Therefore, limited by the capacity of the first RRU, the number of cells actually carried by the baseband board in use may be small, which may result in that the resources of the baseband board cannot be fully utilized, and thus the capacity can be expanded by increasing the number of RRUs. Optionally, as shown in fig. 3, the radio frequency unit forwarding interface architecture further includes: at least one second RRU;

each second RRU comprises a second FPGA for merging or separating data, a second ASIC, at least two third optical ports and at least one fourth optical port;

the second FPGA comprises a plurality of second high-speed interfaces, and the second FPGA is connected with the second ASIC through part of the second high-speed interfaces;

the first end of at least one third optical port is connected with the RRU of the previous stage, and the second end of each third optical port is connected with the second FPGA through a second high-speed interface;

the first end of at least one fourth optical port is used for being connected with a subsequent stage of RRU, and the second end of each fourth optical port is connected with the second FPGA through a second high-speed interface.

It should be understood that the third optical port described above may be used for photoelectric conversion or electro-optical conversion of data, i.e. the third optical port may convert data in the form of electrical signals and data in the form of optical signals to each other. The fourth optical port may also be used for performing photoelectric conversion or electro-optical conversion on data, that is, the fourth optical port may perform mutual conversion between data in the form of an electrical signal and data in the form of an optical signal. And the second FPGA is used for merging or separating the data. The second ASIC is used to perform digital intermediate frequency functions.

It will be appreciated that for the third optical ports, two ports are provided for each third optical port, wherein a first end of the third optical port is for connection with the baseband board and a second end of the third optical port is for connection with the second high speed interface. For the fourth optical ports, each fourth optical port is provided with two ports, wherein a first end of the fourth optical port is used for being connected with a third optical port of a subsequent stage of RRU, and a second end of the fourth optical port is used for being connected with a second high-speed interface.

It should be understood that the structure of the third optical port is not limited thereto. For example, in some embodiments, the third optical port is an optical module interface. Furthermore, the third optical port is a 10G optical module interface. The structure of the fourth optical port is not limited herein. For example, in some embodiments, the fourth optical port is an optical module interface. Furthermore, the fourth optical port is an optical module interface of 10G. In a specific implementation, the third optical port and the fourth optical port have the same structure.

It should be understood that the structure of the second ASIC is not limited thereto. For example, in some embodiments, the second ASIC may include two ASIC interfaces, at least one of the two ASIC interfaces being connected with two of the plurality of second high speed interfaces.

It should be appreciated that in some embodiments, either one of the two ASIC interfaces is simultaneously connected with both of the second high speed interfaces. In other embodiments, one of the two ASIC interfaces is connected to one of the second high speed interfaces and the other ASIC interface is connected to the other of the second high speed interfaces.

It should be understood that the structure of the second FPGA is not limited thereto. In some embodiments, the second FPGA includes a plurality of second high-speed interfaces, and the second FPGA is connected to the second ASIC through a portion of the second high-speed interfaces. In this embodiment, it can be considered that each of the second high-speed interfaces is provided with two ends, one end is connected to the second ASIC, and the other end is connected to the second end of the third optical port or the second end of the fourth optical port.

It should be understood that, in a specific implementation, the number of the second high-speed interfaces is the same as the sum of the number of the third optical ports and the number of the fourth optical ports.

It should be understood that the structure of the second high-speed interface of the second FPGA is not limited thereto. For example, in some embodiments, the second high speed interface is a SERDES interface. Further, the second high-speed interface is a 10G SERDES interface.

It should be understood that in some embodiments, the second FPGA being connected to the second ASIC via a portion of the second high speed interface may be understood such that the portion of the second high speed interface of the second FPGA and the second ASIC interact via the transmission of signals to provide communication between the portion of the second high speed interface of the second FPGA and the second ASIC. And part of the second high-speed interface of the second FPGA and the second ASIC can be in wired communication connection or wireless communication connection.

Further, in other embodiments, the second FPGA is connected to the second ASIC via a portion of the second high speed interface, which may be understood as a portion of the second high speed interface of the second FPGA interfacing with the ASIC via signal transmission interaction, to provide communication between the portion of the second high speed interface of the second FPGA and the ASIC interface.

It should be understood that, in some embodiments, the connection between the second high-speed interface and the second end of the third optical port may be understood as that the second high-speed interface of the second FPGA and the second end of the third optical port perform communication between the second high-speed interface of the second FPGA and the third optical port through transmission and interaction of signals. The second high-speed interface of the second FPGA and the third optical port may be in wired communication connection or in wireless communication connection.

It should be understood that, in some embodiments, the connection between the second high-speed interface and the second end of the fourth optical port may be understood as that the second high-speed interface of the second FPGA and the second end of the fourth optical port form communication between the second high-speed interface of the second FPGA and the fourth optical port through transmission and interaction of signals. The second high-speed interface of the second FPGA and the fourth optical port may be connected by wired communication or wireless communication.

It should be understood that, in a specific implementation, the second RRU may further include a transceiver, a radio frequency device, and the like, where the radio frequency device may be a radio frequency link, the transceiver is connected to the second ASIC, and the radio frequency device is connected to the transceiver or the second ASIC.

Therefore, by setting at least one second RRU, the size of data which can be processed is increased, and the number of connecting circuits of the baseband board and the RRU is reduced, so that the construction cost of the radio frequency unit forward interface architecture is reduced.

Optionally, in some embodiments, the first RRU is cascaded with at least one second RRU.

It should be understood that in some embodiments, the at least one second RRU may comprise one second RRU, as illustrated in fig. 3. In still other embodiments, the at least one second RRU includes a plurality of second RRUs, as shown in fig. 4 and 5.

It should be understood that the first RRU is cascaded with at least one second RRU, which is a subsequent stage RRU of the first RRU, in a case where the number of the second RRUs is one. And under the condition that the number of the second RRUs is multiple, the multiple second RRUs are sequentially cascaded, the second RRU at the uppermost stage is connected with the first RRU, and the second RRU at the uppermost stage is the RRU at the next stage of the first RRU.

In this embodiment, a first RRU is cascaded with at least one second RRU. Under the condition that the capacity of each second RRU is the same, the connection circuit of the baseband board and the RRU can be reduced simultaneously under the condition of increasing the size of the data which can be processed by a mode of cascading the first RRU and at least one second RRU, and the construction cost of the radio frequency unit forward interface architecture is reduced.

Optionally, as shown in fig. 4 and fig. 5, the at least one second RRU includes two second RRUs; the two second RRUs are a third RRU and a fourth RRU; the first RRU, the third RRU and the fourth RRU are sequentially cascaded together. It should be understood that the first RRU, the third RRU, and the fourth RRU are sequentially cascaded together, which means that for the first RRU, the first RRU is the uppermost RRU, and the third RRU is the next RRU of the first RRU. For the third RRU, the first RRU is an RRU of a previous stage of the third RRU, and the fourth RRU is an RRU of a subsequent stage of the third RRU. For the fourth RRU, the fourth RRU is the lowest stage RRU, and the third RRU is the RRU of the previous stage of the fourth RRU.

It should be understood that, the first RRU, the third RRU, and the fourth RRU are sequentially cascaded together, which may be understood that at least a portion of the third optical ports of the third RRU are connected to the first ends of at least a portion of the second optical ports in a one-to-one correspondence manner through the first ends of the third optical ports. At least part of the fourth optical ports of the third RRUs are correspondingly connected with the first ends of at least part of the third optical ports of the fourth RRUs through the first ends of the third optical ports. In a specific implementation, the fourth optical port of the fourth RRU may be considered as an idle state.

It should be understood that the third RRU and the fourth RRU may have the same structure, i.e., the structure of each second RRU described above. The third RRU includes a second FPGA, a second ASIC, at least two third optical ports, and at least one fourth optical port, which are corresponding to the third RRU and perform merging or separation processing on data. The fourth RRU also includes a second FPGA, a second ASIC, at least two third optical ports, and at least one fourth optical port, which are corresponding to the fourth RRU and perform merging or separation processing on data.

In this embodiment, the first RRU, the third RRU, and the fourth RRU are sequentially connected together, and thus, in this embodiment, the first RRU, the third RRU, and the fourth RRU may be regarded as three stages of RRU cascade connections. Through the arrangement, on one hand, the size of data which can be processed is further increased, on the other hand, the number of connecting lines between the baseband board and the RRU is further reduced, and meanwhile, the influence on the service processing speed and the reliability of a radio frequency unit forward transmission interface architecture is small.

Optionally, in some embodiments, the first RRU comprises two first optical ports, wherein one first optical port is connected to the first baseband board through a first end thereof, and the other first optical port is connected to the second baseband board through a first end thereof. Optionally, as shown in fig. 4, in some embodiments, the first RRU further includes one second optical port, the third RRU includes two third optical ports and one fourth optical port, and the fourth RRU includes two third optical ports and one fourth optical port;

one second optical port in the first RRU is connected to any one third optical port in the third RRU, and one fourth optical port in the third RRU is connected to any one third optical port in the fourth RRU.

Optionally, as shown in fig. 5, in some embodiments, the first RRU further includes two second optical ports, the third RRU includes two third optical ports and two fourth optical ports, and the fourth RRU includes two third optical ports and two fourth optical ports;

two second optical ports in the first RRU are connected to two third optical ports in the third RRU, and two fourth optical ports in the third RRU are connected to two third optical ports in the fourth RRU, respectively.

Optionally, the first ASIC includes two ASIC interfaces, at least one of the two ASIC interfaces being connected to two of the plurality of first high speed interfaces.

For better understanding of the present invention, the following will use the embodiments shown in fig. 4 and fig. 5 as examples to describe the downlink data signal processing flow and the uplink data signal processing flow of the radio frequency unit forwarding interface architecture provided in this embodiment.

For convenience of description, in the first embodiment shown in fig. 4 and the second embodiment shown in fig. 5, the two illustrated base belt plates are respectively referred to as a base belt plate 1 and a base belt plate 2. And it is assumed that the baseband board 1 carries data of cell a, data of cell b, and data of cell c, and the baseband board 2 carries data of cell d, data of cell f, and data of cell e. The cell a and the cell d correspond to the first RRU shown in the drawing, the cell b and the cell e correspond to the third RRU shown in the drawing, and the cell c and the cell f correspond to the fourth RRU shown in the drawing.

In the first embodiment shown in fig. 4 and the second embodiment shown in fig. 5, the first optical port, the second optical port, the third optical port, and the fourth optical port have the same structure, and each of the first optical port, the second optical port, the third optical port, and the fourth optical port is a 10G optical module interface.

As shown in fig. 4 and 5, the first FPGA is provided with four first high-speed interfaces, the third FPGA is provided with four second high-speed interfaces, and the fourth FPGA is provided with four second high-speed interfaces. Wherein the first high speed interface and the second high speed interface are all identical in structure. Each of the first high-speed interfaces and each of the second high-speed interfaces shown in fig. 4 and 5 are SERDES interfaces of 10G. For convenience of description, the first high speed interface and the second high speed interface will not be distinguished in the following description, i.e., both the first high speed interface and the second high speed interface are referred to as high speed interfaces.

As shown in fig. 4 and 5, the first ASIC, the third ASIC, and the fourth ASIC are each provided with two ASIC interfaces having the same structure, where each ASIC interface in fig. 4 and 5 is a 25G SERDES interface.

Example one

As shown in fig. 4, in this embodiment, for convenience of description, two first optical ports included in the first RRU are respectively denoted as a first optical port 1 and a first optical port 2, and one second optical port included in the first RRU is denoted as a second optical port 1.

And recording two third optical ports included in the third RRU as a third optical port 31 and a third optical port 32, respectively, recording a fourth optical port included in the third RRU as a fourth optical port 1, recording a second FPGA included in the third RRU as a third FPGA, and recording a second ASIC included in the third RRU as a third ASIC.

The two third optical ports included in the fourth RRU are respectively denoted as a third optical port 41 and a third optical port 42, the fourth optical port included in the fourth RRU is denoted as a fourth optical port 2, the second FPGA included in the fourth RRU is denoted as a fourth FPGA, and the second ASIC included in the fourth RRU is denoted as a fourth ASIC.

First, a specific process of the radio frequency unit forwarding interface architecture provided in this embodiment when processing a downlink data signal will be described.

When processing the downlink data signal, the baseband board 1 sends the data corresponding to the cell a, the data corresponding to the cell b, and the data corresponding to the cell c to the corresponding first optical port 1 in the form of an optical signal through the optical fiber. The first optical port 1 performs photoelectric conversion on the received data to obtain data in an electric signal form, and sends the data in the electric signal form obtained by conversion to the first FPGA through a first high-speed interface of the first FPGA. Meanwhile, the baseband board 2 sends the data corresponding to the cell d, the data corresponding to the cell f and the data corresponding to the cell e to the corresponding first optical port 2 in the form of optical signals through optical fibers, the first optical port 2 performs photoelectric conversion on the received data, converts the received data into data in the form of electric signals, and sends the converted data in the form of electric signals to the first FPGA through the second high-speed interface of the first FPGA. And then, the first FPGA combines the data corresponding to the cell a and the data corresponding to the cell d, and sends the combined data corresponding to the cell a and the cell d to the first ASIC for processing. After the first ASIC completes the digital intermediate frequency function, all functions of the first RRU are realized through the connected transceiver and the radio frequency link.

The first FPGA combines and processes the data corresponding to the cell b, the data corresponding to the cell c, the data corresponding to the cell e, and the data corresponding to the cell f through the third high-speed interface of the first FPGA, and then sends the combined and processed data to the second optical port 1, the second optical port 1 converts the data corresponding to the cell b, the data corresponding to the cell c, the data corresponding to the cell e, and the data corresponding to the cell f into data in an optical signal form, and sends the converted data to the third optical port 31. Then, after receiving the data corresponding to the combined cell b, cell c, cell e, and cell f, the third optical port 31 converts the data corresponding to the combined cell b, cell c, cell e, and cell f into data in the form of an electrical signal, and sends the converted data to the third FPGA through the first high-speed interface of the third FPGA. And then, the third FPGA separates the data corresponding to the combined cell b, cell c, cell e and cell f into the data of the pre-combined cell b and cell e and the data of the pre-combined cell c and cell f. And then the third FPGA sends the data of the pre-combined cell b and cell e to a third ASIC for processing. And after the third ASIC completes the digital intermediate frequency function, all functions of the third RRU are realized through the connected transceiver and the radio frequency link.

The third FPGA sends the data of the precombined cell c and the cell f to the fourth optical port 1 through the third high-speed interface of the third FPGA, and the fourth optical port 1 converts the data of the precombined cell c and the cell f into data in an optical signal form and sends the converted data to the third optical port 41. Then, after receiving the data of the precombined cell c and the cell f in the form of optical signals, the third optical port 41 converts the precombined cell c and the cell f into data in the form of electrical signals, and sends the converted data to the fourth FPGA through the first high-speed interface of the fourth FPGA. And then, the fourth FPGA sends the data of the pre-combined cell c and cell f to a fourth ASIC for processing. And after the fourth ASIC completes the digital intermediate frequency function, all functions of the fourth RRU are realized through the connected transceiver and the radio frequency link.

The specific process of processing the uplink data signal by the radio frequency unit forwarding interface architecture provided in this embodiment will be described below.

And after the fourth ASIC obtains the data corresponding to the cell c and the data corresponding to the cell f through the connected transceiver and the radio frequency link, the data corresponding to the cell c and the data corresponding to the cell f are sent to the fourth FPGA through a first high-speed interface of the fourth FPGA.

The fourth FPGA combines the data corresponding to the cell c and the data corresponding to the cell f through the first high-speed interface of the fourth FPGA, and then sends the combined data to the third optical port 41. The third optical port 41 converts the combined data of the cell c and the cell f in the form of the received electrical signals into data in the form of optical signals, and transmits the converted data to the fourth optical port 1. Then, after receiving the combined data of the cell c and the cell f, the fourth optical port 1 converts the combined data of the cell c and the cell f in the form of optical signals into data in the form of electrical signals, and sends the converted data to the third FPGA through a third high-speed interface of the third FPGA. And after the third ASIC obtains the data corresponding to the cell b and the data corresponding to the cell e through the connected transceiver and the radio frequency link, the third ASIC sends the data corresponding to the cell b and the data corresponding to the cell e to the third FPGA through a first high-speed interface of the third FPGA.

The third FPGA combines the data corresponding to the cell b, the data corresponding to the cell e, and the combined data of the cell c and the cell f, and sends the combined data to the third optical port 31 through the first high-speed interface of the third FPGA. The third optical port 31 converts the received data of the combined cell b, cell e, cell c, and cell f into data in the form of optical signals, and transmits the converted data to the second optical port 1. And then the second optical port 1 converts the data in the form of optical signals into the data in the form of electric signals after receiving the combined data of the cell b, the cell e, the cell c and the cell f, and sends the converted data to the first FPGA through a third high-speed interface of the first FPGA. And after the first ASIC obtains the data corresponding to the cell a and the data corresponding to the cell d through the connected transceiver and the radio frequency link, the data corresponding to the cell a and the data corresponding to the cell d are sent to the first FPGA through a first high-speed interface of the first FPGA. The first FPGA separates the combined data of the cell b, the cell e, the cell c and the cell f into pre-combined data of the cell b and the cell c and pre-combined data of the cell e and the cell f.

And the first FPGA combines the data corresponding to the cell a and the data of the pre-combined cell b and the cell c again, and sends the combined data to the first optical port 1 through a first high-speed interface of the first FPGA. Meanwhile, the first FPGA merges the data corresponding to the cell d and the data of the pre-merged cell e and f again, and sends the merged data to the first optical port 2 through the second high-speed interface of the first FPGA. The first optical port 1 converts the received data of the combined cell a, cell b, and cell c into data in the form of an optical signal, and transmits the converted data to the baseband board 1. Meanwhile, the first optical port 2 converts the received data of the cell d, the cell e, and the cell f after being combined into data in an optical signal form, and sends the converted data to the baseband board 2.

Example two

As shown in fig. 5, in this embodiment, for convenience of description, two first optical ports included in the first RRU are respectively denoted as a first optical port 1 and a first optical port 2, and two second optical ports included in the first RRU are respectively denoted as a second optical port 1 and a second optical port 2. And recording two third optical ports included in the third RRU as a third optical port 31 and a third optical port 32, recording two fourth optical ports included in the third RRU as a fourth optical port 1 and a fourth optical port 3, recording a second FPGA included in the third RRU as a third FPGA, and recording a second ASIC included in the third RRU as a third ASIC.

As shown in fig. 5, two third optical ports included in the fourth RRU are respectively denoted as a third optical port 41 and a third optical port 42, two fourth optical ports included in the fourth RRU are respectively denoted as a fourth optical port 2 and a fourth optical port 4, a second FPGA included in the fourth RRU is denoted as a fourth FPGA, and a second ASIC included in the fourth RRU is denoted as a fourth ASIC.

First, a specific process of the radio frequency unit forwarding interface architecture provided in this embodiment when processing a downlink data signal will be described.

When processing the downlink data signal, the baseband board 1 sends the data corresponding to the cell a, the data corresponding to the cell b, and the data corresponding to the cell c to the corresponding first optical port 1 in the form of an optical signal through the optical fiber. The first optical port 1 performs photoelectric conversion on the received data to obtain data in an electric signal form, and sends the converted data in the electric signal form to the first FPGA through a first high-speed interface of the first FPGA. Meanwhile, the baseband board 2 sends the data corresponding to the cell d, the data corresponding to the cell e and the data corresponding to the cell f to the corresponding first optical port 2 in the form of optical signals through optical fibers, the first optical port 2 performs photoelectric conversion on the received data, converts the received data into data in the form of electric signals, and sends the converted data in the form of electric signals to the first FPGA through the second high-speed interface of the first FPGA. And then, the first FPGA combines the data corresponding to the cell a and the data corresponding to the cell d, and sends the combined data to the first ASIC for processing. After the first ASIC completes the digital intermediate frequency function, all functions of the first RRU are realized through the connected transceiver and the radio frequency link.

The first FPGA sends the data corresponding to the cell b and the data corresponding to the cell c to the second optical port 1 through the third high-speed interface of the first FPGA, and the second optical port 1 converts the data corresponding to the cell b and the data corresponding to the cell c into data in an optical signal form and sends the converted data to the third optical port 31. The first FPGA sends the data corresponding to the cell e and the data corresponding to the cell f to the second optical port 2 through the fourth high-speed interface of the first FPGA, and the second optical port 2 converts the data corresponding to the cell e and the data corresponding to the cell f into an optical signal form and sends the converted data to the third optical port 32. After receiving the data corresponding to the cell b and the data corresponding to the cell c in the optical signal form, the third optical port 31 converts the data corresponding to the cell b and the data corresponding to the cell c into data in the electrical signal form, and sends the converted data to the third FPGA through the first high-speed interface of the third FPGA. Meanwhile, after receiving the data corresponding to the cell e and the data corresponding to the cell f in the form of optical signals, the third optical port 32 converts the data corresponding to the cell e and the data corresponding to the cell f into data in the form of electrical signals, and sends the converted data to the third FPGA through the second high-speed interface of the third FPGA. And then, the third FPGA combines the data corresponding to the cell b and the data corresponding to the cell e, and sends the combined data to a third ASIC for processing. And after the third ASIC completes the digital intermediate frequency function, all functions of the third RRU are realized through the connected transceiver and the radio frequency link.

The third FPGA sends the data corresponding to the cell c to the fourth optical port 1 through a third high-speed interface of the third FPGA, and the fourth optical port 1 converts the data corresponding to the cell c into data in an optical signal form and sends the converted data to the third optical port 41. The third FPGA sends the data corresponding to the cell f to the fourth optical port 3 through the fourth high-speed interface of the third FPGA, and the fourth optical port 3 converts the data corresponding to the cell f into data in an optical signal form and sends the converted data to the third optical port 42. After receiving the data corresponding to the cell c in the optical signal form, the third optical port 41 converts the data corresponding to the cell c into data in the electrical signal form, and sends the converted data to the fourth FPGA through the first high-speed interface of the fourth FPGA. Meanwhile, after receiving the data corresponding to the cell f in the form of the optical signal, the third optical port 42 converts the data corresponding to the cell f into data in the form of an electrical signal, and sends the converted data to the fourth FPGA through the second high-speed interface of the fourth FPGA. And the fourth FPGA combines the data corresponding to the cell c and the data corresponding to the cell f, and sends the combined data to a fourth ASIC for processing. And after the fourth ASIC completes the digital intermediate frequency function, all functions of the fourth RRU are realized through the connected transceiver and the radio frequency link.

The specific process of processing the uplink data signal by the radio frequency unit forwarding interface architecture provided in this embodiment will be described below.

And after the fourth ASIC obtains the data corresponding to the cell c and the data corresponding to the cell f through the connected transceiver and the radio frequency link, the data corresponding to the cell c and the data corresponding to the cell f are sent to the fourth FPGA through a first high-speed interface and a second high-speed interface of the fourth FPGA.

The fourth FPGA sends the data corresponding to the cell c to the third optical port 41 through the first high-speed interface of the fourth FPGA, and the third optical port 41 converts the received data corresponding to the cell c in the form of an electrical signal into data in the form of an optical signal and sends the converted data to the fourth optical port 1. The fourth FPGA sends the data corresponding to the cell f to the third optical port 42 through the second high-speed interface of the fourth FPGA, and the third optical port 42 converts the received data corresponding to the cell f in the form of an electrical signal into data in the form of an optical signal and sends the converted data to the fourth optical port 3. Then, after receiving the data corresponding to the cell c, the fourth optical port 1 converts the data corresponding to the cell c in the optical signal form into data in the electrical signal form, and sends the converted data to the third FPGA through a third high-speed interface of the third FPGA. After receiving the data corresponding to the cell f, the fourth optical port 3 converts the data corresponding to the cell f in the form of an optical signal into data in the form of an electrical signal, and sends the converted data to the third FPGA through a fourth high-speed interface of the third FPGA. And after the third ASIC obtains the data corresponding to the cell b and the data corresponding to the cell e through the connected transceiver and the radio frequency link, the data corresponding to the cell b and the data corresponding to the cell e are sent to the third FPGA through a first high-speed interface and a second high-speed interface of the third FPGA.

And the third FPGA merges the data corresponding to the cell b and the data corresponding to the cell c, and sends the merged data to the third optical port 31 through the first high-speed interface of the third FPGA. Meanwhile, the third FPGA merges the data corresponding to the cell e and the data corresponding to the cell f, and sends the merged data to the third optical port 32 through the second high-speed interface of the third FPGA. The third optical port 31 converts the received data of the combined cell b and cell c into data in the form of an optical signal, and transmits the converted data to the second optical port 1. Then, the third optical port 32 converts the received data of the cell e and the cell f after being combined into data in the form of optical signals, and transmits the converted data to the second optical port 2. After receiving the combined data of the cell b and the cell c, the second optical port 1 converts the data in the form of optical signals into data in the form of electrical signals, and sends the converted data to the first FPGA through a third high-speed interface of the first FPGA. And then, after receiving the data corresponding to the merged cell e and cell f, the second optical port 2 converts the data in the form of optical signals into data in the form of electrical signals, and sends the converted data to the first FPGA through a fourth high-speed interface of the first FPGA. And after the first ASIC obtains the data corresponding to the cell a and the data corresponding to the cell d through the connected transceiver and the radio frequency link, the data corresponding to the cell a and the data corresponding to the cell d are sent to the first FPGA through a first high-speed interface and a second high-speed interface of the first FPGA.

The first FPGA combines the data corresponding to the cell a and the combined data of the cell b and the cell c again, and sends the combined data to the first optical port 1 through a first high-speed interface of the first FPGA. Meanwhile, the first FPGA combines the data corresponding to the cell d and the combined data of the cell e and the cell f again, and sends the combined data to the first optical port 2 through the second high-speed interface of the first FPGA. Then, the first optical port 1 converts the received data of the cell a, the cell b, and the cell c after being combined into data in the form of an optical signal, and transmits the converted data to the baseband board 1. The first optical port 2 converts the received data of the cell d, the cell e, and the cell f after being combined into data in an optical signal form, and sends the converted data to the baseband board 2.

The embodiment of the utility model provides a still provide a basic station, this basic station includes that at least two baseband boards and foretell radio frequency unit pass interface framework before, and the first end and a baseband board of every first light mouth are connected.

It should be understood that, in the foregoing architecture of the radio frequency unit forward interface, the first end of each first optical port is connected to one baseband board. Therefore, the number of the base band plates is the same as the number of the first optical ports. In a particular implementation, the at least two baseband boards described above can be considered to be located in one BBU.

It should be understood that the number of the base band plates in the present embodiment is not particularly limited herein. As shown in fig. 1, in some embodiments, the number of the base band plates is two, and the number of the first optical ports is four. In other embodiments, as shown in fig. 2, the number of the base band plates is three, and the number of the first optical ports is four. In still other embodiments, as shown in fig. 3, the number of the base band plates is two and the number of the first light ports is three.

It should be understood that the baseband board may carry data and interact with the first RRU through the first end of the corresponding first optical port. Generally, each baseband board may carry data of at least one cell in units of cells.

The radio frequency unit forwarding interface architecture included in this embodiment is the radio frequency unit forwarding interface architecture in the above embodiment, and specific structures may refer to the description in the above embodiment, which is not described herein again. Since the radio frequency unit forward interface architecture in the above embodiment is adopted in this embodiment, the base station provided in this embodiment has all the beneficial effects of the radio frequency unit forward interface architecture in the above embodiment.

The foregoing is a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.

Claims (10)

1. A radio frequency unit forwarding interface architecture, comprising:

the remote control system comprises a first remote radio unit, a second remote radio unit and a control unit, wherein the first remote radio unit comprises a first programmable logic gate array used for merging or separating data, a first application specific integrated circuit, at least two first optical ports and at least one second optical port;

wherein the first array of programmable logic gates comprises a plurality of first high-speed interfaces, the first array of programmable logic gates being connected to the first application specific integrated circuit through a portion of the first high-speed interfaces;

the first end of each first optical port is connected with a baseband board, and the second end of each first optical port is connected with the first programmable logic gate array through one first high-speed interface;

the first end of each second optical port is used for being connected with a radio remote unit of a later stage, and the second end of each second optical port is connected with the first programmable logic gate array through one first high-speed interface.

2. The radio unit forwarding interface architecture of claim 1, further comprising: at least one second remote radio unit;

each second remote radio unit comprises a second programmable logic gate array used for carrying out merging or separation processing on data, a second application specific integrated circuit, at least two third optical ports and at least one fourth optical port;

wherein the second array of programmable logic gates comprises a plurality of second high speed interfaces, the second array of programmable logic gates being connected to the second application specific integrated circuit through a portion of the second high speed interfaces;

the first end of at least one third optical port is connected with a radio remote unit of a previous stage, and the second end of each third optical port is connected with the second programmable logic gate array through one second high-speed interface;

the first end of at least one fourth optical port is used for being connected with a radio remote unit of a later stage, and the second end of each fourth optical port is connected with the second programmable logic gate array through one second high-speed interface.

3. The radio unit forwarding interface architecture of claim 2, wherein the first remote radio unit is cascaded with the at least one second remote radio unit.

4. The radio unit fronthaul interface architecture according to any of claims 1-3, wherein the number of the first optical ports is two or three.

5. The radio unit forwarding interface architecture of claim 2, wherein the at least one second remote radio unit comprises two second remote radio units; the two second remote radio units are a third remote radio unit and a fourth remote radio unit; the first remote radio unit, the third remote radio unit and the fourth remote radio unit are sequentially cascaded together.

6. The radio unit fronthaul interface architecture of claim 5, wherein the first radio remote unit comprises two of the first optical ports, wherein one of the first optical ports is connected to a first baseband board through a first end thereof, and the other of the first optical ports is connected to a second baseband board through a first end thereof.

7. The radio unit fronthaul interface architecture according to claim 6, wherein the first radio remote unit includes a second optical port, the third radio remote unit includes two third optical ports and a fourth optical port, and the fourth radio remote unit includes two third optical ports and a fourth optical port;

one of the second optical ports in the first remote radio unit is connected to any one of the third optical ports in the third remote radio unit, and one of the fourth optical ports in the third remote radio unit is connected to any one of the third optical ports in the fourth remote radio unit.

8. The radio unit forwarding interface architecture according to claim 6, wherein the first remote radio unit includes two second optical ports, the third remote radio unit includes two third optical ports and two fourth optical ports, and the fourth remote radio unit includes two third optical ports and two fourth optical ports;

the two second optical ports in the first remote radio unit are respectively connected with the two third optical ports in the third remote radio unit, and the two fourth optical ports in the third remote radio unit are respectively connected with the two third optical ports in the fourth remote radio unit.

9. The radio unit fronthaul interface architecture of claim 1, wherein the first asic comprises two asic interfaces, at least one of the two asic interfaces being connected to two of the plurality of first high speed interfaces.

10. A base station comprising at least two baseband boards and a radio unit fronthaul interface architecture according to any of claims 1-9, a first end of each of the first optical ports being connected to one of the baseband boards.

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