CN217280825U

CN217280825U - Nano-patterned composite substrate and high-light quantum efficiency LED chip

Info

Publication number: CN217280825U
Application number: CN202221031777.0U
Authority: CN
Inventors: 王峰; 周林华; 赵海琴
Original assignee: Suzhou Ruiermei Photoelectric Technology Co ltd
Current assignee: Suzhou Ruiermei Photoelectric Technology Co ltd
Priority date: 2022-04-29
Filing date: 2022-04-29
Publication date: 2022-08-23
Anticipated expiration: 2032-04-29

Abstract

The utility model discloses a nanometer graphical composite substrate, including the sapphire substrate, the sapphire substrate has at least one side polishing face, polishing face is equipped with first indium tin oxide transparent conducting layer, first indium tin oxide transparent conducting layer is equipped with netted hole form nanometer graphical structure layer, netted hole form nanometer graphical structure layer includes a plurality of nanometer line width meshes that are the array and arrange. According to the composite substrate, the nano graphical structure is prepared on the indium tin oxide transparent conducting layer, on one hand, the coarsening of the bottom of the epitaxial layer is facilitated, the light quantum efficiency of an LED chip is improved, and therefore the light emitting is improved, on the other hand, the nano graphical structure is helpful for solving the problem of lattice mismatch between the planar sapphire substrate and the GaN epitaxial layer caused by different materials, and the release of stress of the GaN epitaxial layer in the epitaxial process is facilitated.

Description

Nano-patterned composite substrate and high-light quantum efficiency LED chip

Technical Field

The utility model belongs to the technical field of the LED chip, specifically relate to a graphical composite substrate of nanometer and high light quantum efficiency LED chip.

Background

GaN epitaxy is grown primarily on sapphire substrates. Because the crystal structure of the sapphire substrate and the crystal structure of the GaN material are the same as the crystal structure of the zinc blende with six cubes, the crystal structures are relatively close, and the thermal expansion coefficients of the two materials are also relatively close, the sapphire substrate is relatively suitable for growing GaN epitaxy. In addition, sapphire substrates have many advantages: firstly, the production technology of the sapphire substrate is mature, the crystal structure is close to that of a GaN material, and the quality of a grown GaN epitaxial device is good; secondly, the chemical property of the sapphire is relatively stable and can be applied to the high-temperature growth process; finally, sapphire is mechanically strong and easy to handle and clean. Therefore, most GaN epitaxy processes typically use sapphire as the substrate.

The LED structure prepared by GaN epitaxy in the early stage is directly prepared by epitaxy on a plane sapphire substrate, then in order to improve the light-emitting quantum efficiency, a patterned sapphire substrate with a micron-scale patterned size structure is directly etched on the plane sapphire substrate (usually, the patterned size is 2.6-2.8 um in bottom width, 0.3um in spacing and 1.6-1.8 um in height), and then in order to further improve the light quantum efficiency and release the epitaxial stress, the micron-scale patterned size structure is developed into a nano-scale patterned size structure. However, because the sapphire has very high hardness, the difficulty of preparing the nano-scale patterning on the sapphire body is high, and the cost is high. Due to the insulating property of the sapphire body, the nano patterned structure layer is also insulating, and the nano patterned structure with the insulating surface layer can only be used for preparing a single PN structure LED chip structure.

Although the sapphire substrate and the GaN material have relatively close crystal structures, the two materials are heteroepitaxy, so that certain problems of lattice mismatch and thermal stress mismatch exist, and a large number of crystal defects are generated in GaN epitaxy, so that the yield in subsequent chip manufacturing processes is reduced. The utility model discloses consequently come.

SUMMERY OF THE UTILITY MODEL

To the technical problem who exists above-mentioned, the utility model aims at: the nanometer graphical composite substrate and the LED chip with high light quantum efficiency are provided, the composite substrate is provided with the nanometer graphical structure on the indium tin oxide transparent conducting layer, on one hand, the coarsening of the bottom of the epitaxial layer is facilitated, the reflection efficiency is improved, and therefore the light emitting is improved, on the other hand, the nanometer graphical structure is helpful for solving the problem of lattice mismatch caused by different materials between the plane sapphire substrate and the GaN epitaxial layer, and the release of stress of the GaN epitaxial layer in the epitaxial process is facilitated. The LED chip with a plurality of quantum wells can be prepared on the composite substrate, so that the light quantum efficiency of the LED chip is improved, and the brightness is improved.

The technical scheme of the utility model is that:

a nano-patterned composite substrate comprises a sapphire substrate, wherein the sapphire substrate is provided with at least one polished surface, the polished surface is provided with a first indium tin oxide transparent conducting layer, the first indium tin oxide transparent conducting layer is provided with a meshed nano-patterned structural layer, and the meshed nano-patterned structural layer comprises a plurality of nano-scale line width meshes which are arranged in an array mode.

In a preferred technical scheme, the thickness of the first indium tin oxide transparent conducting layer is 200-500 nm.

In the preferred technical scheme, the diameter of the nanometer line width mesh is 300-700 nm, and the distance is 1-2 um.

In a preferred technical scheme, the nanometer line width meshes penetrate through the whole first indium tin oxide transparent conducting layer.

The utility model also discloses a high light quantum efficiency LED chip, be equipped with p-GaN buffer layer, first p-GaN layer, first multiple quantum well, n-GaN layer, second multiple quantum well and second p-GaN layer in proper order on the netted nanometer graphical structure layer of sapphire composite substrate in above-mentioned arbitrary item, p-GaN buffer layer, first p-GaN layer, first multiple quantum well, and n-GaN layer constitute first luminous PN junction; the n-GaN layer, the second multiple quantum well and the second p-GaN layer form a second light-emitting PN junction.

In a preferred technical scheme, a second transparent conducting layer is arranged on the second p-GaN layer.

In a preferred technical scheme, the thickness of the second transparent conducting layer is 150-250 nm.

In a preferred technical solution, the material of the second transparent conductive layer is one or a mixture of more of indium tin oxide, fluorine tin oxide, barium tin oxide, and graphene.

In a preferred technical scheme, a first P-type electrode is arranged on the first indium tin oxide transparent conducting layer, an n-type electrode is arranged on the n-GaN layer, and a second P-type electrode is arranged on the second transparent conducting layer.

In the preferred technical scheme, the P-GaN buffer layer extends crystals from the polished surface of the sapphire substrate at the bottom of the nanometer-scale line width mesh and covers the whole nanometer-scale line width mesh.

Compared with the prior art, the utility model has the advantages that:

1. according to the composite substrate, the nano graphical structure is prepared on the indium tin oxide transparent conducting layer, on one hand, the coarsening of the bottom of the epitaxial layer is facilitated, the reflection efficiency is improved, and therefore the light emitting is improved, on the other hand, the nano graphical structure is helpful for solving the problem of lattice mismatch between the planar sapphire substrate and the GaN epitaxial layer caused by different materials, and the release of stress of the GaN epitaxial layer in the epitaxial process is facilitated.

2. The LED chip prepared by the composite substrate has the advantages that two PN junctions emit light, the two PN junctions emit light simultaneously, the light emitting efficiency is high, the traditional single PN junction light emitting structure mode is changed, the light emitting efficiency is doubled, and the brightness is greatly improved. Is suitable for large-scale batch production.

Drawings

The invention will be further described with reference to the following drawings and examples:

fig. 1 is a schematic structural diagram of a nano-patterned composite substrate according to the present invention;

FIG. 2 is a plan view of the mesh-like nano-patterned structure of the present invention;

fig. 3 is an SEM image of the mesh-like nanopatterned structure of the present invention;

fig. 4 is a schematic diagram of a high quantum efficiency LED chip of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings. It should be understood that the description is intended to be illustrative only and is not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.

The embodiment is as follows:

as shown in fig. 1, a nano-patterned composite substrate 100 includes a sapphire substrate 1, the sapphire substrate 1 has at least one polished surface, the polished surface is provided with a first Indium Tin Oxide (ITO) transparent conductive layer 2, the first Indium Tin Oxide (ITO) transparent conductive layer 2 is provided with a mesh-shaped nano-patterned structure layer 21, and the mesh-shaped nano-patterned structure layer 21 includes a plurality of nano-scale line-width meshes 13 arranged in an array.

As shown in fig. 2 and 3, the nanopatterned composite substrate 100 is also provided with a composite substrate guide edge 16, which serves as a guide edge for the crystal orientation.

Specifically, a single-side polished or double-side polished flat sapphire substrate is selected as a base plate, and the surface roughness of the polished surface of the sapphire substrate 1 is less than or equal to 0.3 nm. A first ITO (indium tin oxide) transparent conductive layer 2 is prepared on the polished surface of a planar sapphire substrate 1 by a sputtering method.

In a preferred embodiment, the thickness of the first ITO transparent conductive layer 2 is 200-500 nm.

Specifically, the mesh-shaped nanopatterned structure layer 21 is prepared by nanoimprint lithography on the first Indium Tin Oxide (ITO) transparent conductive layer 2.

In a preferred embodiment, the diameter of the nano-sized line-width mesh 13 is 300 to 700nm, and the pitch is 1 to 2 um.

In a preferred embodiment, the nano-sized wire-width mesh 13 extends through the entire first ito transparent conductive layer 2, i.e. the bottom of the nano-sized wire-width mesh 13 is the polished surface of the planar sapphire substrate 1.

In another embodiment, as shown in fig. 3, a high light quantum efficiency LED chip is disclosed, wherein a p-GaN buffer layer 3, a first p-GaN layer 4, a first Multiple Quantum Well (MQWs) 5, an n-GaN layer 7, a second Multiple Quantum Well (MQWs) 8, and a second p-GaN layer 9 are sequentially disposed on the mesh-shaped nanopatterned structure layer 21 of the nanopatterned composite substrate 100, and the p-GaN buffer layer 3, the first p-GaN layer 4, the first Multiple Quantum Well (MQWs) 5, and the n-GaN layer 7 form a first light emitting PN junction; the n-GaN layer 7, the second multiple quantum well 8, and the second p-GaN layer 9 constitute a second light emitting PN junction.

Specifically, each layer may be epitaxially grown on the surface of the nano-patterned composite substrate 100 in sequence by a Metal Organic Chemical Vapor Deposition (MOCVD) method.

In a preferred embodiment, a second transparent conductive layer 10 is disposed on the second p-GaN layer 9.

Specifically, the second transparent conductive layer 10 can be prepared by a sputtering method, and the thickness of the second transparent conductive layer 10 is 150-250 nm. The material of the second transparent conductive layer 10 may be one or more of Indium Tin Oxide (ITO), fluorine tin oxide, barium tin oxide, or graphene, and preferably Indium Tin Oxide (ITO) in the present invention.

Specifically, the P-GaN buffer layer 3 extends crystal from the polished surface of the sapphire substrate 1 at the bottom of the nanometer-scale line width mesh 13 and covers the whole nanometer-scale line width mesh 13, and is used for further improving the crystal quality during the subsequent epitaxial layer growth, reducing the defects during the crystal growth and reducing the stress.

In a preferred embodiment, a first P-type electrode 6 is disposed on the first ITO transparent conductive layer 2, an n-type electrode 11 is disposed on the n-GaN layer 7, and a second P-type electrode 12 is disposed on the second transparent conductive layer 10.

Specifically, the first P-type electrode 6, the n-type electrode 11, and the second P-type electrode 12 may be fabricated by using a semiconductor chip electrode fabrication process such as mask lithography, ICP etching, sputtering or evaporation, and metal lift-off. The materials of the first P-type electrode 6, the n-type electrode 11 and the second P-type electrode 12 are one or more of chromium, platinum, gold, nickel, titanium, copper, indium, tin, lead, silver and other metal materials.

And forming ohmic contact between the metal layers of each electrode area and the p-GaN semiconductor layer by using an alloy process method.

It is to be understood that the above-described embodiments of the present invention are merely illustrative of or explaining the principles of the invention and are not to be construed as limiting the invention. Therefore, any modification, equivalent replacement, improvement and the like made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. Further, it is intended that the appended claims cover all such variations and modifications as fall within the scope and boundaries of the appended claims or the equivalents of such scope and boundaries.

Claims

1. The nano-patterned composite substrate comprises a sapphire substrate and is characterized in that the sapphire substrate is provided with at least one polished surface, the polished surface is provided with a first indium tin oxide transparent conductive layer, the first indium tin oxide transparent conductive layer is provided with a meshed nano-patterned structure layer, and the meshed nano-patterned structure layer comprises a plurality of nano-line width meshes which are arranged in an array.

2. The nanopatterned composite substrate according to claim 1, wherein the first indium tin oxide transparent conductive layer has a thickness of 200 to 500 nm.

3. The nanopatterned composite substrate according to claim 1, wherein the nano-sized line-width mesh has a diameter of 300 to 700nm and a pitch of 1 to 2 um.

4. The nanopatterned composite substrate of claim 1, wherein the nanoscale wire-width mesh extends through the entire first indium tin oxide transparent conductive layer.

5. A high light quantum efficiency LED chip is characterized in that a p-GaN buffer layer, a first p-GaN layer, a first multiple quantum well, an n-GaN layer, a second multiple quantum well and a second p-GaN layer are sequentially arranged on the mesh-shaped nano patterned structural layer of the nano patterned composite substrate according to any one of claims 1 to 4, wherein the p-GaN buffer layer, the first p-GaN layer, the first multiple quantum well and the n-GaN layer form a first light emitting PN junction; the n-GaN layer, the second multiple quantum well and the second p-GaN layer form a second light-emitting PN junction.

6. The LED chip with high optical quantum efficiency of claim 5, wherein a second transparent conductive layer is disposed on the second p-GaN layer.

7. The LED chip with high optical quantum efficiency according to claim 6, wherein the thickness of the second transparent conductive layer is 150-250 nm.

8. The LED chip with high optical quantum efficiency according to claim 6, wherein the material of the second transparent conductive layer is one or more of indium tin oxide, fluorine tin oxide, barium tin oxide or graphene.

9. The LED chip of claim 6, wherein a first P-type electrode is disposed on the first ITO transparent conductive layer, an n-type electrode is disposed on the n-GaN layer, and a second P-type electrode is disposed on the second transparent conductive layer.

10. The LED chip according to claim 5, wherein the P-GaN buffer layer extends the crystal from the polished surface of the sapphire substrate at the bottom of the nanometer-scale line-width mesh and covers the entire nanometer-scale line-width mesh.