CN217160063U

CN217160063U - LED lattice module

Info

Publication number: CN217160063U
Application number: CN202122679326.XU
Authority: CN
Inventors: 不公告发明人
Original assignee: Guangzhou Zhongyuan Intelligent Technology Co ltd
Current assignee: Guangzhou Zhongyuan Intelligent Technology Co ltd
Priority date: 2021-11-03
Filing date: 2021-11-03
Publication date: 2022-08-09
Anticipated expiration: 2031-11-03

Abstract

The embodiment of the application provides a LED dot matrix module, and this module includes: the LED array circuit comprises a controller, a decoding circuit and an LED dot matrix circuit; the controller transmits address driving signals to the decoding circuit through the at least two first driving signal output ends and the at least two address driving signal input ends; the LED lattice circuit comprises a plurality of rows of LED lamps; each line of LED lamps is respectively connected with one first signal output end of the decoding circuit, the first signal output ends connected with the LED lamps in each line correspond to different address driving signals one by one, the decoding circuit receives the address driving signals, and the decoding circuit controls the LED lamps to be lightened line by line through the address driving signals. The embodiment of the application can prevent the LED from flickering when the multi-row LED lamp is switched and lightened.

Description

LED lattice module

Technical Field

The embodiment of the application relates to the field of LED dot matrix driving, in particular to an LED dot matrix module.

Background

The existing LED lattice module is driven by using an LED lattice, generally, a discrete row-column driving circuit is built by an integrated digital logic chip, the row-column driving circuit controls the LED lattice by receiving a driving signal of a controller, in some technologies, a decoding circuit receives the driving signal of the controller to perform row switching control of the LED lattice, and other circuits receive the driving signal of the controller to perform column switching control of the LED lattice.

The inventor finds that: when the decoding circuit receives the address driving signal of the controller to perform line switching on the LED dot matrix circuit to light the LED lamp, the decoding circuit determines the address driving signal according to the combination of the signals output by at least two address driving signal output ends of the controller, the controller changes the signals output by the address driving output ends bit by bit, and when the controller changes the address signals output by the address driving signal output ends, the address driving signal received by the decoding circuit cannot be completely and synchronously changed, so that the problem that the LED lamp flickers due to inaccurate address driving signal received by the decoding circuit is temporarily caused.

SUMMERY OF THE UTILITY MODEL

In order to overcome the problems existing in the related art, the application provides an LED dot matrix module which has the advantage that the LED lamp can be prevented from flickering when the LED dot matrix is switched.

According to an aspect of an embodiment of the present application, there is provided an LED dot matrix module, including: the LED array circuit comprises a controller, a decoding circuit and an LED dot matrix circuit;

the decoding circuit comprises at least two address driving signal input ends and a plurality of first signal output ends; the controller comprises a first set of drive signal outputs; the first group of driving signal output ends comprise at least two first driving signal output ends; the controller transmits address driving signals to the decoding circuit through the at least two first driving signal output ends and the at least two address driving signal input ends;

the LED dot matrix circuit comprises a plurality of rows of LED lamps; each row of LED lamps is correspondingly connected with one path of first signal output end of the decoding circuit, and the first signal output ends connected with each row of LED lamps correspond to different address driving signals one by one; and the decoding circuit receives the address driving signal and controls the LED lamps to be lightened line by line through the address driving signal.

The decoding circuit of the embodiment of the application comprises at least two address driving signal input ends and a plurality of first signal output ends; the controller comprises a first group of driving signal output ends; the first group of driving signal output ends comprise at least two first driving signal output ends; the at least two first driving signal output ends are connected with the at least two address driving signal input ends in a one-to-one correspondence manner; the controller passes through two at least first drive signal output ends with two at least address drive signal input ends to decoding circuit transmission address drive letter, and every line of LED lamp correspond with decoding circuit's a first signal output end is connected, the different address drive signal of the first signal output end one-to-one that every line of LED lamp is connected, decoding circuit receives address drive signal, just decoding circuit passes through address drive signal control LED lamp lights row by row to prevent the problem of LED scintillation.

In one embodiment, the address driving signals corresponding to the first signal output ends connected with the LED lamps of the adjacent switching lighting rows are different by only one bit; the decoding circuit comprises a decoder and a plurality of rows of first control switches; the decoder comprises at least two signal input ends and a plurality of signal output ends; one path of signal input end of the decoder corresponds to one path of address driving signal input end of the decoding circuit, and the enabling end of each row of the first control switch is correspondingly connected with one path of signal output end of the decoder; the input end of each row of the first control switch is grounded; the output end of each row of the first control switch is connected with the corresponding row of the LED lamps, so that the LED lamps can be switched only by changing the output signal of one path of the first driving signal output end of the controller, the problem of LED flicker is prevented, meanwhile, the output signal of the first driving signal output end can be frequently changed by the controller, the occupation of memory codes of the controller is reduced, and the efficiency is improved.

In one embodiment, the LED lattice circuit further comprises a plurality of columns of LED lamps, and a plurality of rows of the LED lamps and a plurality of columns of the LED lamps are arranged in a mutually crossed manner to form an LED lamp array;

the LED dot matrix module also comprises a sequential logic circuit; the sequential logic circuit comprises a sequential driving signal input end and a plurality of paths of second signal output ends;

the controller further comprises a second set of drive signal outputs; the second group of driving signal output ends are connected with a time sequence driving signal input end of the time sequence logic circuit, and the controller transmits a time sequence driving signal to the time sequence logic circuit through the second group of driving signal output ends and the time sequence driving signal input end; each row of the LED lamps is correspondingly connected with one path of second signal output end of the sequential logic circuit; and the sequential logic circuit receives the sequential driving signal and controls the row LED lamps connected with the second signal output end corresponding to the sequential driving signal to be on.

The sequential driving signal is received through the sequential logic circuit, and the row LED lamps connected with the second signal output ends corresponding to the sequential driving signal are controlled to be turned on, so that the lighting control of the row LED lamps is conveniently realized.

In one embodiment, the sequential logic circuit further comprises a clear signal input; the zero clearing signal input end is connected with a first signal output end of one path of the decoding circuit; after the row LED lamps are sequentially lightened, the decoding circuit outputs a zero clearing signal to the zero clearing signal input end, and then the idle first signal output end in the decoding circuit is used for carrying out zero clearing control on the sequential logic circuit, so that the occupation of a port of the controller can be saved, the idle first signal output end of the decoding circuit can be used, and the full utilization of resources is realized.

In one embodiment, the second set of drive signal outputs comprises a clock signal output and a data signal output; the time sequence driving signal input end of the time sequence logic circuit comprises a clock signal input end and a data signal input end; the clock signal output end is connected with the clock signal input end; the data signal output end is connected with the data signal input end. The controller inputs a sequential driving signal to the sequential logic circuit through the data signal output end and the data signal input end, and the controller inputs a clock signal to the sequential logic circuit through the clock signal output end and the clock signal input end, so that the sequential logic circuit changes the sequential driving signal output by the second driving signal output end according to the clock signal, and further the precise control of the sequential logic circuit is realized.

In one embodiment, the sequential logic circuit includes a shift register and a plurality of columns of second control switches; the shift register comprises a signal input end and a plurality of paths of signal output ends; the signal input end of the shift register corresponds to the time sequence driving signal input end of the time sequence logic circuit; the enabling end of each row of the second control switches is correspondingly connected with one signal output end of the shift register; the input end of each column of the second control switch is grounded; the output end of each row of second control switches corresponds to one path of second signal output end of the sequential logic circuit, and the output end of each row of second control switches is connected with the corresponding row of LED lamps. According to the embodiment of the application, the shift register is used for receiving the time sequence driving signal sent by the controller, and the shift register is used for controlling the LED lamps connected with the corresponding signal output ends to be lightened so as to conveniently control the LED lamps in the corresponding row.

In one embodiment, the second control switch comprises a second triode and a second current limiting resistor; the base electrode of the second triode is connected with one signal output end of the shift register through the second current limiting resistor, the emitting electrode of the second triode is connected with the power supply, and the collecting electrode of the second triode is connected with the LED lamps in the corresponding row. And after the second triode expands the current of the signal output by the decoder, the signal is input into the LED lamp, so that the LED lamp can be normally switched on and off within a control range.

In one embodiment, the first control switch comprises a first triode and a first current limiting resistor; the base electrode of the first triode is connected with one signal output end of the decoder through the first current limiting resistor, the emitting electrode of the first triode is grounded, and the collecting electrode of the first triode is connected with the LED lamp in the corresponding row. According to the embodiment of the application, the first triode is used for amplifying the current of the signal output by the decoder and then inputting the current to the LED lamp, so that the LED lamp can be normally switched on and off within a control range.

In one embodiment, the LED lattice circuit further includes a first capacitor and a second capacitor connected in parallel, one end of each of the first capacitor and the second capacitor connected in parallel is connected to the power supply, and the other end of each of the first capacitor and the second capacitor connected in parallel is grounded for power supply filtering.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

For a better understanding and practice, the invention is described in detail below with reference to the accompanying drawings.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic circuit diagram of an LED dot matrix module according to an embodiment;

FIG. 2 is a schematic block diagram of an LED dot matrix module according to an embodiment of the present application;

FIG. 3 is a schematic block diagram of an LED dot matrix module according to another embodiment of the present application;

FIG. 4 is a schematic block diagram of an LED dot matrix module according to yet another embodiment of the present application;

FIG. 5 is a circuit diagram of an LED dot matrix module according to one embodiment of the present application;

10-controller, 101-first group of driving signal output ends, 1011-at least two first driving signal output ends, 102-second group of driving signal output ends, 20-decoding circuit, 201-at least two address driving signal input ends, 202-multi-path first signal output ends, 203-decoder, 204-multi-row first control switch, 30-LED lattice circuit, 301-multi-row LED lamp, 302-multi-row LED lamp, 40-time sequence logic circuit, 401-time sequence driving signal input end, 402-multi-path second signal output end, 403-zero clearing signal input end, 404-shift register and 405-multi-row second control switch.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated.

In the description of the present application, it is to be understood that the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not necessarily used to describe a particular order or sequence, nor are they to be construed as indicating or implying relative importance. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The word "if/if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination". Further, in the description of the present application, "a plurality" means two or more unless otherwise specified. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

In order to better understand the technical solutions of the present application, some technical solutions will be described below.

The inventor discovers that in the process of implementing the application: when the decoding circuit receives the address driving signal of the controller to switch the LED dot matrix to light the LED lamp, the problem of LED flicker occurs.

Specifically, please refer to fig. 1, which is a schematic circuit diagram of an LED dot matrix module according to an embodiment. The LED dot matrix module includes a controller (not shown), a decoding circuit, and an LED dot matrix circuit 100; the LED lattice circuit comprises a first row of LED lamps, a second row of LED lamps, … and a fifth row of LED lamps; the decoding circuit comprises a decoding chip 200 and first triodes Q6, Q7, Q8, Q9 and Q10; the three-way address driving signal output end of the controller is respectively connected with the three-way address driving signal input ends A0, A1 and A2 of the decoding chip 200 in a one-to-one correspondence manner, and the controller transmits address driving signals to the decoding circuit through the three-way address driving signal output end and the three-way address driving signal input ends A0, A1 and A2 of the decoding chip 200. Five signal output ends Y0, Y1, Y2, Y3 and Y4 of the decoding chip 200 are respectively connected with the first row of LED lamps, the second row of LED lamps, … and the fifth row of LED lamps in a one-to-one correspondence manner through first triodes Q6, Q7, Q8, Q9 and Q10. The decoding circuit receives the address driving signal and controls the line LED lamps connected with the signal output end corresponding to the address driving signal to be lightened. The address driving signal is the combination of the address signals output by the three address driving signal output ends of the controller.

When the controller sequentially transmits the address driving signals of 000, 001, 010, 011 and 100 to the decoding circuit through the three-way address driving signal input end, the decoding circuit sequentially receives the address driving signals and controls the first row of LED lamps, the second row of LED lamps … and the fifth row of LED lamps connected with the five-way signal output ends Y0, Y1, Y2, Y3 and Y4 corresponding to the address driving signals to be sequentially lightened.

Since the decoding chip 200 itself has a preset address decoding rule, the decoding chip 200 has a corresponding signal output terminal for the received address driving signal, for example, when the decoding chip 200 receives the address driving signal of 010, the signal output terminal Y2 of the decoding chip 200 has an output, and the third row LED lamp controlled by the output signal of Y2 is turned on.

In the process of sequentially switching from the first row of LED lamps to the second row of LED lamps … to the fifth row of LED lamps, the address driving signals received by the decoding chip 200 are 000, 001, 010, 011 and 100 in sequence. When the address driving signal is changed from 011 to 100, two-bit address signals are changed, because the controller changes the address signal output by the address driving signal output end bit by bit, and when the controller changes the address signal output by the address driving signal output end, there is a delay of several tens of nanoseconds, that is, when the address driving signal is converted from 011 to 100, the conversion process of the address driving signal is 011 → 010 → 000 → 100, and therefore, the decoding chip receives the input of the driving address signal in sequence, and at this time, the signal output terminals Y3, Y2, Y0 and Y4 of the corresponding decoding chips will have outputs in turn, therefore, after the fourth row of LED lamps connected with the signal output end Y3 is turned off, the third row of LED lamps connected with the signal output end Y2 flickers briefly, the first row of LED lamps connected with the signal output end Y0 flickers briefly, and then the fifth row of LED lamps connected with the signal output end Y4 is turned on. That is, during the process of switching from the fourth line lighting to the fifth line lighting, the third line and the first line are briefly lighted, so that the line-by-line lighting of the LED dot matrix circuit cannot be really realized.

It should be noted that the rows and columns in the embodiments of the present application are only used for distinguishing similar objects, and are not necessarily used for describing specific arrangement objects, and are not understood to indicate or imply relative importance, and the rows and columns in the present application are relative and can be switched, that is, the manner of connection and control of the devices arranged in the form of rows in the present application is also applicable to the manner of connection and control of the devices arranged in the form of columns.

Please refer to fig. 2, which is a schematic block diagram of an LED dot matrix module according to an embodiment of the present application, the LED dot matrix module according to the embodiment of the present application includes: controller 10, decoding circuit 20 and LED dot matrix circuit 30.

The decoding circuit 20 includes at least two address driving signal input terminals 201 and a plurality of first signal output terminals 202; the controller 10 comprises a first set of drive signal outputs 101; the first group of driving signal output terminals 101 includes at least two first driving signal output terminals 1011; the at least two first driving signal output ends 1011 are connected to the at least two address driving signal input ends 201 in a one-to-one correspondence manner, and the controller 10 transmits the address driving signals to the decoding circuit 20 through the first driving signal output ends 1011 and the address driving signal input ends 201.

The LED dot matrix circuit 30 includes a plurality of rows of LED lamps 301, each row of LED lamps is correspondingly connected to one of the first signal output terminals of the decoding circuit 20, and the first signal output terminals connected to each row of LED lamps correspond to different address driving signals; the decoding circuit 20 controls the LED lamps to be lighted line by line through the address driving signal.

The controller 10 is any device that can implement the technical solution of the present application, and may include one or more processing cores, for example, the controller 10 may be implemented by a microcontroller MCU and other devices, and the specific type and model of the controller 10 are not limited in the present application.

The decoding circuit 20 is any device capable of implementing the technical solution of the present application, and is capable of receiving an address driving signal transmitted by the controller 10, and controlling the first signal output terminal corresponding to the decoding circuit 20 to output a signal according to an address decoding rule of the decoding circuit 20, so as to drive the LED lamp connected to the first signal output terminal to operate, that is, the decoding circuit 20 has a signal output terminal corresponding to the received address driving signal, and according to the address driving signal, can control the first signal output terminal corresponding to the decoding circuit 20 to output a signal, so as to drive the LED lamp connected to the first signal output terminal to operate. Illustratively, the decoding circuit 20 may be a circuit composed of a decoder and a transistor, or the decoding circuit 20 may be a chip integrating the decoder and the transistor.

The address driving signal is a combination of signals output by at least two first driving signal output ends, that is, the address signal output by one of the first driving signal output ends is different, and the address driving signals are also different.

The decoding circuit 20 of the embodiment of the present application includes at least two address driving signal input terminals 201 and multiple first signal output terminals 202; the controller 10 comprises a first set of drive signal outputs 101; the first group of driving signal output terminals 101 includes at least two first driving signal output terminals 1011; the at least two first driving signal output ends 1011 are connected with the at least two address driving signal input ends 201 in a one-to-one correspondence manner; the controller 10 transmits the address driving signal to the decoding circuit 20 through the first driving signal output end 1011 and the address driving signal input end 201, each row of LED lamps is correspondingly connected with one path of first signal output end of the decoding circuit 20, the first signal output ends connected with the LED lamps in each row correspond to different address driving signals one by one, the decoding circuit receives the address driving signal, and the decoding circuit controls the LED lamps to be lighted line by line through the address driving signal, so that the problem of LED flickering can be prevented.

In one embodiment, address driving signals corresponding to first signal output ends connected with adjacent row LED lamps switched to be lighted are different by only one bit, and therefore switching of the LED lamps can be performed only by changing one path of output signals of the first driving signal output ends of the controller, so that the problem of LED flicker is prevented, meanwhile, the controller can be reduced, the output signals of the first driving signal output ends are frequently changed, occupation of memory codes of the controller is reduced, and efficiency is improved.

Please refer to fig. 3, which is a schematic block diagram of an LED dot matrix module according to another embodiment of the present application. In the present embodiment, the decoding circuit 20 includes a decoder 203 and a plurality of rows of first control switches 204; the decoder 203 comprises at least two signal input ends and a plurality of signal output ends; one signal input end of the decoder 203 corresponds to one address driving signal input end of the decoding circuit 20; the enabling end of the first control switch in each row is connected with one signal output end of the decoder 203; the input end of the first control switch of each row is grounded; the output end of each row of first control switches corresponds to one path of first signal output end of the decoding circuit 20 connected with the corresponding row of LED lamps, and the output end of each row of first control switches is connected with the corresponding row of LED lamps. According to the embodiment of the application, the decoder 203 receives the address driving signal sent by the controller 10, and the decoder 203 decodes the address driving signal, so that the LED lamp connected with the corresponding signal output end is conveniently controlled to be turned on.

In one embodiment, the first control switch comprises a first triode and a first current limiting resistor; the base of the first triode is connected with one signal output end of the decoder 203 through the first current limiting resistor, the emitter of the first triode is grounded, and the collector of the first triode is connected with the LED lamps in the corresponding row. After the signal output by the decoder 203 is subjected to current expansion through the first triode, the signal is input into the LED lamp, so that the LED lamp can be normally switched on and off within a current control range.

Please refer to fig. 4, which is a schematic block diagram of an LED dot matrix module according to another embodiment of the present application. In this embodiment, the LED dot matrix circuit 30 further includes a plurality of rows of LED lamps 302, and the plurality of rows of LED lamps are disposed to cross each other to form an LED lamp array.

The LED lattice module further comprises a sequential logic circuit 40; the sequential logic circuit 40 comprises a sequential driving signal input end 401 and a multi-path second signal output end 402; the controller 10 also includes a second set of drive signal outputs 102.

The second group of driving signal output ends 102 are connected to the timing driving signal input end 401 of the timing logic circuit 40, and the controller 10 transmits the timing driving signal to the timing logic circuit 40 through the second group of driving signal output ends 102 and the timing driving signal input end 401; each row of LED lamps is correspondingly connected with one path of second signal output end of the sequential logic circuit 40; the sequential logic circuit 40 receives the sequential driving signal and controls the row of LED lamps connected to the second signal output terminal corresponding to the sequential driving signal to be turned on.

The sequential logic circuit 40 may be any device that can implement the technical solution of the present application, and for example, the sequential logic circuit 40 may be a circuit composed of a shift register and a transistor, or the sequential logic circuit 40 may be a chip integrating the shift register and the transistor.

In the embodiment of the application, the sequential logic circuit 40 receives the sequential driving signal and controls the lighting of the row of LED lamps connected to the second signal output end corresponding to the sequential driving signal, so that the lighting control of the row of LED lamps is conveniently realized.

Further, with continued reference to fig. 4, in one embodiment, the sequential logic circuit 40 further includes a clear signal input terminal 403; the clear signal input terminal 403 is connected to a first signal output terminal of the decoding circuit 20. Specifically, the controller 10 outputs a periodic address driving signal to the decoding circuit 20, and in one period, the decoding circuit 20 outputs a clear signal to the sequential logic circuit after the row LED lamps are sequentially turned on according to the address driving signal. The idle first signal output end in the decoding circuit 20 is used for carrying out zero clearing control on the sequential logic circuit 40, so that not only can the port occupation of the controller 10 be saved, but also the idle first signal output end of the decoding circuit 20 can be used, and the full utilization of resources is realized.

In one embodiment, the timing driving signal comprises a clock signal and a data signal, and the second set of driving signal outputs comprises a clock signal output and a data signal output; the signal input ends of the sequential logic circuit 40 correspondingly comprise a clock signal input end and a data signal input end; the clock signal output end is connected with the clock signal input end; the data signal output end is connected with the data signal input end. The controller 10 inputs the timing driving signal to the timing logic circuit 40 through the data signal output terminal and the data signal input terminal. The controller 10 inputs a clock signal to the sequential logic circuit 40 through the clock signal output terminal and the clock signal input terminal, so that the sequential logic circuit 40 determines the sequential driving signal output by the second driving signal output terminal according to the clock signal, and further, the synchronous input of the controller 10 to the data signal of the sequential logic circuit 40 is realized through the clock signal, thereby realizing the precise control of the sequential logic circuit 40. Specifically, the timing driving signal is a series of data bit sequences composed of 0 and 1, where 0 represents a low level and 1 represents a high level; the clock signal is a square wave with a fixed period and is used for synchronizing the controller and the sequential logic circuit during the transmission of the data signal. For example, the controller may send a data bit on each rising edge of the clock signal, the sequential logic circuit may use the same clock to sample on each rising edge of the clock signal to obtain a corresponding data bit, and finally, combine the data bits obtained in one cycle to obtain a sequential driving signal; in this process, the sequential logic circuit stores the data bits collected at the rising edge of each clock, and determines the sequential driving signal according to the data bits stored in this cycle.

With continued reference to fig. 4, the sequential logic circuit 40 includes a shift register 404 and a plurality of columns of second control switches 405; shift register 404 includes a signal input terminal and a plurality of signal output terminals; the signal input terminal of the shift register 404 corresponds to the timing driving signal input terminal 401 of the timing logic circuit 40; the enable end of each row of second control switches is connected with one signal output end of the shift register 404; the input end of each column of second control switches is grounded; the output end of each row of second control switches corresponds to one path of second signal output end of the sequential logic circuit 40, and the output end of each row of second control switches 405 is connected with the corresponding row of LED lamps. In the embodiment of the present application, the sequential logic circuit 40 receives the sequential driving signal sent by the controller 10, and the sequential logic circuit 40 controls the LED lamps connected to the corresponding signal output ends to be turned on, so as to control the LED lamps in the corresponding row.

In one embodiment, the second control switch comprises a second triode and a second current limiting resistor; the base electrode of the second triode is connected with one signal output end of the shift register 404 through a second current limiting resistor, the emitting electrode of the second triode is connected with the power supply, the collecting electrode of the second triode is connected with the LED lamp of the corresponding row, and the signal output by the decoder 203 is input into the LED lamp after being expanded through the second triode, so that the LED lamp is controlled to be normally switched on and off within a control range.

In one embodiment, the LED dot matrix circuit 30 further includes a first capacitor and a second capacitor connected in parallel, one end of the first capacitor and the second capacitor connected in parallel is connected to the power supply, and the other end is grounded for power supply filtering.

Please refer to fig. 5, which is a circuit diagram of an LED dot matrix module according to an embodiment of the present application; the operation process of the LED dot matrix module of the present application for lighting the LED lamps row by row is described in detail below by taking, as an example, the decoder 203 with the model 74HC238, the shift register 404 with the model 74HC595, the LED dot matrix 30 with 5 rows of LED lamps and 5 columns of LED lamps, the multi-row first control switch 204 composed of 5 NPN transistors, and the multi-row second control switch 405 composed of 5 PNP transistors.

In order to make the operation of the LED dot matrix module more clear, please refer to fig. 5 to specifically describe the connection relationship of the components.

As shown in FIG. 5, the three address driving signal inputs A0, A1, and A2 of the decoder 203 are connected to a three first driving signal output of the controller (not shown) to receive the address driving signals input by the controller; five signal output ends Y0, Y1, Y3, Y2 and Y6 of the decoder 203 are connected to bases of the first triodes Q6, Q7, Q8, Q9 and Q10 through first current-limiting resistors R6, R7, R8, R9 and R10, respectively; the emitters of the first triodes Q6, Q7, Q8, Q9 and Q10 are all grounded; the collector of the first triode Q6 is connected with the first connection end from the LED1 to the LED5 in the first row of LED lamps; the collector of the first triode Q7 is connected with the first connection end from the LED6 to the LED10 in the second row of LED lamps; the collector electrode of the first triode Q8 is connected with the first connection end from the LED11 to the LED15 in the third row of LED lamps; the collector electrode of the first triode Q9 is connected with the first connection end from the LED16 to the LED20 in the fourth row of LED lamps; the collector of the first triode Q10 is connected with the first connection end of the LED21 to the LED25 in the fifth row of LED lamps.

The clock signal input terminal SCLK and the data signal input terminal SER of the shift register 404 are connected to the clock signal output terminal and the data signal output terminal of the controller, respectively, and receive the timing driving signal input by the controller through the clock signal output terminal. Five signal output terminals Q0, Q1, Q2, Q3 and Q4 of the shift register 404 are respectively connected with bases of second triodes Q1, Q2, Q3, Q4 and Q5 through second current-limiting resistors R1, R2, R3, R4 and R5; the emitters of the second diodes Q1, Q2, Q3, Q4 and Q5 are all connected to the power source VCC. The collector of the second triode Q1 is connected with the second connection ends of the LED1, the LED6, the LED11, the LED16 and the LED21 in the first column of LED lamps; the collector of the second triode Q2 is connected with the second connecting ends of the LED2, the LED7, the LED12, the LED17 and the LED22 in the second row of LED lamps; the collector of the second triode Q3 is connected with the second connection end of the LED3, the LED8, the LED13, the LED18 and the LED23 in the third LED lamp column; the collector of the second triode Q4 is connected with the second connection ends of the LED4, the LED9, the LED14, the LED19 and the LED24 in the fourth column of LED lamps; the collector of the second triode Q5 is connected to the second connection terminals of the LED5, the LED10, the LED15, the LED20, and the LED25 in the fifth row of LED lamps, and the clear signal input terminal RCLK of the shift register 404 is connected to one signal output terminal Y4 of the decoder 203.

The LED dot matrix circuit 30 further includes a first capacitor C1 and a second capacitor C2 connected in parallel, one end of each of the first capacitor C1 and the second capacitor C2 connected in parallel is connected to the power VCC, and the other end of each of the first capacitor C1 and the second capacitor C2 connected in parallel is connected to the ground for power filtering.

The operation process of the LED dot matrix module of the present application is specifically described as follows:

when the line LED lamps of the LED dot matrix circuit 30 are switched and lighted line by line, the controller outputs timing driving signals to the clock signal input terminal SCLK and the data signal input terminal SER of the shift register 404 through the clock signal output terminal and the data signal output terminal, so that the five signal output terminals Q0, Q1, Q2, Q3 and Q4 of the shift register 404 all output high levels, and further the second triodes Q1, Q2, Q3, Q4 and Q5 are turned on. The second connecting end of each row of LED lamps is connected with a power supply VCC, and further the second connecting end of each row of LED lamps is high level; meanwhile, the three-way first driving signal output end of the controller sequentially outputs driving address signals of 000, 001, 011, 010, 110 and 100, the five-way address driving signal input ends Y0, Y1, Y3, Y2, Y6 and Y4 of the decoder 203 sequentially output high level, so that the first triodes Q6, Q7, Q8, Q9 and Q10 are sequentially turned on, the first connection ends of the LEDs 1 to the LED5 in the first row of LED lamps are grounded, the first connection ends of the LEDs 5 to the LED5 in the second row of LED lamps are grounded, the first connection ends of the LEDs 5 to the LED5 in the third row of LED lamps are grounded, the first connection ends of the LEDs 5 to the LED5 in the fourth row of LED lamps are grounded, the LEDs 5 to the LED5 in the fifth row of LED lamps are grounded, the LEDs 5 to the LEDs 5 in the first row of LED lamps are sequentially turned on, the LEDs 5 to the LEDs 5 in the second row of the fourth row of LED lamps are reset, and the LEDs 5 in the fourth row of LED5 are reset, the LEDs 5 to the LEDs 5 of the LEDs 5 are sequentially shifted to the LED5 of the LEDs 5 of the first row of the LEDs 5 of the second row of the LEDs 5 of the LEDs are reset register 5, therefore, when the lines are switched, only one address bit of the driving address signal of the adjacent switching line is changed, and the problem of LED lamp flickering is prevented.

When some LED lamps of the LED dot matrix circuit 30 are turned on, for example, when the LEDs 1, the LEDs 3, and the LEDs 5 in the first row of LED lamps need to be turned on, the three first driving signal output ports of the controller output 000, so that the fifth address driving signal output port Y0 of the decoder 203 outputs a high level, so that the first triode Q6 is turned on, and the first ends of the first row of LED lamps are all grounded, thereby controlling the turning on of the first row of LED lamps; meanwhile, the controller inputs data bits of 1, 0, 1, 0 and 1 to the shift register 404 in sequence through the data signal output end at the rising edge of the clock signal, and the controller inputs the clock signal to the shift register 404 through the clock signal output end, so that the shift register 404 collects the data bits at the rising edge of the clock signal according to the clock signal, and outputs a timing driving signal of 10101 at five signal output ends Q0, Q1, Q2, Q3 and Q4 of the shift register 404, so that the second triodes Q1, Q2, Q3, Q4 and Q5 are in a state of conduction, non-conduction, non-conduction and conduction in sequence, so that the second ends of the LEDs 1, 3 and the LEDs 5 of the first row of LED lamps are connected to the power supply VCC, and further the LEDs 1, LEDs 3 and LEDs 5 of the first row of LED lamps are lighted.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.

The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. An LED lattice module, comprising: the LED array circuit comprises a controller, a decoding circuit and an LED dot matrix circuit;

the LED dot matrix circuit comprises a plurality of rows of LED lamps; each row of LED lamps is correspondingly connected with one path of first signal output end of the decoding circuit, and the first signal output ends connected with each row of LED lamps correspond to different address driving signals one by one; the decoding circuit receives the address driving signal, and the decoding circuit controls the LED lamps to be lightened line by line through the address driving signal.

2. The LED dot matrix module of claim 1, wherein:

the address driving signals corresponding to the first signal output ends connected with the adjacent row LED lamps switched and lighted are only different by one bit;

the decoding circuit comprises a decoder and a plurality of rows of first control switches; the decoder comprises at least two signal input ends and a plurality of signal output ends; one path of signal input end of the decoder corresponds to one path of address driving signal input end of the decoding circuit, and the enabling end of each row of the first control switches is correspondingly connected with one path of signal output end of the decoder; the input end of each row of the first control switch is grounded; and the output end of each row of the first control switch is connected with the LED lamp of the corresponding row.

3. The LED dot matrix module of claim 2, wherein:

the LED dot matrix circuit also comprises a plurality of rows of LED lamps, and the LED lamps in the plurality of rows are mutually crossed to form an LED lamp array;

4. The LED dot matrix module of claim 3, wherein:

the sequential logic circuit also comprises a zero clearing signal input end; the zero clearing signal input end is connected with a first signal output end of one path of the decoding circuit; and after the row LED lamps are sequentially lightened, the decoding circuit outputs a zero clearing signal to the zero clearing signal input end.

5. The LED dot matrix module of claim 3, wherein:

the second group of driving signal output ends comprise a clock signal output end and a data signal output end; the time sequence driving signal input end of the time sequence logic circuit comprises a clock signal input end and a data signal input end; the clock signal output end is connected with the clock signal input end; the data signal output end is connected with the data signal input end.

6. The LED lattice module of claim 4 or 5, wherein:

the sequential logic circuit comprises a shift register and a plurality of columns of second control switches; the shift register comprises a signal input end and a plurality of paths of signal output ends; the signal input end of the shift register corresponds to the time sequence driving signal input end of the time sequence logic circuit; the enabling end of each row of the second control switches is correspondingly connected with one signal output end of the shift register; the input end of each column of the second control switch is grounded; the output end of each row of the second control switch corresponds to one path of second signal output end of the sequential logic circuit, and the output end of each row of the second control switch is connected with the corresponding row of the LED lamps.

7. The LED dot matrix module of claim 6, wherein:

the second control switch comprises a second triode and a second current-limiting resistor; the base electrode of the second triode is connected with one signal output end of the shift register through the second current limiting resistor, the emitting electrode of the second triode is connected with the power supply, and the collecting electrode of the second triode is connected with the LED lamps in the corresponding row.

8. The LED dot matrix module of claim 2, wherein:

the first control switch comprises a first triode and a first current-limiting resistor; the base electrode of the first triode is connected with one signal output end of the decoder through the first current limiting resistor, the emitting electrode of the first triode is grounded, and the collecting electrode of the first triode is connected with the LED lamp in the corresponding row.

9. The LED dot matrix module according to claim 7 or 8, wherein:

the LED lattice circuit further comprises a first capacitor and a second capacitor which are connected in parallel, one end of the first capacitor and one end of the second capacitor which are connected in parallel are both connected to a power supply, and the other end of the first capacitor and the other end of the second capacitor which are connected in parallel are both grounded.

10. The LED dot matrix module of claim 8, wherein:

the first triode is an NPN triode.