CN217159719U - Third-order intercept point test circuit - Google Patents
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Abstract
The utility model relates to a third-order intercept point test circuit in radio frequency communication technical field, including first signal source route, second signal source route, power synthesis circuit and signal analysis route, first signal source route is f according to the carrier signal output frequency of input 1 The first path of signal of (1); the second signal source path outputs a frequency f according to the input carrier signal 2 The second path of signals; the first path of signal and the second path of signal are two paths of single-tone signals with the same amplitude and similar output frequency, and the first path of signal and the second path of signal output frequency f 1 And f 2 Within the range of the operating frequency of the device under test; the power synthesis circuit is used for synthesizing the first path of signal and the second path of signal into one pathThe synthesized signal is sent to the input end of the tested device through the output port; the signal analysis path receives an output signal generated by an output end of the tested device and converts the output signal into a signal for calculating a third-order intercept point. The test circuit provides hardware circuit support for rapidly testing the third-order intercept point of the tested device.
Description
Technical Field
The utility model relates to a radio frequency communication technical field, in particular to third-order intercept test circuit.
Background
In a radio frequency or microwave multi-carrier communication system, a Third-order Intercept Point IP3(Third-order Intercept Point) is an important index for measuring linearity or distortion. For analog microwave communication, crosstalk of adjacent channels can be generated, and for digital microwave communication, the frequency spectrum utilization rate of a system can be reduced, and the error rate can be changed.
IP3 is typically tested with two input tones, which are radio or microwave frequency signals with two frequencies that are relatively close together. Patent "a method and an apparatus for testing a power amplifier and a computer readable storage medium" (publication number CN113267718A) discloses a method for calculating a third-order intermodulation coefficient, comprising the steps of: acquiring a test signal based on an input-output characteristic function of a power amplifier to be tested, wherein the test signal comprises a dual-tone signal; obtaining a test output signal of the test signal after passing through the power amplifier to be tested according to the input and output characteristic function; carrying out amplitude-phase distortion fitting on the test output signal to obtain a nonlinear output signal of the power amplifier to be tested based on the amplitude-phase distortion; obtaining a theoretical third-order intermodulation coefficient of the power amplifier to be tested according to the nonlinear output signal; inputting the test signal into the power amplifier to be tested to obtain a practical third-order intermodulation coefficient of the power amplifier to be tested; acquiring the signal gain of the power amplifier to be tested; obtaining a theoretical horizontal and vertical coordinate of a third-order intermodulation interception point of the power amplifier to be tested according to the theoretical third-order intermodulation coefficient and the signal gain, and obtaining an actual horizontal and vertical coordinate of the third-order intermodulation interception point of the power amplifier to be tested according to the actual third-order intermodulation coefficient and the signal gain; and obtaining a nonlinear test result of the power amplifier to be tested according to the theoretical horizontal and vertical coordinates and the actual horizontal and vertical coordinates of the three-order intermodulation intercept points. The disclosure focuses on the improvement of the method, on one hand, a theoretical third-order intermodulation coefficient of the power amplifier to be tested is calculated, so that a theoretical abscissa and ordinate of a third-order intermodulation intercept point of the power amplifier to be tested are obtained by means of the theoretical third-order intermodulation coefficient and the signal gain of the power amplifier to be tested, on the other hand, a test signal is input into the power amplifier to be tested to obtain test data of the power amplifier to be tested, so that an actual third-order intermodulation coefficient is obtained, an actual abscissa and ordinate of the third-order intermodulation intercept point are obtained through the actual third-order intermodulation coefficient and the signal gain, and finally, a test result is obtained through comparison of the third-order intermodulation coefficient and the signal gain, so that the test accuracy is greatly improved.
However, as the closest prior art, this scheme does not disclose a circuit for inputting a two-tone signal to a device under test, nor a circuit for generating a test output signal for the third-order intermodulation intercept point calculation, and therefore, its implementation scheme is not known from a hardware circuit.
SUMMERY OF THE UTILITY MODEL
The utility model discloses to above-mentioned problem, a third-order intercept test circuit is given, can test the third-order intercept value of device under test fast.
In order to achieve the above purpose, the invention provides the following technical scheme:
a third-order intercept point test circuit comprises a first signal source path, a second signal source path, a power synthesis circuit and a signal analysis path,
the first signal source path is used for outputting a frequency f according to an input carrier signal 1 The first path of signal of (1);
the second signal source path is used for outputting a frequency f according to the input carrier signal 2 The second path of signals; the first path of signal and the second path of signal are two paths of single-tone signals with the same amplitude and similar output frequency, and the first path of signal and the second path of signal output frequency are frequency f 1 And f 2 Within the range of the operating frequency of the device under test;
the power synthesis circuit is used for synthesizing the first path of signal and the second path of signal into a path of signal and sending the synthesized path of signal to the input end of the tested device through the output port;
the signal analysis path receives an output signal generated at an output of the device under test and converts the output signal to a signal for third order intercept calculation.
As the preferred scheme of the utility model, the first signal source path is the same as the structure of the second signal source path, and comprises an FPGA control circuit, an orthogonal digital up-conversion circuit, an electrically-controlled attenuator circuit, a first mixing circuit, a first local oscillator circuit, a second mixing circuit and a second local oscillator circuit;
the FPGA control circuit is used for outputting a carrier generation control signal to the orthogonal digital up-conversion circuit; the orthogonal digital up-conversion circuit generates a control signal according to the carrier wave and outputs a carrier wave signal with fixed frequency to the electrically-adjusted attenuator circuit; the electrically-tuned attenuator circuit is used for amplitude conditioning of the carrier signal, then the carrier signal is filtered and attenuated and then sent to the first mixing circuit, and the carrier signal is mixed with a first local oscillation signal generated by the first local oscillation circuit to obtain a fixed first intermediate frequency signal; the first intermediate frequency signal is sent to a second frequency mixing circuit, and is mixed with a second local oscillation signal generated by a second local oscillation circuit to obtain a broadband radio frequency output signal; the broadband radio frequency output signal is subjected to amplitude conditioning and then outputs a radio frequency signal to the power synthesis circuit.
As the preferred scheme of the utility model, the attenuator is transferred to electricity that electric regulation attenuator circuit comprises PIN diode, resistance and electric capacity.
As the preferred scheme of the utility model, obtain radio frequency signal is the radio frequency output signal of broadband obtains through the conditioning of the controllable digital attenuator of two-stage.
As a preferable proposal of the utility model, the signal analysis path comprises a first frequency mixing circuit, a first local oscillator circuit, a second frequency mixing circuit, a second local oscillator circuit, an AD converter and an FPGA digital down-conversion circuit,
after input and conditioning, the output signal of the tested device is sent to a first frequency mixing circuit to be mixed with a first local oscillation signal generated by a first local oscillation circuit to obtain a fixed second intermediate frequency signal; and the second intermediate frequency signal is amplified, subjected to band-pass filtering and attenuation processing and then sent to a second frequency mixing circuit, is mixed with a second local oscillator signal generated by a second local oscillator circuit to obtain a third intermediate frequency signal which can be directly subjected to digital signal processing, and the third intermediate frequency signal is subjected to sampling of an AD converter and conversion of an FPGA digital down-conversion circuit to obtain a signal for third-order intercept point calculation.
As the utility model discloses a preferred scheme, local oscillator circuit produces local oscillator signal through phase-locked loop circuit.
As a preferred proposal of the utility model, the phase-locked loop circuit comprises a phase-locked loop chip HMC830, a loop filter and a filtering amplitude conditioning circuit,
the phase-locked loop chip is used for receiving a reference signal and a VTUNE signal output by the loop filter, outputting a CP signal to the loop filter, and outputting an initial local oscillator signal, wherein the initial local oscillator signal outputs the local oscillator signal to the frequency mixing circuit after being subjected to high-pass filtering, attenuation, amplification and low-pass filtering of the filtering amplitude conditioning circuit.
As the utility model discloses a preferred scheme, the reference signal of phase-locked loop circuit input comes from OCXO crystal oscillator, the reference output signal that OCXO crystal oscillator produced divides the ware into two way signals through the merit, respectively through enlarging, decay and filtering after, send the reference signal of phase-locked loop circuit as phase-locked loop chip HMC 830.
As a preferred aspect of the present invention, the loop filter is a passive loop filter.
As a preferable proposal of the utility model, the passive loop filter comprises a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor,
the first resistor and the first branch are connected between the first end of the second resistor and the ground in parallel, the third resistor is connected with the second resistor in series, the third capacitor is connected between the first end of the third resistor and the ground in parallel, and the fourth capacitor is connected between the second end of the third resistor and the ground in parallel.
Compared with the prior art, the invention has the beneficial effects that:
the utility model provides an intercept point test circuit, the circuit includes first signal source route, second signal source route, power synthesis circuit and signal analysis route, first signal source route and second signal source route output two tunnel range the same, the single tone signal that the output frequency is close to, and the output frequency of two routes is in the device working frequency range under test; the power synthesis circuit is used for synthesizing the two paths of single-tone signals into one path of signal and inputting the synthesized one path of signal to the input end of the tested device; the signal analysis path receives an output signal generated by an output end of the tested device and converts the output signal into a signal for calculating a third-order intercept point. The test circuit provides hardware circuit support for rapidly testing the third-order intercept point of the tested device.
Description of the drawings:
FIG. 1 is a block diagram of the overall hardware of the third-order intercept point test circuit in embodiment 1;
fig. 2 is a schematic diagram of an output amplitude conditioning circuit of the first signal source path in embodiment 1;
FIG. 3 is a schematic diagram of first and second mixing circuits of a first signal source path in embodiment 1;
fig. 4 is a schematic diagram of a first local oscillation signal generating circuit used in first frequency mixing in a first signal source path in embodiment 1;
fig. 5 is a schematic diagram of a second local oscillator signal generating circuit used for second frequency mixing in the first signal source path in embodiment 1;
fig. 6 is a schematic diagram of a first mixing circuit and a second mixing circuit of a second signal source path and a power combining circuit in embodiment 1;
fig. 7 is a schematic diagram of a first local oscillator signal generating circuit used for first frequency mixing in a second signal source path in embodiment 1;
fig. 8 is a schematic diagram of a second local oscillator signal generating circuit used for second mixing in a second signal source path in embodiment 1;
FIG. 9 is a schematic diagram of an input amplitude conditioning circuit of the signal analysis path in embodiment 1;
fig. 10 is a schematic diagram of first and second mixing circuits of a signal analysis path in embodiment 1;
fig. 11 is a schematic diagram of a first local oscillation signal generating circuit used for first frequency mixing in a signal analysis path in embodiment 1;
fig. 12 is a schematic diagram of a second local oscillation signal generating circuit used for second frequency mixing in the signal analysis path in embodiment 1;
FIG. 13 is a schematic diagram of a phase-locked loop circuit in embodiment 1;
fig. 14 is a schematic diagram of a reference signal of a specific phase-locked loop circuit in embodiment 1.
Detailed Description
The present invention will be described in further detail with reference to test examples and specific embodiments. It should be understood that the scope of the above-described subject matter is not limited to the following examples, and any techniques implemented based on the disclosure of the present invention are within the scope of the present invention.
Example 1
A third-order intercept point test circuit is shown in a figure 1, and comprises a first signal source path, a second signal source path, a power synthesis circuit and a signal analysis path. The first signal source channel comprises an FPGA control circuit, an orthogonal digital up-conversion circuit, a first frequency mixing circuit, a first local oscillator circuit, a second frequency mixing circuit and a second local oscillator circuit; the second signal source channel comprises an FPGA control circuit, an orthogonal digital up-conversion circuit, a first frequency mixing circuit, a first local oscillator circuit, a second frequency mixing circuit and a second local oscillator circuit; the signal analysis channel comprises a first frequency mixing circuit, a first local oscillator circuit, a second frequency mixing circuit, a second local oscillator circuit, an AD converter and an FPGA digital down converter circuit.
The main function of the test circuit of the third-order intercept is to obtain the signal of the third-order intercept value of the tested device. A first signal source path part and a second signal source path part in the circuit generate two single-tone signals with the same amplitude and similar frequency, the single-tone signals are output to a Device Under Test (DUT) after passing through a power synthesis circuit, the output value of the Device Under Test (DUT) is sent to a signal analysis path part in the circuit, the signal analysis path part outputs signals for three-order intercept point calculation, the output power value of the single-tone signals and the power value of three-order intermodulation are measured by the signals for the three-order intercept point calculation through spectrum analysis, and finally, the three-order intercept point value of the Device Under Test (DUT) is calculated in a controller unit.
1. First signal source path
The FPGA controls the orthogonal digital up-converter to generate a carrier signal with fixed frequency, the signal passes through an electrically-controlled attenuator consisting of a PIN diode and a resistance capacitor to perform amplitude conditioning on the carrier signal, then the carrier signal is transmitted into a first frequency mixing circuit after being filtered and attenuated, and is mixed with a local oscillation signal generated by the first local oscillation circuit to obtain a fixed high-medium frequency signal. The intermediate frequency signal is amplified by an amplifier, filtered by a band-pass filter, attenuated by an attenuator and the like, then sent to a second mixer, mixed with a second local oscillator signal generated by a second local oscillator circuit to obtain a broadband radio frequency output signal, and finally conditioned by a two-stage controllable digital attenuator to obtain a required radio frequency signal as an output. Suppose the first signal has a frequency f 1 Amplitude of P in 。
A schematic diagram of an output amplitude conditioning circuit of the first signal source path is shown in fig. 2, and the output amplitude conditioning circuit is a conditioning path of an output signal after second frequency mixing; a schematic diagram of first and second mixing circuits of the first signal source path is shown in fig. 3; a schematic diagram of a first local oscillator signal generating circuit used for first frequency mixing in a first signal source path is shown in fig. 4; a schematic diagram of a second local oscillator signal generating circuit used for the second mixing in the first signal source path is shown in fig. 5.
2. Second signal source path
The generation principle of the second signal source is similar to that of the first signal source, and only the frequencies of the two paths of signals are different. By amplitude calibration, the amplitudes of the two signals can be the same. Suppose that the frequency of the second path signal is f 2 Amplitude of P in 。
A schematic diagram of the first and second mixing circuits and the power combining circuit of the second signal source path is shown in fig. 6; a schematic diagram of a first local oscillator signal generating circuit used for first frequency mixing in a second signal source path is shown in fig. 7; a schematic diagram of a second local oscillator signal generating circuit used for the second mixing in the second signal source path is shown in fig. 8.
3. Power combined output
Two paths of carrier signals with approximate frequencies and the same amplitude, which are generated by the two signal source paths, are synthesized into a path of signal by a power synthesis circuit, the path of signal is sent to the input end of a tested Device (DUT) through an output port, and the output signal of the tested Device (DUT) enters a signal analysis path through the input port of the circuit for signal analysis. The detailed schematic diagram of the power synthesis circuit is shown in fig. 6, and in fig. 6, two paths of carrier signals with similar frequencies and same amplitudes generated by two signal source paths are realized by a power synthesis chip with the model of ADP-2-1W +.
4. Signal analysis path
An output signal of a Device Under Test (DUT) enters a signal analysis channel through an input port, and the signal is input and conditioned and then sent to a first frequency mixing circuit to be mixed with a first local oscillation signal generated by a first local oscillation circuit to obtain a fixed intermediate frequency signal; the intermediate frequency signal is amplified by an amplifier, is subjected to signal processing such as filtering by a radio frequency band-pass filter, attenuation by an attenuator and the like, and then is sent to a second-stage mixing circuit to be mixed with a fixed second local oscillator signal generated by a second local oscillator circuit to obtain an intermediate frequency signal which can be directly subjected to digital signal processing.
Fig. 9 shows a schematic diagram of an input amplitude conditioning circuit of a signal analysis path, where the input amplitude conditioning circuit performs amplitude conditioning on a signal input to the signal analysis path, and is an amplitude conditioning circuit before first frequency mixing; a schematic diagram of the first and second mixing circuits of the signal analysis path is shown in fig. 10; a schematic diagram of a first local oscillator signal generating circuit used for first frequency mixing in a signal analysis path is shown in fig. 11; a schematic diagram of a second local oscillator signal generating circuit used for the second mixing in the signal analysis path is shown in fig. 12.
The output power of the single-tone signal is P out The frequency of the third-order intermodulation component is (2 f) 1 -f 2 ) And (2 f) 2 -f 1 ) Due to f 1 And f 2 Has the same amplitude, and the output of the third-order intermodulation component is the same, which is P IMD3 . The formula for the third order intercept is shown below:
IIP3＝P in +1/2IMD 3
OIP3＝P out +1/2IMD 3 ＝IIP3+G
wherein
IMD 3 ＝P out -P IMD3
G＝P out -P in
In the above formula, IIP3 is the input third-order intercept point; OIP3 is the output third order intercept; p in Is the input power level of the single tone signal; p out Is the output power level of the single tone signal; g is the small signal gain of the Device Under Test (DUT); IMD 3 For third order intermodulation distortion, equal to the output power level P of the interference signal out Minus the third order intermodulation P IMD3 The value of the power level.
From the above equation, if the input/output power of the single tone signal and the level values of the third order intermodulation products are measured, the value of the input/output third order intercept point can be obtained.
5. Local oscillator generating circuit
The radio frequency part needs six local oscillation signals in total, each signal source path and the radio frequency analysis path need two local oscillation signals respectively, and a specific local oscillation generating circuit is shown in fig. 4, 5, 7, 8, 11 and 12. These local oscillator signals are generated by a phase locked loop circuit comprising a phase locked loop chip HMC830, which is schematically shown in fig. 13. A phase-locked loop circuit formed by the phase-locked loop chip HMC830 and the loop filter generates a local oscillation signal, and outputs a signal with a proper amplitude to a frequency mixer for frequency mixing after high-pass filtering, attenuation, amplification and low-pass filtering.
The reference signal of the phase-locked loop circuit is from an OCXO crystal oscillator, a reference output signal generated by the crystal oscillator is divided into two paths of signals through a power divider, and the two paths of signals are respectively amplified, attenuated and filtered and then sent to the phase-locked loop circuit to serve as the reference signal of the phase-locked loop chip HMC 830.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. A third-order intercept point test circuit is characterized in that the circuit comprises a first signal source path, a second signal source path, a power synthesis circuit and a signal analysis path,
the first signal source path is used for outputting a frequency f according to an input carrier signal 1 The first path of signal of (1);
the second signal source path is used for outputting a frequency f according to the input carrier signal 2 The second path of signals; the first path of signal and the second path of signal are two paths of single-tone signals with the same amplitude and similar output frequency, and the first path of signal and the second path of signal output frequency are frequency f 1 And f 2 Within the range of the operating frequency of the device under test;
the power synthesis circuit is used for synthesizing the first path of signal and the second path of signal into a path of signal and sending the synthesized path of signal to the input end of the tested device through the output port;
the signal analysis path receives an output signal generated at an output of the device under test and converts the output signal to a signal for third order intercept calculation.
2. The third-order intercept point test circuit of claim 1, wherein the first signal source path and the second signal source path have the same structure, and comprise an FPGA control circuit, a quadrature digital up-conversion circuit, an electrically tunable attenuator circuit, a first mixer circuit, a first local oscillator circuit, a second mixer circuit, and a second local oscillator circuit;
the FPGA control circuit is used for outputting a carrier generation control signal to the orthogonal digital up-conversion circuit; the orthogonal digital up-conversion circuit generates a control signal according to the carrier wave and outputs a carrier wave signal with fixed frequency to the electrically-adjusted attenuator circuit; the electrically-tuned attenuator circuit is used for amplitude conditioning of the carrier signal, then the carrier signal is filtered and attenuated and then sent to the first mixing circuit, and the carrier signal is mixed with a first local oscillation signal generated by the first local oscillation circuit to obtain a fixed first intermediate frequency signal; the first intermediate frequency signal is sent to a second frequency mixing circuit, and is mixed with a second local oscillation signal generated by a second local oscillation circuit to obtain a broadband radio frequency output signal; and the broadband radio frequency output signal is subjected to amplitude conditioning and then outputs a radio frequency signal to the power synthesis circuit.
3. A third order intercept point test circuit according to claim 2 wherein said electrically tunable attenuator circuit is an electrically tunable attenuator consisting of a PIN diode, a resistor and a capacitor.
4. A third order intercept point test circuit according to claim 2 wherein said rf signal is derived by conditioning said wideband rf output signal with a two-stage controllable digital attenuator.
5. The third order intercept point test circuit of claim 2 wherein the signal analysis path comprises a first mixer circuit, a first local oscillator circuit, a second mixer circuit, a second local oscillator circuit, an AD converter and an FPGA digital down-conversion circuit;
after input and conditioning, the output signal of the tested device is sent to a first frequency mixing circuit to be mixed with a first local oscillation signal generated by a first local oscillation circuit to obtain a fixed second intermediate frequency signal; and the second intermediate frequency signal is amplified, subjected to band-pass filtering and attenuation processing and then sent to a second frequency mixing circuit, is mixed with a second local oscillator signal generated by a second local oscillator circuit to obtain a third intermediate frequency signal which can be directly subjected to digital signal processing, and the third intermediate frequency signal is subjected to sampling of an AD converter and conversion of an FPGA digital down-conversion circuit to obtain a signal for third-order intercept point calculation.
6. A third order intercept point test circuit according to any of claims 2 to 5 wherein the local oscillator circuit generates the local oscillator signal by means of a phase locked loop circuit.
7. The third order intercept point test circuit of claim 6 wherein the phase locked loop circuit includes a phase locked loop chip HMC830, a loop filter and a filtered amplitude conditioning circuit,
the phase-locked loop chip is used for receiving a reference signal and a VTUNE signal output by the loop filter, outputting a CP signal to the loop filter, and outputting an initial local oscillator signal, wherein the initial local oscillator signal outputs the local oscillator signal to the frequency mixing circuit after being subjected to high-pass filtering, attenuation, amplification and low-pass filtering of the filtering amplitude conditioning circuit.
8. A third order intercept point test circuit as claimed in claim 7, wherein the reference signal at the input of the PLL circuit is from an OCXO crystal oscillator, and the reference output signal generated by the OCXO crystal oscillator is divided into two signals by a power divider, and the two signals are amplified, attenuated and filtered respectively and then sent to the PLL circuit as the reference signal of the PLL chip HMC 830.
9. The third order intercept point test circuit of claim 7 wherein the loop filter is a passive loop filter.
10. The third order intercept point test circuit of claim 9, wherein the passive loop filter comprises a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor,
the first resistor and the first branch are connected between the first end of the second resistor and the ground in parallel, the third resistor is connected with the second resistor in series, the third capacitor is connected between the first end of the third resistor and the ground in parallel, and the fourth capacitor is connected between the second end of the third resistor and the ground in parallel.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024125493A1 (en) * | 2022-12-16 | 2024-06-20 | 深圳飞骧科技股份有限公司 | Intermodulation measurement device |
| WO2024125484A1 (en) * | 2022-12-16 | 2024-06-20 | 深圳飞骧科技股份有限公司 | Input third-order intercept point test method, related system, and storage medium |
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2022
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024125493A1 (en) * | 2022-12-16 | 2024-06-20 | 深圳飞骧科技股份有限公司 | Intermodulation measurement device |
| WO2024125484A1 (en) * | 2022-12-16 | 2024-06-20 | 深圳飞骧科技股份有限公司 | Input third-order intercept point test method, related system, and storage medium |
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