CN217133983U - Internal compensation circuit of pixel structure - Google Patents
Internal compensation circuit of pixel structure Download PDFInfo
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- CN217133983U CN217133983U CN202220809216.2U CN202220809216U CN217133983U CN 217133983 U CN217133983 U CN 217133983U CN 202220809216 U CN202220809216 U CN 202220809216U CN 217133983 U CN217133983 U CN 217133983U
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Abstract
The utility model discloses an internal compensation circuit of a pixel structure, wherein each pixel unit of the pixel structure comprises a first switch tube and a plurality of sub-pixels; each sub-pixel comprises a 4T2C driving framework, one end of a first transistor is connected with Data, the control end of the first transistor is connected with Scan1, and the other end of the first transistor is connected with one end of a first capacitor and the control end of a second transistor; one end of the second transistor is connected with one end of the third transistor, the control end of the third transistor is connected with the EM, and the other end of the third transistor is connected with the OVDD; the other end of the second transistor is connected with the light emitting diode, and the other end of the first capacitor is connected with one end of the fourth transistor, one end of the second capacitor and the light emitting diode; the other end of the fourth transistor is connected with Vsus, and the control end of the fourth transistor is connected with Reset; the other end of the second capacitor and the cathode of the light emitting diode are connected with the OVSS; the other end of the first transistor is connected with one end of a first switch tube, the other end of the first switch tube is connected with the Verf, and the control end of the first switch tube is connected with the Scan 2. The utility model discloses make panel luminance even.
Description
Technical Field
The utility model relates to a show technical field, especially relate to an internal compensation circuit of pixel structure.
Background
Since the Thin Film Transistor (TFT) in each pixel is slowly degraded with the increase of the operating time, the threshold voltage (V) is caused TH ) Changing while each TFT is making V TH The principle of operation of AMOLED is current driven, and the current is mainly driven by V TH Resulting in non-uniform brightness of the AMOLED panel, thereby eliminating V TH The influence of (b) is an important research topic. Meanwhile, the resolution of the panel is affected by the size of the pixel, and the size of the pixel is affected by the size of each sub-pixel, so reducing the number of TFTs in each sub-pixel is also an important research topic.
Disclosure of Invention
An object of the utility model is to provide an inside compensating circuit of pixel structure solves the inhomogeneous problem of luminance that VTH drift arouses.
The technical scheme adopted by the utility model is as follows:
an internal compensation circuit of a pixel structure, each pixel unit of the pixel structure comprises at least two adjacent sub-pixels; each sub-pixel comprises a 4T2C pixel drive circuit, the pixel unit comprises a first switch tube arranged at the periphery,
the 4T2C pixel driving circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, and an organic light emitting diode,
one end of the first transistor is connected with the Data signal Data, the control end of the first transistor is connected with the Scan signal Scan1, and the other end of the first transistor is respectively connected with one end of the first capacitor and the control end of the second transistor;
one end of the second transistor is connected with one end of the third transistor, the control end of the third transistor is connected with the EM signal, and the other end of the third transistor is connected with the power supply voltage OVDD; the other end of the second transistor is connected with the anode of the organic light-emitting diode,
the other end of the first capacitor is respectively connected with one end of the fourth transistor, one end of the second capacitor and the anode of the organic light-emitting diode;
the other end of the fourth transistor is connected with a high voltage Vsus, and the control end of the fourth transistor is connected with a Reset signal Reset;
the other end of the second capacitor and the cathode of the organic light emitting diode are connected to a common grounding voltage OVSS;
the other end of the first transistor of each sub-pixel is connected to one end of a first switching tube, the other end of the first switching tube is connected to the reference voltage Verf, and the control end of the first switching tube is connected to the Scan signal Scan 2.
Further, the first switch tube is a transistor;
further, the first transistor, the second transistor, the third transistor, the fourth transistor and the first switch transistor are all Thin Film Transistors (TFTs).
Further, the Scan signal Scan1 and the Scan signal Scan2 are generated by GPIO circuits
Further, the compensation circuit includes an IC chip, and the IC chip generates the Scan signal Scan1 and the Scan signal Scan 2; the IC chip controls the on-off of the first transistor through a scanning signal Scan 1; the IC chip controls the on-off of the first switch tube through a scanning signal Scan 2.
A control method of an internal compensation circuit of a pixel structure comprises the following steps:
a first phase reset phase: scan2 and Reset input high voltage, a second transistor, a fourth transistor and a first switch tube are opened, the fourth transistor inputs Vsus, and the first switch tube inputs Vref;
and a second stage compensation stage: scan2 and EM input high voltage, Reset and Scan1 input low voltage, the second transistor, the third transistor and the first switch tube are opened, and the first switch tube inputs Vref, V G = Vref, the voltage at the other end of the second transistor is raised from Vsus to the second transistorT2 being closed when the body is in use, i.e. V S =Vref-V TH ；
The third stage data writing stage: scan1 input high voltage, Reset, Scan2 and EM input low voltage, first transistor and second transistor are turned on, first transistor input V DATA ，V G =V DATA ；
A fourth stage of luminescence: scan1, Scan2, and Reset input low voltage, Em input high voltage, second transistor and third transistor are turned on.
Further, the Scan signal Scan1 and the Scan signal Scan2 are generated by GPIO circuits.
Further, the Scan signal Scan1 and the Scan signal Scan2 are generated by the IC chip.
The utility model adopts the above technical scheme, compare in prior art and have following advantage: (1) can compensate VTH, make the picture brightness of every place of the panel uniform. (2) The current is not influenced by OVDD and OVSS, and the problem of uneven brightness caused by I-R drop is solved. (3) And only one TFT is used for controlling Vref in each row, so that the occupied area of each Pixel is saved, more pixels can be accommodated in a unit area, and the PPI can be improved.
Drawings
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments;
FIG. 1 is a schematic diagram of an internal compensation circuit of a pixel structure according to the present invention;
FIG. 2 is a schematic diagram of an internal compensation circuit of a pixel structure according to the present invention;
FIG. 3 is a schematic diagram of a Vref writing stage of a control method for an internal compensation circuit of a pixel structure according to the present invention;
FIG. 4 is a schematic diagram of a compensation stage of a control method of an internal compensation circuit of a pixel structure according to the present invention;
FIG. 5 is a schematic diagram of a data writing stage of a control method for an internal compensation circuit of a pixel structure according to the present invention;
fig. 6 is a schematic diagram of a light-emitting stage of a control method of an internal compensation circuit of a pixel structure according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
As shown in any of fig. 1 to 6, the present invention discloses an internal compensation circuit of a pixel structure, each pixel unit of the pixel structure comprises at least two adjacent sub-pixels; each sub-pixel comprises a 4T2C pixel drive circuit, the pixel unit comprises a first switch tube T5 arranged at the periphery,
the 4T2C pixel driving circuit comprises a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor C1, a second capacitor C2, an organic light emitting diode D1 and an IC chip,
one end of the first transistor T1 is connected to the Data signal Data, the control end of the first transistor T1 is connected to the Scan signal Scan1, and the other end of the first transistor T1 is connected to one end of the first capacitor C1 and the control end of the second transistor T2, respectively;
one end of the second transistor T2 is connected to one end of the third transistor T3, a control end of the third transistor T3 is connected to the EM signal, and the other end of the third transistor T3 is connected to the power supply voltage OVDD; the other end of the second transistor T2 is connected to the anode of the organic light emitting diode D1,
the other end of the first capacitor C1 is connected to one end of the fourth transistor T4, one end of the second capacitor C2 and the anode of the organic light emitting diode D1, respectively;
the other end of the fourth transistor T4 is connected to the high voltage Vsus, and the control end of the fourth transistor T4 is connected to the Reset signal Reset;
the other end of the second capacitor C2 and the cathode of the organic light emitting diode D1 are connected to a common ground voltage OVSS;
the other end of the first transistor T1 of each sub-pixel is connected to one end of a first switching tube T5, the other end of the first switching tube T5 is connected to a reference voltage Verf, the control end of the first switching tube T5 is connected to a Scan signal Scan2, and the IC chip controls the on-off of the first transistor T1 through a Scan signal Scan 1; the IC chip controls the on-off of the first switch tube T5 through a scanning signal Scan 2.
Further, the first switch transistor T5 is a transistor;
further, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the first switching transistor T5 are all Thin Film Transistors (TFTs).
The following is a detailed description of the specific working principle of the present invention:
as shown in FIG. 1, the internal compensation circuit structure, each single sub-Pixel is a 4T2C structure, wherein Vdata is written into data voltage of RGB, Scan1 controls writing of Vdata, EM controls writing of OVDD, Reset controls writing of Vsus, and Scan2 controls writing of direct current voltage Vref into the internal compensation circuit of each row of sub-pixels in AA area. Fig. 2 is a schematic diagram of the architecture.
As shown in FIG. 3, in the first stage of Reset phase, Scan2 and Reset inputs high voltage, T2, T4 and T5 are turned on, T4 inputs Vsus, T5 inputs Vref and V G =Vref， V S =Vsus。
As shown in FIG. 4, in the second stage compensation phase, Scan2 and EM input high voltage, Reset and Scan1 input low voltage, T2, T3 and T5 are opened, T5 input Vref, V G = Vref, S Point Voltage V S Rises from Vsus to Vref-V TH At time T2 closed, i.e. V S =Vref-V TH Thus, a V is supplemented TH 。
As shown in FIG. 5, in the third stage of data writing phase, Scan1 inputs high voltage, Reset, Scan2 and EM inputs low voltage, T1 and T2 are turned on, and T1 inputs V DATA ，V G =V DATA . The voltage at point S is coupled to Vref-V due to the coupling effect of the capacitor TH +[C1/(C1+C2)](V DATA -Vref), i.e. V S = Vref-V TH +[C1/(C1+C2)](V DATA -Vref)。
As shown in FIG. 6, in the fourth stage of light emission, Scan1, Scan2 and Reset input low voltage, Em input high voltage, T2 and T3 are turned on, and the voltage at the S point is from Vref to V due to OLED light emission TH +[C1/(C1+C2)](V DATA Vref) to V OLED + OVSS, i.e. V S =V OLED + OVSS due to capacitanceIs coupled to the voltage of point G DATA +V OLED +OVSS-{Vref-V TH +[C1/(C1+C2)](V DATA Vref) i.e. V) G =V DATA +V OLED +OVSS-{Vref-V TH +[C1/(C1+C2)](V DATA -Vref) } into the saturation region current formula I OLED =1/2μ n C OX W/L(V GS -V TH ) 2 To obtain I OLED =1/2μ n C OX (W/L){[1-C1/(C1+C2)](V DATA -Vref)} 2 (Note. mu.) n Is field effect mobility, C OX An insulating layer capacitor per unit area; W/L is TFT channel width to length). From the OLED luminous current formula, it can be understood that the OLED current is only equal to V DATA Vref is relevant, and other parameters are relatively fixed; and the compensation circuit has eliminated V TH Drift and I-R drop caused brightness non-uniformity problems.
The utility model adopts the above technical scheme, compare in prior art and have following advantage: (1) can compensate VTH, make the picture brightness of every place of the panel uniform. (2) The current is not influenced by OVDD and OVSS, and the problem of uneven brightness caused by I-R drop is solved. (3) And only one TFT is used for controlling Vref in each row, so that the occupied area of each Pixel is saved, more pixels can be accommodated in a unit area, and the PPI can be improved.
It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. The embodiments and features of the embodiments in the present application may be combined with each other without conflict. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the detailed description of the embodiments of the present application is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Claims (5)
1. An internal compensation circuit for a pixel structure, comprising: each pixel unit of the pixel structure comprises at least two adjacent sub-pixels; each sub-pixel comprises a 4T2C pixel drive circuit, the pixel unit comprises a first switch tube arranged at the periphery,
the 4T2C pixel driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor and an organic light emitting diode,
one end of the first transistor is connected with the Data signal Data, the control end of the first transistor is connected with the Scan signal Scan1, and the other end of the first transistor is respectively connected with one end of the first capacitor and the control end of the second transistor;
one end of the second transistor is connected with one end of the third transistor, the control end of the third transistor is connected with the EM signal, and the other end of the third transistor is connected with the power supply voltage OVDD; the other end of the second transistor is connected with the anode of the organic light-emitting diode,
the other end of the first capacitor is respectively connected with one end of the fourth transistor, one end of the second capacitor and the anode of the organic light-emitting diode;
the other end of the fourth transistor is connected with a high voltage Vsus, and the control end of the fourth transistor is connected with a Reset signal Reset;
the other end of the second capacitor and the cathode of the organic light emitting diode are connected to a common grounding voltage OVSS;
the other end of the first transistor of each sub-pixel is connected to one end of a first switching tube, the other end of the first switching tube is connected to the reference voltage Verf, and the control end of the first switching tube is connected to the Scan signal Scan 2.
2. The internal compensation circuit of a pixel structure of claim 1, wherein: the first switch tube is a transistor.
3. The internal compensation circuit of a pixel structure of claim 1, wherein: the first transistor, the second transistor, the third transistor, the fourth transistor and the first switch tube are all thin film transistors.
4. The internal compensation circuit of a pixel structure of claim 1, wherein: the Scan signal Scan1 and the Scan signal Scan2 are generated by GPIO circuits.
5. The internal compensation circuit of a pixel structure of claim 1, wherein: the compensation circuit comprises an IC chip, wherein the IC chip generates a scanning signal Scan1 and a scanning signal Scan 2; the IC chip controls the on-off of the first transistor through a scanning signal Scan 1; the IC chip controls the on-off of the first switch tube through a scanning signal Scan 2.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220809216.2U CN217133983U (en) | 2022-04-08 | 2022-04-08 | Internal compensation circuit of pixel structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220809216.2U CN217133983U (en) | 2022-04-08 | 2022-04-08 | Internal compensation circuit of pixel structure |
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| CN217133983U true CN217133983U (en) | 2022-08-05 |
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| CN202220809216.2U Active CN217133983U (en) | 2022-04-08 | 2022-04-08 | Internal compensation circuit of pixel structure |
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