CN217037179U - Communication circuit and communication board - Google Patents
Communication circuit and communication board Download PDFInfo
- Publication number
- CN217037179U CN217037179U CN202220249730.5U CN202220249730U CN217037179U CN 217037179 U CN217037179 U CN 217037179U CN 202220249730 U CN202220249730 U CN 202220249730U CN 217037179 U CN217037179 U CN 217037179U
- Authority
- CN
- China
- Prior art keywords
- resistor
- voltage
- circuit
- communication
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Dc Digital Transmission (AREA)
Abstract
The utility model discloses a communication circuit and a communication board, wherein the communication circuit comprises: the receiving circuit is arranged between the receiving pin and the communication bus, and the transmitting circuit is used for inverting a first input signal transmitted by the transmitting pin into a first bus voltage and outputting the first bus voltage to the communication bus; the receiving circuit is used for receiving a second bus voltage transmitted on the communication bus, inverting the second bus voltage into a second input signal and transmitting the second input signal to the receiving pin. The communication circuit provided by the utility model is connected with the chip of the control board through the group of sending pins and receiving pins, so that more sending/receiving ports are prevented from being arranged on the control board, meanwhile, the communication wiring harness is reduced, and all data can be transmitted on one communication line by only one communication bus.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a communication circuit and a communication board.
Background
The Universal Asynchronous Receiver/Transmitter (UART) protocol is a common communication protocol for various household appliances.
Referring to fig. 1, in the prior art, slave control boards (also called function boards) in a UART-based household appliance all occupy a set of TXD (transmit)/RXD (receive) ports of a master control board, and each slave control board needs to be wired with 2 communication lines to be connected with the TXD/RXD ports of the master control board respectively. Therefore, in the household appliances with more function boards, more TXD/RXD ports need to be arranged on the main control board, and more communication lines need to be arranged, which is high in cost and difficult in later maintenance.
SUMMERY OF THE UTILITY MODEL
The utility model mainly aims to provide a communication circuit and a communication board, and aims to solve the technical problems that more sending/receiving ports are required to be arranged on a main control board and more communication lines are required to be arranged in the existing household appliance.
To achieve the above object, the present invention provides a communication circuit, including:
the transmitting circuit is arranged between a transmitting pin and a communication bus, and is used for inverting a first input signal transmitted by the transmitting pin into a first bus voltage and outputting the first bus voltage to the communication bus; and
and the receiving circuit is arranged between the receiving pin and the communication bus, and is used for receiving the second bus voltage transmitted on the communication bus, inverting the second bus voltage into a second input signal and transmitting the second input signal to the receiving pin.
Optionally, the sending circuit includes:
the first switch circuit is respectively connected with the sending pin and the second switch circuit and used for outputting a first voltage signal to the second switch circuit according to a first input signal transmitted by the sending pin; and
and the second switch circuit is respectively connected with the first switch circuit and the communication bus and is used for outputting a first bus voltage to the communication bus according to the first voltage signal.
Optionally, the first switching circuit includes:
the first voltage division module is respectively connected with the sending pin and the first switch module and is used for dividing the first input signal transmitted by the sending pin to obtain a divided input signal and outputting the divided input signal to the first switch module; and
and the first switch module is respectively connected with the first voltage division module and the second switch circuit and is used for outputting a first voltage signal to the second switch circuit according to the input signal after voltage division.
Optionally, the second switch circuit includes a second switch module;
the second switch module comprises a first resistor, a second resistor and a first triode, one end of the first resistor is connected with a first reference power supply, the other end of the first resistor is connected with a collector of the first triode, an emitter of the first triode is grounded, a base of the first triode is respectively connected with the first switch circuit and the second resistor, and the other end of the second resistor is grounded.
Optionally, the first switch module includes a third resistor, a fourth resistor, and a second triode;
one end of the third resistor is connected with a second reference power supply, the other end of the third resistor is connected with a collector of the second triode, an emitter of the second triode is grounded, a base of the second triode is respectively connected with a signal output end of the first voltage division module and the fourth resistor, and the other end of the fourth resistor is grounded.
Optionally, the first switch module includes fifth to seventh resistors and a first optocoupler;
the first input end of the first optical coupler is connected with the fifth resistor and the first voltage division module respectively, the second input end of the first optical coupler is connected with the other end of the fifth resistor, the second input end of the first optical coupler is grounded, the first output end of the first optical coupler is connected with the sixth resistor and the seventh resistor respectively, the second output end of the first optical coupler is grounded, the other end of the sixth resistor is connected with a third reference power supply, and the other end of the seventh resistor is connected with the second switch circuit.
Optionally, the receiving circuit includes:
the third switch circuit is respectively connected with the communication bus and the fourth switch circuit and used for outputting a second voltage signal to the fourth switch circuit according to a second bus voltage transmitted on the communication bus; and
and the fourth switch circuit is respectively connected with the receiving pin and the third switch circuit and is used for outputting a second input signal to the receiving pin according to the second voltage signal.
Optionally, the third switch circuit includes:
the second voltage division module is respectively connected with the communication bus and the third switch module, and is used for dividing a second bus voltage transmitted on the communication bus to obtain a divided bus voltage and outputting the divided bus voltage to the third switch module; and
and the third switch module is respectively connected with the second voltage division module and the fourth switch circuit and is used for outputting a second voltage signal to the fourth switch circuit according to the divided bus voltage.
Optionally, the third switch module includes: the eighth resistor, the ninth resistor and the third triode;
one end of the eighth resistor is connected with a fourth reference power supply, the other end of the eighth resistor is connected with a collector of the third triode, a base of the third triode is connected with the second voltage division module, an emitter of the third triode is grounded, one end of the ninth resistor is connected with the base of the third triode, and the other end of the ninth resistor is connected with the emitter of the third triode.
Optionally, the fourth switching circuit includes a fourth switching module;
the fourth switching module comprises a tenth resistor, an eleventh resistor and a fourth triode;
one end of the tenth resistor is connected with a fifth reference power supply, the other end of the tenth resistor is connected with a collector of the fourth triode, the collector of the fourth triode is connected with the receiving pin, a base of the fourth triode is connected with the third switching circuit, an emitter of the fourth triode is grounded, one end of the eleventh resistor is connected with the base of the fourth triode, and the other end of the eleventh resistor is connected with the emitter of the fourth triode.
Optionally, the fourth switching circuit includes a fifth switching module;
the fifth switch module comprises a twelfth resistor, a thirteenth resistor, a second optical coupler and a first capacitor;
a first input end of the second optical coupler is connected with the third switch circuit, a second input end of the second optical coupler is grounded, a first output end of the second optical coupler is respectively connected with one end of the twelfth resistor, a first end of the first capacitor and the receiving pin, a second output end of the second optical coupler is grounded, the other end of the twelfth resistor is connected with a sixth reference power supply, and a second end of the first capacitor is connected with a second output end of the second optical coupler; one end of the thirteenth resistor is connected with the first input end of the second optical coupler, and the other end of the thirteenth resistor is connected with the second input end of the second optical coupler.
Optionally, the receiving circuit includes:
and the voltage division circuit is used for receiving a second bus voltage transmitted on the communication bus, dividing the second bus voltage to obtain a second input signal, and transmitting the second input signal to the receiving pin.
Optionally, the voltage divider circuit includes:
the third voltage division module is respectively connected with the communication bus and the fourth voltage division module, and is used for receiving a second bus voltage transmitted on the communication bus, dividing the second bus voltage and outputting the divided second bus voltage to the fourth voltage division module; and
and the fourth voltage division module is respectively connected with the third voltage division module and the receiving pin, and is used for inverting the voltage transmitted by the third voltage division module into a second input signal and transmitting the second input signal to the receiving pin.
Optionally, the fourth voltage division module includes a fourteenth resistor and a second capacitor, a first end of the second capacitor is connected to the third voltage division module and the receiving pin, a second end of the second capacitor is grounded, one end of the fourteenth resistor is connected to the first end of the second capacitor, and the other end of the fourteenth resistor is connected to the second end of the second capacitor.
Optionally, the communication circuit further includes:
and the filtering protection circuit is connected with the communication bus and is used for filtering high-frequency interference signals on the communication bus.
Optionally, the filter protection circuit includes a third capacitor, two first diodes and a second diode connected in series, a first end of the third capacitor is connected to the communication bus, a second end of the third capacitor is grounded, an anode of the first diode is connected to a second end of the third capacitor, a cathode of the first diode is connected to an anode of the second diode, a cathode of the second diode is connected to the reference power supply, and a cathode of the first diode is connected to the communication bus.
To achieve the above object, the present invention also proposes a communication board including the communication circuit as described above.
The communication circuit provided by the utility model is connected with the chip of the control panel through the group of sending pins and receiving pins, so that more sending/receiving ports are prevented from being arranged on the control panel, meanwhile, the communication wiring harness is reduced, and all data can be transmitted on one communication line by only one communication bus.
Drawings
In order to more clearly illustrate the embodiments or technical solutions of the present invention, the drawings used in the embodiments or technical solutions of the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic diagram of a communication mode between a master control board and a slave control board in the prior art;
fig. 2 is a diagram of an application scenario of the communication circuit according to the present invention;
fig. 3 is a schematic structural diagram of a communication circuit according to a first embodiment of the present invention;
fig. 4 is a block diagram of a communication circuit according to an embodiment of the present invention;
FIG. 5 is a schematic circuit diagram of a communication circuit according to an embodiment of the present invention;
fig. 6 is another circuit schematic diagram of a communication circuit according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a communication circuit according to a second embodiment of the present invention;
FIG. 8 is a schematic circuit diagram of a communication circuit according to an embodiment of the present invention;
fig. 9 is a schematic circuit diagram of a communication circuit according to an embodiment of the present invention;
fig. 10 is another circuit schematic diagram of a communication circuit according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of a communication circuit according to a fourth embodiment of the present invention;
fig. 12 is another schematic circuit diagram of a communication circuit according to an embodiment of the present invention;
fig. 13 is another circuit schematic diagram of a communication circuit according to an embodiment of the present invention.
The reference numbers illustrate:
the implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the utility model and are not intended to limit the utility model.
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that all directional indicators (such as upper, lower, left, right, front and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should be considered to be absent and not within the protection scope of the present invention.
Referring to fig. 2, fig. 2 is a diagram of an application scenario of the communication circuit according to the present invention.
In practical applications, as shown in fig. 2, one of the above communication circuits may be disposed in each of the master control board and the slave control board, and control chips or processors are integrated in the master control board and the slave control board, and the control chips or processors are connected to the communication bus through the communication circuits. For the outside, each slave control board is connected with the master control board through a communication bus.
In this embodiment, different slave control boards are connected in parallel to one communication bus and connected to the master control board, which solves the problem that a plurality of communication lines need to be arranged on the master control board in the prior art. Meanwhile, all the slave control boards are connected with a group of RXD/TXD ports in the master control board through a communication bus, and the defect that more sending/receiving ports need to be arranged on the control board (master control board) in the prior art is overcome.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a communication circuit according to a first embodiment of the present invention.
As shown in fig. 3, in the present embodiment, the communication circuit includes a transmission circuit 10 and a reception circuit 20. Wherein the transmitting circuit 10 is arranged between a transmit pin (TXD) and a communication bus; the receiver circuit 20 is provided between a receiver pin (RXD) and the communication bus.
The transmitting circuit 10 inverts the first input signal transmitted by the transmitting pin into a first bus voltage and outputs the first bus voltage to the communication bus; the receiving circuit 20 receives the second bus voltage transmitted on the communication bus, inverts the second bus voltage into a second input signal, and transmits the second input signal to the receiving pin.
It should be noted that the communication circuit provided in this embodiment may be disposed in any multi-module communication scenario. The master control board or the slave control board can be a circuit board which is arranged on household appliances or other electrical appliances and contains a control chip or a processor. In the data processing and interaction process among the modules in the electrical equipment, the control panels have different roles according to different functions realized by the control panels, for example, the functions realized by the slave control panels such as the display module, the temperature changing module, the frequency conversion module and the WIFI module are different from the functions realized by the master control panel. Of course, in a scenario of one master multiple slaves or multiple master multiple slaves, there is no substantial difference in hardware properties between the master control board and the slave control boards. In some cases, the master control board may also serve as a slave control board, and the slave control board may also serve as a master control board.
The present embodiment is described by taking a master and multiple slaves as an example. In a specific implementation, the master control board is connected with a plurality of slave control boards through a communication bus, and different slave control boards are connected in parallel on the communication bus.
In a specific application, after the transmitting circuit 10 disposed on the master control board performs level inversion on an input signal to be transmitted from the master control board to the target slave control board, a high voltage meeting the currently used communication protocol specification of the communication bus is obtained (for example, the standard LIN communication protocol specification requires that the high voltage on the communication line is 12V), and then the high voltage is transmitted to the target slave control board through the communication bus.
The target slave control board receives the high voltage through a receiving circuit 20 '(not shown) in the communication circuit, then inverts the high voltage into a high voltage meeting the communication protocol specification requirement (for example, the high voltage required by the UART communication protocol specification is 5V) used by the target slave control board and responds, then inverts a response signal through a transmitting circuit 10' (not shown) (to obtain a bus voltage), and transmits the bus voltage to the master control board through the same communication bus, the receiving circuit 20 of the master control board receives the bus voltage transmitted on the communication bus, then inverts the bus voltage into an input signal and transmits the input signal to a receiving pin, and a master control chip in the master control board processes and responds to the input signal, thereby completing data interaction between the master control board and the slave control board.
This embodiment has avoided seting up more send/receive port on the control panel through above-mentioned communication circuit, has reduced the communication pencil simultaneously, only needs a communication bus can realize that all data are on a communication line.
Further, in order to simplify the circuit configuration of the above-described transmission circuit 10 and ensure stability of signal transmission. The transmitting circuit 10 of the present embodiment may further include a first switch circuit 101 and a second switch circuit 102.
Referring to fig. 4, fig. 4 is a block diagram of a communication circuit according to an embodiment of the present invention.
As shown in fig. 4, an input terminal of the first switch circuit 101 is connected to the transmit pin, an output terminal thereof is connected to the second switch circuit 102, and an output terminal of the second switch circuit 102 is connected to the communication bus.
The first switch circuit 101 is configured to output a first voltage signal to the second switch circuit 102 according to a first input signal transmitted by the transmit pin. The second switch circuit 102 is configured to output a first bus voltage to the communication bus according to the first voltage signal.
It should be noted that the first input signal can be sent from the master board or the slave board through the transmission pin TXD, the level of the first input signal will affect the output voltage of the first switch circuit 101 (i.e. the voltage value of the first voltage signal), and the output voltage will further affect the voltage output by the second switch circuit 102, so that the voltage finally output to the communication bus is different, for example (i.e. the first bus voltage) 0V or a preset high voltage (e.g. 12V).
In the present embodiment, the first switch circuit 101 and the second switch circuit 102 operate in cooperation with each other, and the purpose thereof is to invert a low voltage to a high voltage or invert a high voltage to a low voltage by a reference power supply connected to the first switch circuit. The specific turning manner needs to be set according to actual conditions, and this embodiment does not specifically limit this.
Further, to simplify the circuit structure of the first switch circuit 101 and reduce the circuit manufacturing cost. The first switch circuit 101 of this embodiment may include: a first voltage division module 11 and a first switch module 12. One end of the first voltage division module 11 is connected with the sending pin, and the other end of the first voltage division module is connected with the first switch module.
It should be noted that, the first voltage dividing module 11 divides the first input signal transmitted by the sending pin to obtain a divided input signal, and outputs the divided input signal. The first switch module 12 outputs a first voltage signal to the second switch circuit 102 according to the divided input signal.
The specific circuit configuration of the first voltage division module 11 is not limited in this embodiment, and may be a module including only one voltage division resistor, a module including any other circuit device that realizes a voltage division function, or a module obtained by combining a plurality of circuit devices that realize a voltage division function.
In this embodiment, the first switch module 12 may be a switch circuit including one or more switching devices (e.g., a switching transistor or an optocoupler OCEP) for performing the switching on and off functions. When receiving different level signals, the first switch module 12 turns off or turns on the circuit, thereby outputting voltage signals with different voltage values.
Further, in order to simplify the circuit configuration of the transmission circuit 10 and reduce the manufacturing cost of the entire circuit. In this embodiment, a switching transistor is preferably used as a switching device in the first switching circuit 101 and/or the second switching circuit 102.
In this embodiment, the first switch module 12 includes a third resistor R3, a fourth resistor R4, and a second transistor Q2, and the first voltage dividing module 11 includes a voltage dividing resistor R1'. The second switching circuit 102 includes a second switching module including a first resistor R1, a second resistor R2, and a first transistor Q1.
Referring to fig. 5, fig. 5 is a schematic circuit diagram of a communication circuit according to the present invention.
As shown in fig. 5, in the present embodiment, one end of the first resistor R1 is connected to the first reference power source V1, the other end of the first resistor R1 is connected to the collector of the first transistor Q1, the emitter of the first transistor Q1 is grounded to GND, and the base of the first transistor Q1 is connected to the first switch circuit 101. One end of the second resistor R2 is connected with the base of the first triode Q1, and the other end is grounded GND. One end of the third resistor R3 is connected to the second reference power source V2, the other end is connected to the collector of the second transistor Q2, the emitter of the second transistor Q2 is grounded GND, and the base of the second transistor Q2 is connected to the signal output end of the first voltage division module 11 (i.e., one end of the voltage division resistor R1') and the fourth resistor R4, respectively. The other end of the fourth resistor R4 is connected to the ground GND.
In this embodiment, the GND may be a ground terminal of the main board, and the first reference power supply V1 may be a power supply that provides a first reference voltage (e.g., 12V) to the main board. The second reference power supply V2 may be a power supply for providing a second reference voltage (e.g. 5V) to the main control board. In practical applications, the second reference voltage provided by the second reference power source V2 can be obtained by dividing the first reference voltage provided by the first reference power source V1.
In specific implementation, when the transmitting pin TXD outputs a high level, the base voltage of the second triode Q2 is higher than the emitter voltage, the second triode Q2 is turned on, the collector voltage of the second triode Q2 is close to zero, the base and emitter voltages of the first triode Q1 are both zero, and the first triode Q1 is turned off. If the resistance value of the first resistor R1 is far smaller than the resistance values of the other resistors connected in series with the first resistor R1, the bus voltage output to the communication bus is close to the first reference voltage provided by the first reference power supply V1, so that the operation of turning the high voltage (5V) conforming to the UART communication protocol into the high voltage (12V) conforming to the LIN communication protocol is completed, and the turned voltage is the high voltage conforming to the standard requirement of the communication protocol currently used by the communication bus (usually, the LIN communication protocol).
Furthermore, in order to improve the signal-to-noise ratio of the communication circuit in long-line data transmission, the reliability of data transmission is ensured. The switching devices in the first switching circuit 101 and/or the second switching circuit 102 may also be implemented by an optocoupler OCEP. Here, the switching device in the first switching circuit 101 is exemplified by the optocoupler OCEP.
Referring to fig. 6, fig. 6 is another schematic circuit diagram of a communication circuit according to an embodiment of the present invention.
As shown in fig. 6, in the present embodiment, the first switch module 12 may further include fifth to seventh resistors (R5 to R7) and a first photo coupler IC1, and the first voltage dividing module 12 includes a voltage dividing resistor R1'.
In this embodiment, the ground terminal of the second switch circuit 102 is E-GND (ground terminal of the slave panel). If the communication circuit is arranged in the master control board, the E-GND is the grounding end of the slave control board, and the GND is the grounding end of the master control board. All slave control boards in this embodiment share one ground terminal E-GND.
In this embodiment, the first input terminal 1 of the first optocoupler IC1 is connected to the first voltage division module R1', one end of the fifth resistor R5 is connected to the first input terminal 1 of the first optocoupler IC1, and the other end is connected to the second input terminal 2 of the first optocoupler IC 1. The second input terminal 2 of the first optocoupler IC1 is connected to the GND, the first output terminal 4 of the first optocoupler IC1 is connected to the seventh resistor R7, and the other end of the seventh resistor R7 is connected to the second switch circuit 102. The second output terminal 3 of the first optocoupler IC1 is connected to ground E-GND. One end of the sixth resistor R6 is connected to the first output terminal 4 of the first optocoupler IC1, and the other end is connected to the third reference power source V3.
Note that, in the present embodiment, the third reference power supply V3 is the same as the second reference power supply V2 shown in fig. 5, and different reference numerals are used here only for convenience of description of the components and are not shown to specifically limit the components.
In this embodiment, the first optocoupler IC1 is used to isolate the power supply and the ground between the master control board and each slave control board, so that the communication circuit can be applied in an isolated scenario. The voltage (for example, 5V) and GND provided by the second reference power supply V2 and the third reference power supply V3 are provided by the master control board, and the voltage and E-GND provided by the first reference power supply V1 are shared among the slave control boards.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a communication circuit according to a second embodiment of the present invention.
As shown in fig. 7, in the second embodiment, the receiving circuit 20 includes: a third switching circuit 201 and a fourth switching circuit 202. The third switch circuit 201 is connected to the communication bus, one end of the fourth switch circuit 202 is connected to the third switch circuit 201, and the other end of the fourth switch circuit 202 is connected to the receiving pin.
The third switch circuit 201 is configured to output a second voltage signal to the fourth switch circuit 202 according to a second bus voltage transmitted on the communication bus; the fourth switch circuit 202 is configured to output a second input signal to the receiving pin according to the second voltage signal.
As in the first embodiment described above, the third switch circuit 201 and the fourth switch circuit 202 work in cooperation with each other, and the purpose thereof is to invert a low voltage to a high voltage or invert a high voltage to a low voltage by a reference power supply connected to itself. The specific turning manner needs to be set according to actual conditions, and this embodiment does not specifically limit this.
Further, to simplify the circuit structure of the third switch circuit 201 and reduce the circuit manufacturing cost.
In one embodiment, the third switching circuit 201 may include: a second voltage division module 21 and a third switching module 22. The second voltage division module 21 is connected to the communication bus, and the third switch module 22 is connected to the second voltage division module 21 and the fourth switch circuit 202.
In this embodiment, the second voltage dividing module 21 is configured to divide a second bus voltage transmitted on the communication bus to obtain a divided bus voltage, and output the divided bus voltage to the third switching module 22;
the third switch module 22 is configured to output a second voltage signal to the fourth switch circuit 202 according to the divided bus voltage.
It should be noted that the specific circuit configuration of the second voltage division module 21 is not limited in this embodiment, and may be a module including only one voltage division resistor, a module including any other circuit device that realizes a voltage division function, or a module obtained by combining a plurality of circuit devices that realize a voltage division function.
In this embodiment, the third switching module 22 may be a switching circuit including one or more switching devices (e.g., a switching transistor or an optocoupler OCEP) for performing the opening and closing operations. When receiving different level signals, the third switching module 22 turns off or turns on the circuit, thereby outputting voltage signals with different voltage values.
In practical applications, the circuit structure of the receiving circuit 20 is simplified, and the manufacturing cost of the whole circuit is reduced. In this embodiment, a switching transistor is preferably used as the switching device in the third switching circuit 201 and the fourth switching circuit 202.
Referring to fig. 8, fig. 8 is a schematic circuit diagram of a communication circuit according to an embodiment of the present invention.
As shown in fig. 8, the third switching module 22 includes: an eighth resistor R8, a ninth resistor R9 and a third triode Q3; the second voltage dividing module 21 includes a voltage dividing resistor R2'.
One end of the eighth resistor R8 is connected to the fourth reference power source V4, and the other end is connected to the collector of the third transistor Q3. The base of the third transistor Q3 is connected to the second voltage divider 21 (i.e. one end of the voltage divider resistor R2'), and the emitter of the third transistor Q3 is grounded GND. One end of the ninth resistor R9 is connected to the base of the third transistor Q3, and the other end is connected to the emitter of the third transistor Q3.
In this embodiment, the fourth switching circuit 202 includes a fourth switching module including a tenth resistor R10, an eleventh resistor R11, and a fourth transistor Q4;
as shown in fig. 8, one end of the tenth resistor R10 is connected to the fifth reference power source V5, and the other end is connected to the collector of the fourth transistor Q4. A collector of the fourth transistor Q4 is connected to the receiving pin RXD, a base of the fourth transistor Q4 is connected to the third switching circuit 201 (i.e., the collector of the third transistor Q3), an emitter of the fourth transistor Q4 is grounded GND, one end of the eleventh resistor R11 is connected to the base of the fourth transistor Q4, and the other end of the eleventh resistor R11 is connected to the emitter of the fourth transistor Q4.
In this embodiment, the GND may be a ground terminal of the main board, and the fourth reference power supply V4 may be a power supply that provides a fourth reference voltage (e.g., 12V) to the main board. The fifth reference power supply V5 may be a power supply for providing a fifth reference voltage (e.g., 5V) to the main control board. In this embodiment, the fourth reference power supply V4 may be the same as the first reference power supply V1, and the voltage supplied by the fifth reference power supply V5 may be obtained by dividing the first reference voltage supplied by the first reference power supply V1.
Furthermore, in order to improve the signal-to-noise ratio of the communication circuit in long-line data transmission and ensure the reliability of data transmission. In this embodiment, the switch devices in the third switch circuit 201 and/or the fourth switch circuit 202 may also be implemented by an optocoupler OCEP. Here, the switching device in the fourth switching circuit 202 is exemplified by the optocoupler OCEP.
Referring to fig. 9, fig. 9 is a schematic circuit diagram of a communication circuit according to an embodiment of the present invention.
The fourth switch circuit 202 comprises a fifth switch module, which comprises a twelfth resistor R12, a thirteenth resistor R13, a second optocoupler IC2, and a first capacitor C1;
as shown in fig. 9, the first input terminal 1 of the second optocoupler IC2 is connected to the third switching circuit 201 (i.e., the collector of the third transistor Q3), the second input terminal 2 of the second optocoupler IC2 is connected to the ground E-GND, the first output terminal 4 of the second optocoupler IC2 is connected to one end of the twelfth resistor R12, the first end of the first capacitor C1 and the receiving pin RXD, the second output terminal 3 of the second optocoupler IC2 is connected to the ground GND, the other end of the twelfth resistor R12 is connected to the sixth reference power supply V6, and the second end of the first capacitor C1 is connected to the second output terminal 3 of the second optocoupler IC 2; one end of the thirteenth resistor R13 is connected to the first input terminal 1 of the second optocoupler IC2, and the other end of the thirteenth resistor R13 is connected to the second input terminal 2 of the second optocoupler IC 2.
Note that, in the present embodiment, the sixth reference power supply V6 is the same as the second reference power supply V2 shown in fig. 5, and different reference numerals are used here only for convenience of description, and are not shown as specific limitations on the components. The second optocoupler IC2 also functions as the first optocoupler IC1 to isolate the power supply and ground between the master controller and the slave controllers, so that the communication circuit can be used in isolated scenarios.
A third embodiment of the communication circuit of the present invention is proposed based on the above-described embodiments.
In the third embodiment, the receiving circuit 20 includes: a voltage divider circuit.
The voltage dividing circuit is used for receiving a second bus voltage transmitted on the communication bus, dividing the second bus voltage to obtain a second input signal, and transmitting the second input signal to a receiving pin RXD.
As an embodiment, the voltage dividing circuit in this embodiment may include a third voltage dividing module 31 and a fourth voltage dividing module 41. The third voltage dividing module 31 is connected to the communication bus, one end of the fourth voltage dividing module 41 is connected to the third voltage dividing module 31, and the other end is connected to the receiving pin RXD.
The third voltage dividing module 31 is configured to receive a second bus voltage transmitted on the communication bus, divide the second bus voltage, and output the divided second bus voltage to the fourth voltage dividing module; the fourth voltage division module 41 is configured to invert the voltage transmitted by the third voltage division module into a second input signal, and transmit the second input signal to the receiving pin.
It should be noted that, the specific circuit configuration of the third voltage dividing module 31 is not limited in this embodiment, and it may be a module that only includes one resistor, for example, R3' in fig. 10, and the module is used to divide the voltage transmitted on the communication bus and output the divided voltage to the fourth voltage dividing module 41 for inversion.
As another implementation mode, the adverse effect of the high-frequency signal on the signal processing of the control chip is reduced. In this embodiment, the fourth voltage dividing module 41 may include a fourteenth resistor R14 and a second capacitor C2, so that the second capacitor C2 filters out high frequency interference signals.
Referring to fig. 10, fig. 10 is another circuit schematic diagram of a communication circuit according to an embodiment of the present invention.
As shown in fig. 10, a first end of the second capacitor C2 is connected to the third voltage division module 31 and the receiving pin, respectively, a second end of the second capacitor C2 is grounded, one end of the fourteenth resistor R14 is connected to the first end of the second capacitor C2, and the other end of the fourteenth resistor R14 is connected to the second end of the second capacitor C2.
For better illustration, the voltage inversion principle of the communication circuit in this embodiment is described herein with reference to fig. 10.
As shown in fig. 10, when the transmit pin TXD transmits a high level, the base voltage of the second transistor Q2 is higher than the emitter voltage, the second transistor Q2 is turned on, the collector voltage of the second transistor Q2 is close to zero, the base voltage and the emitter voltage of the first transistor Q1 are both zero, and thus the first transistor Q1 is turned off. At this time, the voltage output to the communication bus can be calculated by the following equation:
according to actual needs, the resistance value of the first resistor R1 may be selected to be much smaller than the sum of the resistance values of the third voltage dividing resistor R3 'and the fourteenth resistor R14 (i.e., R3' + R14), so that the voltage on the communication bus is close to the first reference voltage output by the first reference power supply V1, and the communication bus is compatible with the high voltage (e.g., 12V) on the communication line required by the standard LIN communication protocol specification.
Accordingly, the voltage of the receive pin RXD can be calculated by:
considering that the communication protocol used by the master control board and the slave control board is generally UART, and the protocol requires a high voltage of 5V, in practical applications, the resistances of the third voltage dividing resistor R3' and the fourteenth resistor R14 should satisfy the following formula:
at this time, the voltage of the receiving pin RXD is 5V, which meets the high voltage required by the UART communication standard.
In another case, when the transmit pin TXD transmits a low level, both the base and emitter voltages of the second transistor Q2 are zero and the second transistor Q2 is turned off. The base voltage of the first transistor Q1 is higher than the emitter voltage, the first transistor Q1 is turned on, the emitter voltage of the first transistor Q1 is near zero, and the voltage on the communication bus is near zero. According to the above calculation VRXDThe voltage at the receive pin RXD can be calculated to be close to zero.
It should be noted that the communication circuit provided in this embodiment is applied to a non-isolated scenario in which there is no requirement for isolation between a power supply and a ground.
The communication circuit provided by the embodiment has a simple structure, only occupies one group of TXD and RXD ports of the main control board, and the communication wire harness only needs three wire harnesses of a power line, a ground line and a bus, so that the communication effect of mounting a plurality of functional modules on one host, a plurality of slaves and a single bus can be realized.
A fourth embodiment of the communication circuit of the present invention is proposed based on the first and second embodiments described above.
Referring to fig. 11 and 12, fig. 11 is a schematic structural diagram of a fourth embodiment of the communication circuit according to the embodiment of the present invention. Fig. 12 is another schematic circuit diagram of a communication circuit according to an embodiment of the present invention.
As shown in fig. 11, the communication circuit in this embodiment may include: a transmission circuit 10, a reception circuit 20, and a filter protection circuit 30. The filter protection circuit 30 is connected to the communication bus and configured to filter out a high-frequency interference signal on the communication bus. The transmission circuit 10 may include a first switch circuit 101 and a second switch circuit 102, and the reception circuit 20 may include a third switch circuit 201 and a fourth switch circuit 202.
In order to filter out high-frequency interference signals on the communication bus and simultaneously prevent static electricity or abnormal surge voltage in the communication bus. In the present embodiment, the filter protection circuit 30 includes a third capacitor C3, and a patch switch diode D1 composed of two first and second diodes connected in series.
In a specific implementation, the first switch circuit 101, the second switch circuit 102, the third switch circuit 201, the fourth switch circuit 202 and the filter protection circuit shown in fig. 11 may be embodied as the circuit principle shown in fig. 12. In practical applications, the communication circuits provided by the present invention are symmetrically arranged in the master control board and the slave control board, and refer to fig. 12 specifically.
As shown in fig. 12, a first terminal of the third capacitor C3 is connected to the communication bus, a second terminal of the third capacitor C3 is grounded GND, an anode of a first diode of the patch switch diode D1 is connected to the second terminal of the third capacitor, a cathode of the first diode is connected to an anode of a second diode, a cathode of the second diode is connected to the reference power source V7, and a cathode of the first diode is connected to the communication bus.
The reference power supply V7 is the same as the first reference power supply V1 shown in fig. 5, and different reference numerals are used here only for convenience of description of the embodiment and are not shown as specific limitations on the component.
In addition, for convenience of description, the reference numerals of the circuit components in the slave control board are represented by lower case english letters corresponding to the reference numerals of the same components in the master control board.
Here, with reference to fig. 12, the following description will be given taking an example in which the master board transmits signals and the slave board receives signals: in practical application, when the master control board sends a high level, Q2 and Q1 are used for level inversion so that the high voltage on the communication bus is:
in the formula, Vq5be is the voltage at the be junction of transistor q 5.
The high voltage of the communication bus is inverted by the q5 and q6 levels on the slave control board to obtain the high level identified by the slave control board, and the whole process realizes that the signal level sent by the master control board is consistent with the signal level received by the slave control board. Conversely, the slave control board sends the data, and the master control board receives the data in a reverse process, which is not described herein again. Through the level upset, can raise the communication bus level, be favorable to improving communication quality, can use in the longer scene of communication line.
Further, referring to fig. 13, fig. 13 is another schematic circuit diagram of a communication circuit according to an embodiment of the present invention.
Based on fig. 13, the principle of level inversion of the communication circuit according to the present embodiment will be described:
when the transmitting pin TXD transmits a high level, the primary side of the optical coupler IC1 works, the secondary side is conducted, and the voltage of the No. 4 pin of the optical coupler IC1 is close to zero at the moment. Therefore, the base voltage and the emitter voltage of the first transistor Q1 are both zero, and the first transistor Q1 is turned off. At this time, the bus voltage output to the communication bus can be calculated by the following equation:
in a specific implementation, the resistance of the first resistor R1 may be much smaller than the sum of the resistances of the ninth resistor R9 and the second voltage-dividing resistor R2'. Therefore, the bus voltage output by the transmitting circuit is close to the first reference voltage provided by the first reference power supply V1 to be compatible with the standard communication protocol specification used by the communication bus. Meanwhile, the base voltage of the third triode Q3 is higher than the emitter voltage, the third triode Q3 is turned on, the collector voltage of the third triode Q3 is close to zero, the voltage of the pin 1 of the second optocoupler IC2 is close to zero, the primary side does not work, the secondary side is cut off, and the voltage of the receiving pin RXD is close to 5V.
In addition, when the tx pin TXD transmits a low level, the primary side of the first optocoupler IC1 is disabled and the secondary side is disabled, the base voltage of the first transistor Q1 is higher than the emitter voltage, the first transistor Q1 is turned on, and the collector voltage of the first transistor Q1 is close to zero. The voltage output to the communication bus is equal to the collector voltage of the first transistor Q1, so the bus voltage is zero. The base voltage of the third triode Q3 is equal to the emitter voltage, the third triode Q3 is cut off, and the instantaneous collector voltage V of the third triode Q3Q3 setCan be calculated by the following formula:
in a specific implementation, the eighth resistor R8 and the thirteenth resistor R13 may have equal resistance values, so that an instantaneous voltage of the collector of the third transistor Q3 is half (for example, 6V) of a reference voltage provided by the fourth reference power supply V4, and the voltage is higher than a voltage at which the primary side of the second optocoupler IC2 is turned on. Thus, the primary side of the second optocoupler IC2 operates and the secondary side is conductive. The voltage on pin No. 4 of the second photo-coupler IC2 is close to zero, and the voltage on the receive pin RXD is equal to the voltage on pin No. 4 of the second photo-coupler IC2, so the voltage on the receive pin RXD is close to zero.
The communication circuit provided by the embodiment has a simple structure, only occupies one group of TXD and RXD ports of the main control board, and the communication wiring harness only needs three wiring harnesses of a power line, a ground wire and a communication bus, so that the communication effect of mounting a plurality of functional modules on one host, a plurality of slaves and a single bus can be realized.
In order to achieve the above object, the present invention also provides a communication board including the communication circuit as described above. The specific structure of the circuit refers to the above embodiments, and since the communication board can adopt the technical solutions of all the above embodiments, the communication board at least has the beneficial effects brought by the technical solutions of the above embodiments, and details are not repeated herein.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all equivalent structures or equivalent processes performed by the present invention or directly or indirectly applied to other related technical fields are also included in the scope of the present invention.
It should be noted that, in the practical application of the present invention, the software program is inevitably applied to the software program, but the applicant states here that the software program applied in the embodiment of the present invention is the prior art, and in the present application, the modification and protection of the software program are not involved, but only the protection of the hardware architecture designed for the purpose of the present invention.
Claims (17)
1. A communication circuit, wherein the communication circuit comprises:
the transmitting circuit is arranged between a transmitting pin and a communication bus and used for inverting a first input signal transmitted by the transmitting pin into a first bus voltage and outputting the first bus voltage to the communication bus; and
and the receiving circuit is arranged between the receiving pin and the communication bus, and is used for receiving the second bus voltage transmitted on the communication bus, inverting the second bus voltage into a second input signal and transmitting the second input signal to the receiving pin.
2. The communication circuit of claim 1, wherein the transmit circuit comprises:
the first switch circuit is respectively connected with the sending pin and the second switch circuit and used for outputting a first voltage signal to the second switch circuit according to a first input signal transmitted by the sending pin; and
and the second switch circuit is respectively connected with the first switch circuit and the communication bus and is used for outputting a first bus voltage to the communication bus according to the first voltage signal.
3. The communication circuit of claim 2, wherein the first switching circuit comprises:
the first voltage division module is respectively connected with the sending pin and the first switch module and is used for dividing the first input signal transmitted by the sending pin to obtain a divided input signal and outputting the divided input signal to the first switch module; and
and the first switch module is respectively connected with the first voltage division module and the second switch circuit and is used for outputting a first voltage signal to the second switch circuit according to the input signal after voltage division.
4. The communication circuit of claim 3, wherein the second switching circuit comprises a second switching module;
the second switch module comprises a first resistor, a second resistor and a first triode, one end of the first resistor is connected with a first reference power supply, the other end of the first resistor is connected with a collector of the first triode, an emitter of the first triode is grounded, a base of the first triode is respectively connected with the first switch circuit and the second resistor, and the other end of the second resistor is grounded.
5. The communication circuit of claim 3, wherein the first switching module comprises a third resistor, a fourth resistor, and a second transistor;
one end of the third resistor is connected with a second reference power supply, the other end of the third resistor is connected with a collector of the second triode, an emitter of the second triode is grounded, a base of the second triode is connected with the signal output end of the first voltage division module and the fourth resistor respectively, and the other end of the fourth resistor is grounded.
6. The communication circuit of claim 3, wherein the first switching module comprises fifth to seventh resistors and a first optocoupler;
the first input end of the first optical coupler is connected with the fifth resistor and the first voltage division module respectively, the second input end of the first optical coupler is connected with the other end of the fifth resistor, the second input end of the first optical coupler is grounded, the first output end of the first optical coupler is connected with the sixth resistor and the seventh resistor respectively, the second output end of the first optical coupler is grounded, the other end of the sixth resistor is connected with a third reference power supply, and the other end of the seventh resistor is connected with the second switch circuit.
7. The communication circuit of claim 1, wherein the receive circuit comprises:
the third switch circuit is respectively connected with the communication bus and the fourth switch circuit and used for outputting a second voltage signal to the fourth switch circuit according to a second bus voltage transmitted on the communication bus; and
and the fourth switch circuit is respectively connected with the receiving pin and the third switch circuit and is used for outputting a second input signal to the receiving pin according to the second voltage signal.
8. The communication circuit of claim 7, wherein the third switching circuit comprises:
the second voltage division module is respectively connected with the communication bus and the third switch module and is used for dividing the second bus voltage transmitted on the communication bus to obtain the divided bus voltage and outputting the divided bus voltage to the third switch module; and
and the third switch module is respectively connected with the second voltage division module and the fourth switch circuit and is used for outputting a second voltage signal to the fourth switch circuit according to the divided bus voltage.
9. The communication circuit of claim 8, wherein the third switching module comprises: the eighth resistor, the ninth resistor and the third triode;
one end of the eighth resistor is connected with a fourth reference power supply, the other end of the eighth resistor is connected with a collector of the third triode, a base of the third triode is connected with the second voltage division module, an emitter of the third triode is grounded, one end of the ninth resistor is connected with the base of the third triode, and the other end of the ninth resistor is connected with the emitter of the third triode.
10. The communication circuit of claim 7, wherein the fourth switching circuit comprises a fourth switching module;
the fourth switching module comprises a tenth resistor, an eleventh resistor and a fourth triode;
one end of the tenth resistor is connected with a fifth reference power supply, the other end of the tenth resistor is connected with a collector of the fourth triode, the collector of the fourth triode is connected with the receiving pin, a base of the fourth triode is connected with the third switching circuit, an emitter of the fourth triode is grounded, one end of the eleventh resistor is connected with the base of the fourth triode, and the other end of the eleventh resistor is connected with the emitter of the fourth triode.
11. The communication circuit of claim 7, wherein the fourth switching circuit comprises a fifth switching module;
the fifth switch module comprises a twelfth resistor, a thirteenth resistor, a second optical coupler and a first capacitor;
a first input end of the second optical coupler is connected with the third switch circuit, a second input end of the second optical coupler is grounded, a first output end of the second optical coupler is respectively connected with one end of the twelfth resistor, a first end of the first capacitor and the receiving pin, a second output end of the second optical coupler is grounded, the other end of the twelfth resistor is connected with a sixth reference power supply, and a second end of the first capacitor is connected with a second output end of the second optical coupler; one end of the thirteenth resistor is connected with the first input end of the second optical coupler, and the other end of the thirteenth resistor is connected with the second input end of the second optical coupler.
12. The communication circuit of claim 1, wherein the receive circuit comprises:
and the voltage division circuit is used for receiving a second bus voltage transmitted on the communication bus, dividing the second bus voltage to obtain a second input signal and transmitting the second input signal to the receiving pin.
13. The communication circuit of claim 12, wherein the voltage divider circuit comprises:
the third voltage division module is respectively connected with the communication bus and the fourth voltage division module, and is used for receiving a second bus voltage transmitted on the communication bus, dividing the second bus voltage and outputting the divided second bus voltage to the fourth voltage division module; and
and the fourth voltage division module is respectively connected with the third voltage division module and the receiving pin, and is used for inverting the voltage transmitted by the third voltage division module into a second input signal and transmitting the second input signal to the receiving pin.
14. The communication circuit according to claim 13, wherein the fourth voltage dividing module comprises a fourteenth resistor and a second capacitor, a first end of the second capacitor is connected to the third voltage dividing module and the receiving pin, respectively, a second end of the second capacitor is grounded, one end of the fourteenth resistor is connected to the first end of the second capacitor, and the other end of the fourteenth resistor is connected to the second end of the second capacitor.
15. The communication circuit of any of claims 1 to 14, further comprising:
and the filter protection circuit is connected with the communication bus and is used for filtering high-frequency interference signals on the communication bus.
16. The communication circuit of claim 15, wherein the filter protection circuit comprises a third capacitor, two first and second diodes connected in series, a first terminal of the third capacitor being connected to the communication bus, a second terminal of the third capacitor being connected to ground, an anode of the first diode being connected to the second terminal of the third capacitor, a cathode of the first diode being connected to an anode of the second diode, a cathode of the second diode being connected to a reference power supply, and a cathode of the first diode being connected to the communication bus.
17. A communication board characterized in that it comprises a communication circuit as claimed in any one of claims 1 to 16.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220249730.5U CN217037179U (en) | 2022-01-30 | 2022-01-30 | Communication circuit and communication board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220249730.5U CN217037179U (en) | 2022-01-30 | 2022-01-30 | Communication circuit and communication board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217037179U true CN217037179U (en) | 2022-07-22 |
Family
ID=82449031
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220249730.5U Active CN217037179U (en) | 2022-01-30 | 2022-01-30 | Communication circuit and communication board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217037179U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116736752A (en) * | 2022-09-21 | 2023-09-12 | 荣耀终端有限公司 | Switching circuit, electronic device and electronic system |
-
2022
- 2022-01-30 CN CN202220249730.5U patent/CN217037179U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116736752A (en) * | 2022-09-21 | 2023-09-12 | 荣耀终端有限公司 | Switching circuit, electronic device and electronic system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107070445B (en) | Serial communication interface function switching circuit and method | |
| CN217037179U (en) | Communication circuit and communication board | |
| CN106649171B (en) | Single-bus full-duplex data communication method and system | |
| CN108647180A (en) | A kind of arithmetic system and corresponding electronic equipment | |
| CN216873219U (en) | Communication circuit and multi-master communication system | |
| CN103118143B (en) | Multiplex circuit of serial interface and Ethernet interface | |
| CN106372025B (en) | Bus type communicating circuit | |
| CN116303205A (en) | Three-in-one interface circuit for serial port, control method thereof and serial port system chip | |
| CN209842613U (en) | Data transmission device | |
| CN214707733U (en) | Communication circuit of monitoring equipment | |
| CN210112034U (en) | CAN transceiver circuit and CAN communication system | |
| CN205105240U (en) | Communication circuit | |
| CN217643403U (en) | RS485 data transceiver circuit and Ethernet switch | |
| CN219659735U (en) | PLC network expansion middleware and PLC network expansion system | |
| CN216751748U (en) | Terminal resistor access control circuit, communication circuit and communication equipment | |
| CN109933550A (en) | A kind of redundancy universal bus system for supporting customized signal | |
| CN213027773U (en) | POE switch network transformer circuit and switch | |
| CN212992306U (en) | Bus switch circuit and device | |
| CN215956411U (en) | Remote communication device | |
| CN220627045U (en) | Conversion circuit for converting serial port into two buses and equipment with serial port into two buses | |
| CN113141244B (en) | Full duplex communication device, electrical appliance system and communication method thereof | |
| CN102447601B (en) | S-bus monobus communicating circuit | |
| CN219802306U (en) | Isolation communication circuit, communication device and Internet of things communication equipment | |
| CN218676031U (en) | Adaptor plate and adaptor device of industrial control equipment and industrial control system | |
| CN216599612U (en) | Terminal matching resistance switching circuit and RS485 networking communication system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |