CN217008204U

CN217008204U - Main control board based on godson dual-system platform

Info

Publication number: CN217008204U
Application number: CN202123383908.XU
Authority: CN
Inventors: 严朋; 李国利; 熊笑颜
Original assignee: Hefei Zhuoyi Hengtong Information Security Co Ltd
Current assignee: Hefei Zhuoyi Hengtong Information Security Co Ltd
Priority date: 2021-12-28
Filing date: 2021-12-28
Publication date: 2022-07-19
Anticipated expiration: 2031-12-28

Abstract

The utility model provides a main control board based on a Loongson dual-system platform. The main control board based on the Loongson dual-system platform comprises a Loongson general processor, a bridge chip, a Loongson embedded processor, an FPGA (field programmable gate array), a micro control unit, a first memory chip, a second memory chip and a third memory chip. The utility model comprises a Loongson general processor system platform and a Loongson embedded processor system platform, can independently run respective operating systems without mutual interference and supports domestic operating systems. And the two system platforms are designed in the same main control board, and can be assisted by division of labor to process different service types, thereby improving the integration level of the system. And components and an operating system on the main control board can realize nationwide productions, and can prevent foreign technology blockade and limitation.

Description

Main control board based on godson dual-system platform

Technical Field

The utility model relates to the field of computer hardware, in particular to a main control board based on a Loongson dual-system platform.

Background

The safe credibility and the autonomous controllability are requirements of the current situation on a domestic computing platform, wherein the safe credibility design is the core competitiveness of the domestic computing equipment, and the hardware architecture and the software algorithm design are innovative breakthrough points of the domestic computing equipment. The safe and reliable design comprises an autonomous cryptosystem at a theoretical level, active control at a chip level, calculation and reliable double-node fusion at a main control board level, a double-system architecture at a software level and the like.

As a new-generation open industry standard, the ATCA (Advanced Telecom Computing Architecture) has attracted attention in the industry since its introduction in 2002. Under the strong push of many enterprises in the industry chain, the industrial applicability of the method is gradually increased. Many major manufacturers of telecommunications equipment have adopted ATCA to design new products. ATCA is now widely accepted from a small range of applications and will find large scale application.

In the actual production process, there are users who put forward the following needs: the computer main control board can process different service types simultaneously, can not affect each other when processing different services, and simultaneously requires devices and operation systems and the like which are nationwide produced. Based on this, it is necessary to design a computer main control board based on a dual system platform.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a main control board based on a Loongson dual-system platform, which can process different service types at the same time, cannot influence each other when processing different services and has higher system integration level.

In order to achieve the above object, the present invention provides a main control board based on a dual Loongson system platform, which includes a Loongson general processor, a bridge chip, a Loongson embedded processor, an FPGA, a micro control unit, a first memory chip, a second memory chip, and a third memory chip;

the godson general processor is in communication connection with the bridge chip, the godson embedded processor, the FPGA and the micro control unit are in communication connection with the bridge chip, the FPGA and the micro control unit are in communication connection with the godson embedded processor, and the FPGA is in communication connection with the micro control unit;

the first memory chip is in communication connection with the Loongson general processor, the second memory chip is in communication connection with the Loongson embedded processor, and the third memory chip is in communication connection with the FPGA.

A core control board for ATCA equipment.

The first memory chip, the second memory chip and the third memory chip are all onboard memory chips;

the first memory chip, the second memory chip and the third memory chip are all DDR memory chips;

the capacity of the first memory chip is 8GB, the capacity of the second memory chip is 4GB, and the capacity of the third memory chip is 4 GB.

The godson general processor and the bridge chip are used for forming one system platform, the godson embedded processor is used for forming another system platform, the two system platforms respectively and independently run respective operating systems, and the godson general processor and the godson embedded processor are respectively connected with different power supplies, so that the two system platforms can be independently turned on and turned off.

The Loongson general processor is an LS3A4000 series chip, the bridge chip is an LS7A1000 series chip, and the Loongson embedded processor is an LS2K1000 series chip.

The godson general processor is provided with a UART port and an SPI port, and the master control board based on the godson dual-system platform further comprises a debug device in communication connection with the UART port and an SPI FLASH in communication connection with the SPI port.

The bridge chip is provided with a PCIE multiplied by 4 port, a SATA2.0 port, a USB2.0 port, a UART port and a DVO port;

the number of the PCIE multiplied by 4 ports is three, the number of the SATA2.0 port, the number of the USB2.0 port and the number of the DVO port are all one, and the number of the UART ports is four;

the main control board based on the Loongson dual-system platform further comprises a first ZD connector, a first network chip, a second network chip, a first display signal conversion chip, a first mSATA slot, a USB2.0 interface, a second ZD connector, a gigabit network port, a third ZD connector and a VGA signal interface;

the bridge chip is respectively in communication connection with the first ZD connector, the first network chip and the second network chip through three PCIE multiplied by 4 ports; the first network chip outputs network signals to a gigabit network port, and the second network chip outputs network signals to a third ZD connector;

the first display signal conversion chip is respectively in communication connection with the DVO port and the VGA signal interface, receives DVO signals from the DVO port, converts the DVO signals into VGA signals and outputs the VGA signals to the VGA signal interface;

the bridge chip is respectively in communication connection with the FPGA, the second ZD connector, the micro control unit and the Loongson embedded processor through four UART ports;

the bridge chip is in communication connection with a first mSATA slot through a SATA2.0 port, and is in communication connection with a USB2.0 interface through a USB2.0 port.

The Loongson embedded processor is provided with a PCIE x 4 port, an RGMII port, a DVO port, a PCIE x1 port, a UART port, an SATA port and a USB2.0 port;

the main control board based on the Loongson dual-system platform further comprises a third network chip, a fourth ZD connector, a second display signal conversion chip, a fifth ZD connector, a sixth ZD connector, a second mSATA slot and a seventh ZD connector;

the number of the PCIE x 4 ports, the RGMII ports, the DVO ports, the PCIE x1 ports, the SATA ports and the USB2.0 ports is one, and the number of the UART ports is two;

the Loongson embedded processor is in communication connection with a third network chip through an RGMII port; the third network chip is in communication connection with the second network chip, so that the in-board interconnection of the network signals output by the bridge chip and the Loongson embedded processor is realized;

the Loongson embedded processor is in communication connection with a fourth network chip through a PCIE x 4 port, and the fourth network chip 31 is in communication connection with a fourth ZD connector;

the second display signal conversion chip is respectively in communication connection with the DVO port and the fifth ZD connector, and receives DVO signals from the DVO port and converts the DVO signals into VGA signals to output the VGA signals to the fifth ZD connector;

the Loongson embedded processor is in communication connection with a sixth ZD connector through a PCIE multiplied by 1 port; the Loongson embedded processor is respectively in communication connection with the FPGA and the micro control unit through two UART ports; the Loongson embedded processor is in communication connection with a second mSATA slot through a SATA port; and the Loongson embedded processor is in communication connection with a seventh ZD connector through a USB2.0 port.

The system also comprises an eighth ZD connector, a fan control chip, an expansion IO chip and a time sequence control CPLD chip;

the micro control unit is provided with two I2C ports and a UART port;

the micro control unit is respectively in communication connection with the fan control chip and the expansion IO chip through two I2C ports, and the expansion IO chip outputs GPIO signals to the sequential control CPLD chip; the micro control unit is in communication connection with the FPGA through a UART port;

the FPGA is provided with an LVDS port and is in communication connection with the eighth ZD connector through the LVDS port.

The model of the Loongson general processor is LS3A4000-I, the model of the bridge chip is LS7A1000-BA, the model of the Loongson embedded processor is LS2K1000-I, the model of the FPGA is national microelectronic SMQ7K325TFFG676, and the model of the micro control unit is megaly creative GD32F450IIH 6;

the model of the first display signal conversion chip and the model of the second display signal conversion chip are both vibration cores GM71 7123C, the model of the fan control chip is megaly innovation GD32F103C8T6, the model of the expansion IO chip is moxa 9110B, the model of the time sequence control CPLD chip is a high cloud semiconductor GW1N-UV4LQ1006/I5, the model of the first network chip is network fast technology WX1860A2, the model of the second network chip is network fast technology WX1860A4, the model of the third network chip is Yutai microelectronics YT8521SH-CA, and the model of the fourth network chip is network fast technology WX1860A 4.

The utility model has the beneficial effects that: the utility model provides a main control board based on a Loongson dual-system platform, which comprises a Loongson general processor, a bridge chip, a Loongson embedded processor, an FPGA (field programmable gate array), a micro control unit, a first memory chip, a second memory chip and a third memory chip, wherein the Loongson general processor is connected with the bridge chip; the godson general processor is in communication connection with the bridge chip, the godson embedded processor, the FPGA and the micro control unit are in communication connection with the bridge chip, the FPGA and the micro control unit are in communication connection with the godson embedded processor, and the FPGA is in communication connection with the micro control unit; the first memory chip is in communication connection with the Loongson general processor, the second memory chip is in communication connection with the Loongson embedded processor, and the third memory chip is in communication connection with the FPGA. The utility model comprises a Loongson general processor system platform and a Loongson embedded processor system platform, can independently run respective operating systems without mutual interference and supports domestic operating systems. And the two system platforms are designed into the same main control board, and can be assisted by division of labor to process different service types, thereby improving the integration level of the system.

Drawings

For a better understanding of the nature and technical aspects of the present invention, reference should be made to the following detailed description of the utility model, taken in conjunction with the accompanying drawings, which are provided for purposes of illustration and description, and are not intended to limit the utility model.

In the attached figures, the drawing is shown,

fig. 1 is a schematic block diagram of a main control board based on a dual Loongson system platform according to the present invention.

Detailed Description

To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.

Referring to fig. 1, the present invention provides a main control board based on a loongson dual-system platform, which is used for a core control board of an ATCA device, where the ATCA device is applied to the field of network communication. The main control board includes a Loongson general processor 1, a bridge chip 2, a Loongson embedded processor 3, a Field Programmable Gate Array (FPGA) 4, a Micro Control Unit (MCU) 5, a first memory chip 12, a second memory chip 36, and a third memory chip 42.

The Loongson general processor 1 is in communication connection with the bridge piece 2, the Loongson embedded processor 3, the FPGA 4 and the micro control unit 5 are in communication connection with the bridge piece 2, the FPGA 4 and the micro control unit 5 are in communication connection with the Loongson embedded processor 3, and the FPGA 4 is in communication connection with the micro control unit 5.

The first memory chip 12 is in communication connection with the Loongson general processor 1, the second memory chip 36 is in communication connection with the Loongson embedded processor 3, and the third memory chip 42 is in communication connection with the FPGA 4.

Optionally, the Loongson general-purpose processor 1 and the bridge chip 2 are communicatively connected through a High Transport (HT) 1.0 bus.

The Loongson general processor 1 is an LS3A4000 series chip, the bridge chip 2 is an LS7A1000 series chip, and the Loongson embedded processor 3 is an LS2K1000 series chip.

Preferably, the model of the Loongson general processor 1 is LS3A4000-I, the model of the bridge chip 2 is LS7A1000-BA, and the model of the Loongson embedded processor 3 is LS2K 1000-I.

The model of the FPGA 4 is national microelectronic SMQ7K325TFFG676, and the model of the micro control unit 5 is megaly innovative GD32F450IIH 6.

Specifically, the main control board adopts an onboard memory mode, that is, a memory is integrated on the main control board. Compared with an off-board memory, the on-board memory has improved performance stability, structural stability and the like. That is, the first memory chip 12, the second memory chip 36, and the third memory chip 42 are all on-board memory chips.

Specifically, the first memory chip 12, the second memory chip 36, and the third memory chip 42 are all DDR (Double Data Rate) memory chips. The capacity of the first memory chip 12 is 8GB, the capacity of the second memory chip 36 is 4GB, and the capacity of the third memory chip 42 is 4 GB.

Preferably, the first memory chip 12 is a Double Data Rate (DDR 4) fourth generation memory chip. The second memory chip 36 is a Double Data Rate (DDR 3) memory chip of the third generation. The third memory chip 42 is a DDR3 memory chip.

In an embodiment of the utility model, the first memory chip 12 is eight DDR4 memory chips mounted on board, and the total capacity is 8 GB. The second memory chip 36 is four onboard DDR3 memory chips, and the total capacity is 4 GB. The third memory chip 42 is four onboard DDR3 memory chips, and the total capacity is 4 GB.

Specifically, the godson Universal processor 1 has a Universal Asynchronous Receiver/Transmitter (UART) port and a Serial Peripheral Interface (SPI) port, and the main control board further includes a debug device 11 communicatively connected to the UART port and a Serial Peripheral Interface (SPI) FLASH memory (FLASH)13 communicatively connected to the SPI port.

The bridge chip 2 has a high-speed Serial component interconnect (PCIE) × 4 port, a Serial Advanced Technology Attachment (SATA) 2.0 port, a USB2.0 port, a UART port, and a Digital Video Output (DVO) port.

The number of the PCIE multiplied by 4 ports is three, the number of the SATA2.0 port, the number of the USB2.0 port and the number of the DVO port are all one, and the number of the UART ports is four.

The main control board further includes a first ZD connector (high-speed board-to-board connector) 21, a first network chip 22, a second network chip 23, a first display signal conversion chip 24, a first msiata (mini Serial Advanced Technology attachment) slot 25, a USB2.0 interface 26, a second ZD connector 27, a gigabit net port 28, a third ZD connector 29, and a Video Graphics Array (VGA) signal interface 241.

The bridge chip 2 is respectively connected to the first ZD connector 21, the first network chip 22, and the second network chip 23 through three PCIE × 4 ports in a communication manner. The first network chip 22 outputs a network signal to the gigabit port 28, and the second network chip 23 outputs a network signal to the third ZD connector 29.

The first display signal conversion chip 24 is respectively in communication connection with the DVO port and the VGA signal interface 241, and the first display signal conversion chip 24 receives the DVO signal from the DVO port and converts the DVO signal into a VGA signal to output the VGA signal to the VGA signal interface 241.

The bridge chip 2 is respectively in communication connection with the FPGA 4, the second ZD connector 27, the micro control unit 5 and the Loongson embedded processor 3 through four UART ports.

The bridge chip 2 is in communication connection with the first mSATA slot 25 through a SATA2.0 port, so that data transmission is performed after the storage device is externally connected. The bridge chip 2 is connected with the USB2.0 interface 26 through the USB2.0 port in a communication mode, so that a USB2.0 signal is output.

Specifically, the Loongson embedded processor 3 has a PCIE × 4 port, a Reduced Gigabit Media Independent Interface (RGMII) port, a DVO port, a PCIE × 1 port, a UART port, an SATA port, and a USB2.0 port.

The main control board further includes a third network chip 30, a fourth network chip 31, a fourth ZD connector 311, a second display signal conversion chip 32, a fifth ZD connector 321, a sixth ZD connector 33, a second mSATA slot 34, and a seventh ZD connector 35.

The number of the PCIE multiplied by 4 ports, the RGMII ports, the DVO ports, the PCIE multiplied by 1 ports, the SATA ports and the USB2.0 ports is one, and the number of the UART ports is two.

The Loongson embedded processor 3 is communicatively connected to the third network chip 30 through an RGMII port. The third network chip 30 is in communication connection with the second network chip 23, so as to achieve the in-board interconnection of the network signals output by the bridge chip 2 and the Loongson embedded processor 3.

The Loongson embedded processor 3 is connected to a fourth network chip 31 through PCIE × 4 port communication, and the fourth network chip 31 is connected to a fourth ZD connector 311 through communication.

The second display signal conversion chip 32 is respectively connected to the DVO port and the fifth ZD connector 321 in a communication manner, and the second display signal conversion chip 32 receives the DVO signal from the DVO port and converts the DVO signal into a VGA signal and outputs the VGA signal to the fifth ZD connector 321.

The first display signal conversion chip 24 and the second display signal conversion chip 32 are both of the type GM 7123C.

The Loongson embedded processor 3 is in communication connection with a sixth ZD connector 33 through PCIE multiplied by 1 ports, and the Loongson embedded processor 3 is in communication connection with the FPGA 4 and the micro control unit 5 through two UART ports respectively; the Loongson embedded processor 3 is connected with a second mSATA slot 34 through SATA port communication, and the Loongson embedded processor 3 is connected with a seventh ZD connector 35 through USB2.0 port communication.

Specifically, the main control board further includes an eighth ZD connector 41, a fan control chip 51, an Input Output (IO) chip 52, and a timing control CPLD (Complex Programmable Logic Device) chip 53.

The micro-control unit 5 has two I2C (Inter-Integrated Circuit) ports and one UART port. The micro control unit 5 is respectively connected to the fan control chip 51 and the extended IO chip 52 through two I2C ports in a communication manner, and the extended IO chip 52 outputs a GPIO (General purpose input/output) signal to the timing control CPLD chip 53. The micro control unit 5 is in communication connection with the FPGA 4 through a UART port.

The FPGA 4 has a Low-Voltage Differential Signaling (LVDS) port, and the FPGA 4 is communicatively connected to the eighth ZD connector 41 through the LVDS port.

The model of the fan control chip 51 is megaly innovation GD32F103C8T6, the model of the extended IO chip 52 is electronic AW9110B, and the model of the time sequence control CPLD chip 53 is a high cloud semiconductor GW1N-UV4LQ 1006/I5.

In an embodiment of the present invention, the main control board integrates 11 gigabit networks, the first network chip 22 has a model of network technology WX1860a2, the second network chip 23 has a model of network technology WX1860a4, the third network chip 30 has a model of yutai microelectronics YT8521SH-CA, and the fourth network chip 31 has a model of network technology WX1860a 4. The number of the gigabit ports 28 is two, and the first network chip 22 outputs two network signals to the two gigabit ports 28 (denoted as ports (1 to 2) in fig. 1). The third ZD connector 29 includes three gigabit ethernet ports, the second network chip 23 outputs four paths of network signals, where three paths of network signals are output to the third ZD connector 29 (marked as the ethernet ports (3-5) in fig. 1), and the other path of network signals (the ethernet port 6) and the network signals (the ethernet port 7) output by the third network chip 30 realize network signal in-board interconnection (marked as the ethernet port 7 and the ethernet port 6 in fig. 1). The fourth ZD connector 311 includes four gigabit ports, and the fourth network chip 31 outputs four network signals to the fourth ZD connector 311 (denoted as ports (8 to 11) in fig. 1).

Specifically, the first ZD connector 21, the second ZD connector 27, the third ZD connector 29, the fourth ZD connector 311, the fifth ZD connector 321, the sixth ZD connector 33, the seventh ZD connector 35, and the eighth ZD connector 41 can all achieve high-demand applications at high data rates, which can be up to 20 or 25 Gbit/s. Preferably the Z-Pack HM-Zd series of connectors from Thailand electronics, Inc.

The first ZD connector 21, the second ZD connector 27, the third ZD connector 29, the fourth ZD connector 311, the fifth ZD connector 321, the sixth ZD connector 33, the seventh ZD connector 35, and the eighth ZD connector 41 are all used for a communication connection test board (not shown), so that PCIE × 4 signals, UART signals, net port signals (net ports (3-5)), net port signals (net ports (8-11)), VGA signals, PCIE × 1 signals, USB signals, and LVDS signals on the main control board are respectively tested through the test board, and further, the related functions of the main control board are verified. On the other hand, the first ZD connector 21, the second ZD connector 27, the third ZD connector 29, the fourth ZD connector 311, the fifth ZD connector 321, the sixth ZD connector 33, the seventh ZD connector 35, and the eighth ZD connector 41 are all used for communication connection with an expansion board (not shown), so that the communication between the PCIE × 4 signal, the UART signal, the network port signal (network ports (3-5)), the network port signal (network ports (8-11)), the VGA signal, the PCIE × 1 signal, the USB signal, and the LVDS signal on the main control board and the expansion board is realized.

It should be noted that the main control board based on the dual Loongson system platform of the present invention includes two hardware platforms (the Loongson general purpose processor and the bridge chip are used to form a system platform, i.e., a Loongson general purpose processor system platform, and the Loongson embedded processor is used to form another system platform, i.e., a Loongson embedded processor system platform), can independently run respective operating systems, and can support a domestic operating system (currently adapted chinese unicorn operating system desktop edition operating system and unicity operating system). The two hardware platforms have independent peripheral interfaces including display interface (VGA signal interface), USB interface, network interface, etc. The Loongson general processor system platform and the Loongson embedded processor system platform are designed into the same main control board, and the Loongson general processor system platform and the Loongson embedded processor system platform are assisted by division of labor, process different service types and improve the integration level of the system. On the other hand, the loongson general processor system platform and the loongson embedded processor system platform respectively and independently run respective operating systems, and the loongson general processor and the loongson embedded processor are respectively connected to different power supplies (not shown), so that the two system platforms can be independently turned on and turned off, and therefore, the two system platforms do not affect each other. That is to say, when the Loongson general-purpose processor system is in shutdown or abnormal and can not work normally, the Loongson embedded processor system can still work normally, and conversely, when the Loongson embedded processor system is in shutdown or abnormal and can not work normally, the Loongson general-purpose processor system can still work normally.

In summary, the present invention provides a main control board based on a dual Loongson system platform, which includes a Loongson general processor, a bridge chip, a Loongson embedded processor, an FPGA, a micro control unit, a first memory chip, a second memory chip, and a third memory chip; the godson general processor is in communication connection with the bridge chip, the godson embedded processor, the FPGA and the micro control unit are in communication connection with the bridge chip, the FPGA and the micro control unit are in communication connection with the godson embedded processor, and the FPGA is in communication connection with the micro control unit; the first memory chip is in communication connection with the Loongson general processor, the second memory chip is in communication connection with the Loongson embedded processor, and the third memory chip is in communication connection with the FPGA. The utility model comprises a Loongson general processor system platform and a Loongson embedded processor system platform, can independently run respective operating systems without mutual interference and support domestic operating systems. And the two system platforms are designed in the same main control board, and can be assisted by division of labor to process different service types, thereby improving the integration level of the system.

As described above, it will be apparent to those skilled in the art that various other changes and modifications can be made based on the technical solution and the technical idea of the present invention, and all such changes and modifications should fall within the protective scope of the appended claims.

Claims

1. A main control board based on a Loongson dual-system platform is characterized by comprising a Loongson general processor (1), a bridge chip (2), a Loongson embedded processor (3), an FPGA (4), a micro control unit (5), a first memory chip (12), a second memory chip (36) and a third memory chip (42);

the Loongson general processor (1) is in communication connection with the bridge chip (2), the Loongson embedded processor (3), the FPGA (4) and the micro control unit (5) are in communication connection with the bridge chip (2), the FPGA (4) and the micro control unit (5) are in communication connection with the Loongson embedded processor (3), and the FPGA (4) is in communication connection with the micro control unit (5);

the first memory chip (12) is in communication connection with the Loongson general processor (1), the second memory chip (36) is in communication connection with the Loongson embedded processor (3), and the third memory chip (42) is in communication connection with the FPGA (4).

2. The Loongson dual-system platform-based main control board of claim 1, wherein the main control board is used for a core control board of ATCA equipment.

3. The Loongson dual-system platform-based master control board according to claim 1, wherein the first memory chip (12), the second memory chip (36), and the third memory chip (42) are onboard memory chips;

the first memory chip (12), the second memory chip (36) and the third memory chip (42) are all DDR memory chips;

the capacity of the first memory chip (12) is 8GB, the capacity of the second memory chip (36) is 4GB, and the capacity of the third memory chip (42) is 4 GB.

4. The Loongson dual-system platform-based main control board as claimed in claim 1, wherein the Loongson general processor (1) and the bridge chip (2) are used to form one system platform, the Loongson embedded processor (3) is used to form another system platform, the two system platforms respectively and independently run respective operating systems, and the Loongson general processor (1) and the Loongson embedded processor (3) are respectively connected to different power supplies, so that the two system platforms can be independently turned on and off.

5. The Loongson dual-system platform-based master control board as claimed in claim 1, wherein the Loongson general processor (1) is an LS3A4000 series chip, the bridge chip (2) is an LS7A1000 series chip, and the Loongson embedded processor (3) is an LS2K1000 series chip.

6. The Loongson dual-system platform-based main control board according to claim 5, wherein the Loongson general processor (1) has a UART port and an SPI port, and the Loongson dual-system platform-based main control board further comprises a debug device (11) communicatively connected with the UART port and an SPI FLASH (13) communicatively connected with the SPI port.

7. The Loongson dual-system platform-based main control board of claim 5, wherein the bridge chip (2) has PCIE x 4 ports, SATA2.0 ports, USB2.0 ports, UART ports and DVO ports;

the number of the PCIE multiplied by 4 ports is three, the number of the SATA2.0 port, the USB2.0 port and the DVO port is one, and the number of the UART ports is four;

the main control board based on the Loongson dual-system platform further comprises a first ZD connector (21), a first network chip (22), a second network chip (23), a first display signal conversion chip (24), a first mSATA slot (25), a USB2.0 interface (26), a second ZD connector (27), a gigabit network port (28), a third ZD connector (29) and a VGA signal interface (241);

the bridge chip (2) is respectively in communication connection with a first ZD connector (21), a first network chip (22) and a second network chip (23) through three PCIE x 4 ports; the first network chip (22) outputs network signals to a gigabit port (28), and the second network chip (23) outputs network signals to a third ZD connector (29);

the first display signal conversion chip (24) is respectively in communication connection with the DVO port and the VGA signal interface (241), and the first display signal conversion chip (24) receives a DVO signal from the DVO port, converts the DVO signal into a VGA signal and outputs the VGA signal to the VGA signal interface (241);

the bridge chip (2) is respectively in communication connection with the FPGA (4), the second ZD connector (27), the micro control unit (5) and the Loongson embedded processor (3) through four UART ports;

the bridge chip (2) is in communication connection with a first mSATA slot (25) through a SATA2.0 port, and the bridge chip (2) is in communication connection with a USB2.0 interface (26) through a USB2.0 port.

8. The Loongson dual-system platform-based master control board according to claim 7, wherein the Loongson embedded processor (3) has PCIE x 4 ports, RGMII ports, DVO ports, PCIE x1 ports, UART ports, SATA ports, and USB2.0 ports;

the main control board based on the Loongson dual-system platform further comprises a third network chip (30), a fourth network chip (31), a fourth ZD connector (311), a second display signal conversion chip (32), a fifth ZD connector (321), a sixth ZD connector (33), a second mSATA slot (34) and a seventh ZD connector (35);

the number of the PCIE x 4 port, the RGMII port, the DVO port, the PCIE x1 port, the SATA port and the USB2.0 port is one, and the number of the UART ports is two;

the Loongson embedded processor (3) is in communication connection with a third network chip (30) through an RGMII port; the third network chip (30) is in communication connection with the second network chip (23), so that the in-board interconnection of network signals output by the bridge chip (2) and the Loongson embedded processor (3) is realized;

the Loongson embedded processor (3) is in communication connection with a fourth network chip (31) through a PCIE x 4 port, and the fourth network chip (31) is in communication connection with a fourth ZD connector (311);

the second display signal conversion chip (32) is respectively in communication connection with the DVO port and the fifth ZD connector (321), and the second display signal conversion chip (32) receives DVO signals from the DVO port, converts the DVO signals into VGA signals and outputs the VGA signals to the fifth ZD connector (321);

the Loongson embedded processor (3) is in communication connection with a sixth ZD connector (33) through a PCIE multiplied by 1 port; the godson embedded processor (3) is respectively in communication connection with the FPGA (4) and the micro control unit (5) through two UART ports; the Loongson embedded processor (3) is in communication connection with a second mSATA slot (34) through a SATA port; and the Loongson embedded processor (3) is in communication connection with a seventh ZD connector (35) through a USB2.0 port.

9. The Loongson dual-system platform-based main control board according to claim 8, further comprising an eighth ZD connector (41), a blower control chip (51), an expansion IO chip (52), and a timing control CPLD chip (53);

the micro control unit (5) is provided with two I2C ports and a UART port;

the micro control unit (5) is respectively in communication connection with a fan control chip (51) and an expansion IO chip (52) through two I2C ports, and the expansion IO chip (52) outputs GPIO signals to a sequential control CPLD chip (53); the micro control unit (5) is in communication connection with the FPGA (4) through a UART port;

the FPGA (4) is provided with an LVDS port, and the FPGA (4) is connected with an eighth ZD connector (41) in a communication mode through the LVDS port.

10. The Loongson dual-system platform-based master control board as claimed in claim 9, wherein the Loongson general processor (1) has a model number LS3A4000-I, the bridge chip (2) has a model number LS7A1000-BA, the Loongson embedded processor (3) has a model number LS2K1000-I, the FPGA (4) has a model number SMQ7K325TFFG676, and the micro control unit (5) has a model number GD32F450IIH 6;

the model of the first display signal conversion chip (24) and the model of the second display signal conversion chip (32) are vibration cores GM71 7123C, the model of the fan control chip (51) is megaly easy to innovate GD32F103C8T6, the model of the expansion IO chip (52) is electronic AW9110B, the model of the time sequence control CPLD chip (53) is a high cloud semiconductor GW1N-UV4LQ1006/I5, the model of the first network chip (22) is network rapid technology WX1860A2, the model of the second network chip (23) is network rapid technology WX1860A4, the model of the third network chip (30) is micro-electronics Yutai 8521SH-CA, and the model of the fourth network chip (31) is network rapid technology WX1860A 4.