CN216958018U - High-reliability lead frame with double Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) - Google Patents

High-reliability lead frame with double Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) Download PDF

Info

Publication number
CN216958018U
CN216958018U CN202122602860.0U CN202122602860U CN216958018U CN 216958018 U CN216958018 U CN 216958018U CN 202122602860 U CN202122602860 U CN 202122602860U CN 216958018 U CN216958018 U CN 216958018U
Authority
CN
China
Prior art keywords
substrate
mosfet
pin
lead frame
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202122602860.0U
Other languages
Chinese (zh)
Inventor
叱晓鹏
习雨攀
潘廷宏
曾陈龙
袁威
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SHENZHEN DIANTONG WINTRONIC MICROELECTRONICS CO Ltd
Original Assignee
SHENZHEN DIANTONG WINTRONIC MICROELECTRONICS CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SHENZHEN DIANTONG WINTRONIC MICROELECTRONICS CO Ltd filed Critical SHENZHEN DIANTONG WINTRONIC MICROELECTRONICS CO Ltd
Priority to CN202122602860.0U priority Critical patent/CN216958018U/en
Application granted granted Critical
Publication of CN216958018U publication Critical patent/CN216958018U/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

The utility model discloses a double-MOSFET high-reliability lead frame, and relates to the technical field of chips. The double-MOSFET high-reliability lead frame comprises a substrate A and a substrate B, wherein an MOSFET chip A and an MOSFET chip B are respectively arranged on the substrate A and the substrate B; the left lower side of the substrate A is connected with a Pin1 Pin through a bonding wire, and the left lower side of the substrate B is connected with a Pin3 Pin through a bonding wire; MOSFET chip A left side is 60 degrees with base plate A's bottom contained angle, MOSFET chip B left side is 60 degrees with base plate B's bottom contained angle. The lead frame provided by the utility model is used for researching and developing an SOP8L double-base-island lead frame, the design is mainly to improve the Pin1 and Pin3 foot parts of the lead frame, the bevel edge design is utilized, the positions of the chip and the edge of the base island are increased on the basis of not influencing the area of the base island and the length of a welding line, and the risk that the glue contaminates the Pin and overflows to the back of the base island is reduced.

Description

High-reliability lead frame with double Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)
Technical Field
The utility model relates to the technical field of chips, in particular to a double-MOSFET high-reliability lead frame.
Background
The MOSFET is a Metal-Oxide-semiconductor field Effect Transistor (MOSFET), which is called a Metal-Oxide-semiconductor field Effect Transistor (MOSFET) for short, and is a MOSFET that can be widely used in analog circuits and digital circuits. With the popularization of the Type-C interface, the MOSFET plays an important role in power conversion and overload protection, and the quick-charging interface uniformly drives the MOSFET to develop; in addition, the MOSFET is a core part of a driving control system of an electric automobile and a charging pile power supply module, in recent years, with the development of the Internet of things and an electric automobile, the proportion of automobile electrons is increased, the industrial demand is rapidly increased, and power elements such as the MOSFET also meet short-term outbreak.
I know MOSFET product adopts SOP8L double-base island double-chip mode, contains 2 MOSFET chips. An important parameter of MOSFET products is the on-resistance, which is the amount of energy dissipated when current flows between the D and S electrodes of the MOSFET chip, which is called the on-loss. For the packaging process, the reduction of the on-resistance can be controlled by reducing the length of the bonding wire between the S pole and the pin, i.e. the closer the chip is to the base island of the lead frame, the better. The above process requirements bring additional quality risks, and when the chip is closer to the lead frame base island, the more easily the chip is stuck, the more easily the glue and the pin are contaminated and short-circuited, and the glue overflows to the back of the base island to cause the problem of reduction of the reliability of subsequent products; in addition, the chip is close to the edge of the base island, so that the whole structure of the packaged product is deviated to one side, the thermal expansion effect during reflow soldering of the product is influenced, and the delamination resistance of the whole product is reduced.
SUMMERY OF THE UTILITY MODEL
The present invention is directed to a dual MOSFET high reliability lead frame to solve the above problems in the related art.
In order to achieve the purpose, the utility model provides the following technical scheme: a double-MOSFET high-reliability lead frame comprises a substrate A and a substrate B, wherein an MOSFET chip A and an MOSFET chip B are respectively arranged on the substrate A and the substrate B;
a Pin8 Pin and a Pin7 Pin are respectively arranged above the substrate A from left to right, and a Pin6 Pin and a Pin5 Pin are respectively arranged above the substrate B from left to right;
the left lower side of the substrate A is connected with a Pin1 Pin through a bonding wire, and the left lower side of the substrate B is connected with a Pin3 Pin through a bonding wire;
MOSFET chip A left side is 60 degrees with base plate A's bottom contained angle, MOSFET chip B left side is 60 degrees with base plate B's bottom contained angle.
Preferably, the lower left corner of the substrate a is designed to be a bevel edge shape, and one side of the Pin1 corresponding to the substrate a is also designed to be a bevel edge;
the lower left corner of the substrate B is designed to be a bevel edge shape, and one side of the Pin3 Pin corresponding to the substrate B is also designed to be a bevel edge.
Preferably, the MOSFET chip a and the MOSFET chip B are provided at the center positions of the substrate a and the substrate B, respectively.
Preferably, a groove A is formed in a space between the substrate A and a Pin1 Pin, and a groove B is formed in a space between the substrate B and a Pin3 Pin;
the grooves A and B are both formed by two V-shapes.
Preferably, the distance between the MOSFET chip A and the edge of the substrate A is controlled to be 400 micrometers, and the distance between the MOSFET chip B and the edge of the substrate B is controlled to be 400 micrometers.
Compared with the prior art, the utility model has the beneficial effects that:
(1) according to the double-MOSFET high-reliability lead frame, the Pin1 Pin and the Pin3 Pin are designed into a bevel edge form, the base island A and the base island B are also designed into a bevel edge form, the Pin1 Pin is designed into a bevel edge form which is cut into the edge of the base island A, the Pin3 Pin is designed into a bevel edge form which is cut into the edge of the base island B, and the design can guarantee the chip bearing capacity of the base island A and the base island B of the original lead frame.
(2) According to the double-MOSFET high-reliability lead frame, the Pin1 Pin and the Pin3 Pin are designed into a bevel edge form, so that the areas of the pins of the Pin1 Pin and the Pin3 Pin are increased and are close to the positions of the base island A and the base island B, the distances between the Pin1 Pin and the Pin3 Pin and the distance between the Pin1 Pin and the MOSFET chip A and the distance between the Pin3 Pin and the MOSFET chip B are kept unchanged from the original distances, and therefore the parameters of the on-resistance are guaranteed to be unchanged.
(3) This two MOSFET high reliability lead frame, MOSFET chip A and MOSFET chip B rotate 60 degrees and remove respectively to base island A and base island B central point and put, and whole product structure overall arrangement is more reasonable, and thermal expansion effect influences when having reduced product reflow soldering improve the anti layering ability of product.
(4) According to the double-MOSFET high-reliability lead frame, the groove A and the groove B form a local V-shaped embedded structure, and when a plastic package material is injected, a lock catch type structure is formed, so that the bonding strength of the island part and the plastic package body part is enhanced, and the anti-layering capability of the whole product is further enhanced.
(5) According to the double-MOSFET high-reliability lead frame, the distance between the MOSFET chip and the edge of the base island is increased to 400 micrometers from original 200 micrometers, the contamination risk of glue of a product is reduced, and the short circuit risk of the glue of the chip is reduced.
Drawings
FIG. 1 is a schematic diagram of an original lead frame structure;
fig. 2 is a lead frame structure of the present invention.
In the figure: 1 a base island A; 2. a base island B; 3, a MOSFET chip A; 4 MOSFET chip B; pin5 Pin 1; pin6 Pin 3; 7, welding wires; 8, groove A; 9 groove B.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-2, the present invention provides a technical solution: the utility model provides a two MOSFET high reliability lead frames, includes base plate A1 and base plate B2, be provided with MOSFET chip A3 and MOSFET chip B4 on base plate A1 and the base plate B2 respectively, the top of base plate A1 is provided with Pin8 position and Pin7 position from left to right respectively, the top of base plate B2 is provided with Pin6 position and Pin5 position from left to right respectively, the left downside of base plate A1 is connected with Pin1 position 5 through bonding wire 7, the left downside of base plate B2 is connected with Pin3 position 6 through bonding wire 7, MOSFET chip A3 left side and base plate A1's bottom contained angle is 60 degrees, MOSFET chip B4 left side and base plate B2's bottom contained angle is 60 degrees.
Furthermore, the lower left corner of the substrate a1 is designed to be a bevel edge, and one side of the Pin1 Pin5 corresponding to the substrate a1 is also designed to be a bevel edge, the lower left corner of the substrate B2 is designed to be a bevel edge, and one side of the Pin3 Pin6 corresponding to the substrate B2 is also designed to be a bevel edge.
Pin1 Pin5 and Pin3 Pin6 are designed into a bevel edge form, a base island A1 and a base island B2 are also designed into a bevel edge form, a Pin1 Pin5 is designed into a bevel edge form which is cut into the edge of a base island A1, and a Pin3 Pin6 is designed into a bevel edge form which is cut into the edge of a base island B2, so that the design can ensure the chip carrying capacity of the base island A and the base island B of the original lead frame, the Pin1 Pin5 and the Pin3 Pin6 are designed into a bevel edge form, the Pin1 Pin5 and the Pin3 Pin6 are enlarged in area and are close to the positions of the base island A1 and the base island B2, the distances between the Pin1 Pin5 and the Pin3 Pin6 and a MOSFET chip A3 and a MOSFET chip B4 are respectively kept unchanged, and the on-resistance parameters are further ensured to be unchanged.
Further, the MOSFET chip A3 and the MOSFET chip B4 are disposed at the center of the substrate a1 and the substrate B2, respectively.
MOSFET chip A3 and MOSFET chip B4 rotate 60 degrees and move to base island A1 and base island B2 central point respectively and put, and whole product structure layout is more reasonable, has reduced the thermal expansion effect influence when the product reflow soldering, improves the anti layering ability of product.
Furthermore, a space between the substrate A1 and the Pin1 Pin5 forms a groove A8, a space between the substrate B2 and the Pin3 Pin6 forms a groove B9, and the groove A8 and the groove B9 are both formed by two V-shaped structures.
The groove A8 and the groove B9 form a local V-shaped embedded structure, and when plastic package materials are injected, a lock catch type structure is formed, so that the bonding strength of the base island part and the plastic package body part is enhanced, and the anti-layering capability of the whole product is further enhanced.
Further, the distance between the edge of the MOSFET chip A3 and the edge of the substrate A1 is controlled to be 400 micrometers, and the distance between the edge of the MOSFET chip B4 and the edge of the substrate B2 is controlled to be 400 micrometers.
The distance between the MOSFET chip and the edge of the base island is increased from 200 micrometers to 400 micrometers, the contamination risk of glue of the product is reduced, and the short circuit risk of the glue of the chip is reduced
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the utility model, the scope of which is defined in the appended claims and their equivalents.

Claims (5)

1. A double MOSFET high reliability lead frame comprises a substrate A (1) and a substrate B (2), and is characterized in that: the substrate A (1) and the substrate B (2) are respectively provided with an MOSFET chip A (3) and an MOSFET chip B (4);
a Pin8 Pin and a Pin7 Pin are respectively arranged above the substrate A (1) from left to right, and a Pin6 Pin and a Pin5 Pin are respectively arranged above the substrate B (2) from left to right;
the left lower side of the substrate A (1) is connected with a Pin1 Pin (5) through a bonding wire (7), and the left lower side of the substrate B (2) is connected with a Pin3 Pin (6) through a bonding wire (7);
MOSFET chip A (3) left side is 60 degrees with the bottom contained angle of base plate A (1), MOSFET chip B (4) left side is 60 degrees with the bottom contained angle of base plate B (2).
2. The dual MOSFET high reliability leadframe of claim 1, wherein: the lower left corner of the substrate A (1) is designed to be in a bevel edge shape, and one side, corresponding to the substrate A (1), of the Pin1 Pin (5) is also designed to be in a bevel edge shape;
the lower left corner of the substrate B (2) is designed to be a bevel edge shape, and one side of the Pin3 Pin (6) corresponding to the substrate B (2) is also designed to be a bevel edge.
3. The dual MOSFET high reliability leadframe of claim 1, wherein: the MOSFET chip A (3) and the MOSFET chip B (4) are respectively arranged at the central positions of the substrate A (1) and the substrate B (2).
4. The dual MOSFET high reliability leadframe of claim 1, wherein: a groove A (8) is formed in a space between the substrate A (1) and a Pin1 Pin (5), and a groove B (9) is formed in a space between the substrate B (2) and a Pin3 Pin (6);
the groove A (8) and the groove B (9) are both formed by two V-shaped grooves.
5. The dual MOSFET high reliability leadframe of claim 1, wherein: the distance between the edges of the MOSFET chip A (3) and the substrate A (1) is controlled to be 400 micrometers, and the distance between the edges of the MOSFET chip B (4) and the substrate B (2) is controlled to be 400 micrometers.
CN202122602860.0U 2021-10-28 2021-10-28 High-reliability lead frame with double Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) Active CN216958018U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202122602860.0U CN216958018U (en) 2021-10-28 2021-10-28 High-reliability lead frame with double Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202122602860.0U CN216958018U (en) 2021-10-28 2021-10-28 High-reliability lead frame with double Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)

Publications (1)

Publication Number Publication Date
CN216958018U true CN216958018U (en) 2022-07-12

Family

ID=82303497

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202122602860.0U Active CN216958018U (en) 2021-10-28 2021-10-28 High-reliability lead frame with double Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)

Country Status (1)

Country Link
CN (1) CN216958018U (en)

Similar Documents

Publication Publication Date Title
US9520345B2 (en) Semiconductor module, semiconductor device having semiconductor module, and method of manufacturing semiconductor module
US10453946B2 (en) Semiconductor device and an electronic device
US9881812B2 (en) Power module and fabrication method for the same
US8669650B2 (en) Flip chip semiconductor device
US8884411B2 (en) Semiconductor device and manufacturing method thereof
CN102655140B (en) Multi-die package
US9153563B2 (en) Electronic device
US8299620B2 (en) Semiconductor device with welded leads and method of manufacturing the same
US9847311B2 (en) Semiconductor device and manufacturing method for the semiconductor device
JPWO2018186353A1 (en) Power module
JP6512231B2 (en) Semiconductor device
JPWO2013133134A1 (en) Semiconductor device and manufacturing method thereof
CN205984966U (en) Big current power semiconductor device's packaging structure
CN103824834A (en) Semiconductor device with improved package structure and manufacturing method of semiconductor device
US9437587B2 (en) Flip chip semiconductor device
US6689642B2 (en) Semiconductor device and manufacturing method thereof
CN216958018U (en) High-reliability lead frame with double Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)
JP6691984B2 (en) Power module
JP7002645B2 (en) Power semiconductor devices, their manufacturing methods, and power conversion devices
CN110164832A (en) High-current semiconductor power device
US20210308791A1 (en) Joint structure, semiconductor device, and joining method
CN203733785U (en) Semiconductor device with improved package structure
WO2022218031A1 (en) Packaging structure for power semiconductor device
CN111725174A (en) DFN5 x 6 double-base island chip packaging structure
CN107978530B (en) Method for reducing injection molding flash of IPM module and DBC substrate

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant