CN216795364U

CN216795364U - Test packaging circuit board

Info

Publication number: CN216795364U
Application number: CN202123241653.3U
Authority: CN
Inventors: 张敬贺; 齐利克
Original assignee: Goertek Microelectronics Inc
Current assignee: Goertek Microelectronics Inc
Priority date: 2021-12-21
Filing date: 2021-12-21
Publication date: 2022-06-21
Anticipated expiration: 2031-12-21

Abstract

The application discloses a test package circuit board, which is used for packaging test of an ASIC chip in an MEMS microphone, and is provided with a first surface and a second surface which are oppositely arranged, wherein the first surface is provided with a plurality of first bonding pads and second bonding pads, the first bonding pads can correspond to ports of the ASIC chip of at least two different types, and the second bonding pads are used for welding a capacitor; the second surface is equipped with a plurality of third pads, and is a plurality of the third pad is used for connecting outside test fixture. This application is provided with a plurality of first pads and second pad on the first surface of circuit board to a plurality of first pads can correspond the port of the ASIC chip of two kind at least different grade types, integrate multiple ASIC design on same circuit, guarantee to be suitable for different types of ASIC chip encapsulation on the same circuit board, can carry out the volume production encapsulation, reduce the encapsulation cost, it is more convenient to use, can satisfy different test demands.

Description

Test packaging circuit board

Technical Field

The application relates to the technical field of chip packaging, in particular to a test packaging circuit board.

Background

In the existing packaging test process of an ASIC chip in a microphone, one ASIC chip generally corresponds to one PCB (circuit board), and a soldering probe is required to test when the ASIC chip is used. Therefore, the existing ASIC chip only supports single package in the packaging test process, and cannot be produced in batch, so that the cost is high.

SUMMERY OF THE UTILITY MODEL

An object of this application is to provide a new technical scheme of test encapsulation circuit board, can solve a problem that ASIC chip corresponds a section circuit board among the prior art at least.

The application provides a test package circuit board, which is used for packaging test of an ASIC chip in an MEMS microphone, the circuit board is provided with a first surface and a second surface which are oppositely arranged, the first surface is provided with a plurality of first bonding pads and second bonding pads, wherein the first bonding pads can correspond to ports of the ASIC chip with at least two different types, and the second bonding pads are used for welding a capacitor; the second surface is provided with a plurality of third bonding pads, and a plurality of third bonding pads are used for connecting an external test tool.

Optionally, the cross section of the circuit board is square, and the first pad includes: the first VDD pad, the first DATA pad, the first CLK pad, the first L/R pad and the first GND pad are arranged at intervals along the length direction on a first long side close to the first surface of the circuit board.

Optionally, the first pad further includes: the circuit board comprises a first SUB bonding pad, a first MIC bonding pad, a first INN bonding pad and a first INP bonding pad, wherein the first SUB bonding pad, the first MIC bonding pad, the first INN bonding pad and the first INP bonding pad are distributed on a second long edge of the first surface close to the circuit board at intervals along the length direction.

Optionally, the first pad further includes: the first VMIC pad, the second INP pad, the second INN pad and the second MIC pad are close to the first short side of the first surface of the circuit board and are arranged at intervals along the width direction.

Optionally, the first pad further includes: a third MIC pad arranged in-line with the second MIC pad.

Optionally, the number of the second pads is two, and the two second pads are arranged on a second long edge close to the first surface of the circuit board and spaced apart from each other along the length direction of the circuit board, so as to be used for soldering one capacitor.

Optionally, the number of the second pads is four, and the four second pads are arranged on the second long edge close to the circuit board and spaced apart from each other along the length direction of the circuit board, so as to be used for soldering the two capacitors.

Optionally, the third pad includes: the second VDD pad, the second DATA pad, the second CLK pad, the second L/R pad and the second GND pad are arranged at intervals along the length direction on a first long side close to the second surface of the circuit board.

Optionally, the third pad further includes: second SUB pad, fourth MIC pad, third INN pad, third INP pad and second VMIC pad, the second SUB pad, fourth MIC pad, third INN pad, third INP pad and the second VMIC pad is being close to the circuit board the second strip long side of second surface is along length direction interval distribution.

Optionally, a first circuit connection layer and a second circuit connection layer are disposed between the first surface and the second surface, the first circuit connection layer is close to the first surface, and the second circuit connection layer is close to the second surface.

According to the test packaging circuit board provided by the embodiment of the utility model, the first surface of the circuit board is provided with the plurality of first bonding pads and the plurality of second bonding pads, the plurality of first bonding pads can correspond to ports of ASIC chips of at least two different types, and a plurality of ASIC designs are integrated on the same circuit handle, so that the same circuit board is suitable for packaging different types of ASIC chips, the mass production packaging can be carried out, the packaging cost is reduced, the use is more convenient, and different test requirements can be met.

Further features of the present application and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which is to be read in connection with the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the application and together with the description, serve to explain the principles of the application.

FIG. 1 is a schematic structural diagram of a first surface of a test package circuit board according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a second surface of a test package circuit board according to an embodiment of the utility model;

FIG. 3 is a schematic structural diagram of a first circuit connection layer of a test package circuit board according to an embodiment of the utility model;

fig. 4 is a schematic diagram of a second circuit connection layer of the test package wiring board according to the embodiment of the utility model.

Reference numerals:

a wiring board 10;

a first VDD pad 21; a first DATA pad 22; a first CLK pad 23; a first L/R pad 24; a first GND pad 25;

a first SUB pad 31; a first MIC pad 32; a first INN pad 33; a first INP pad 34;

a first VMIC pad 41; a second INP pad 42; a second INN pad 43; a second MIC pad 44; a third MIC pad 45;

a second pad 50;

a second VDD pad 61; a second DATA pad 62; a second CLK pad 63; a second L/R pad 64; a second GND pad 65;

the second SUB pad 71; a fourth MIC pad 72; a third INN pad 73; a third INP pad 74; a second VMIC pad 75;

the first line connection layer 81; a second line connection layer 82.

Detailed Description

Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present application unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the application, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

The test package wiring board 10 according to the embodiment of the present invention will be described in detail below with reference to the drawings.

As shown in fig. 1 and 2, according to the test package wiring board 10 of the embodiment of the present invention, the wiring board 10 has a first surface and a second surface which are oppositely arranged, and the first surface is provided with a plurality of first pads and second pads 50.

Specifically, the plurality of first pads can correspond to ports of at least two different types of ASIC chips, and the plurality of second pads 50 are used for bonding capacitance. The second surface is equipped with a plurality of third pads, and a plurality of third pads are used for connecting outside test fixture.

In other words, the test package wiring board 10 according to the embodiment of the present invention is mainly used for a package test of an ASIC chip (ASIC) in a MEMS microphone. The wiring board 10 is referred to as a Printed circuit board { Printed circuit boards }, or a Printed circuit board. The test package circuit board 10 can be suitable for side-mounted testing of various MIC ASIC designs. For example, different types of ASIC chips such as digital ASICs and analog ASICs.

Referring to fig. 1 and 2, the test package wiring board 10 has a first surface and a second surface disposed opposite to each other, the first surface being provided with a plurality of first pads and second pads 50. The plurality of first and second pads 50 may have different functions in order to meet the test requirements of different kinds of ASIC chips. The plurality of first pads can correspond to ports of at least two different types of ASIC chips, and the ASIC chips can be attached to the circuit board 10 during a process of testing the package, and different port pins to be tested on the ASIC chips are punched on the corresponding first pads and/or the second pads 50. Through designing a plurality of different kinds of pads (first pad and second pad 50), can satisfy the design of different kinds (digital, simulation ASIC is general) ASIC chip, be convenient for carry out the volume production encapsulation, reduce the encapsulation cost, it is more convenient to use, can satisfy different test demands.

The plurality of second pads 50 can be used for bonding capacitance. The plurality of second pads 50 may function instead of MEMS, and the plurality of second pads 50 can be equivalent to MEMS. Those skilled in the art can understand that in the MEMS microphone, the MEMS chip is equivalent to a capacitor, and is not described in detail in this application.

It should be noted that, in the process of testing the package in the prior art, the volume of the package circuit board 10 is large, and is usually 3 × 3 cm. The packaged circuit board 10 is placed in a large test fixture for package testing. Therefore, the conventional package wiring board 10 only supports a single package, and cannot be mass-produced, which results in high cost. And this application can design test package circuit board 10 into 4 x 3mm through the small-size test fixture of corresponding design, and the size of circuit board 10 is unanimous (4 x 3mm) with ASIC chip size, has greatly reduced the volume of circuit board 10.

The second surface of the test package circuit board 10 is provided with a plurality of third bonding pads, and the plurality of third bonding pads are mainly used for connecting an external test tool to realize the package test of the ASIC chip.

Therefore, according to the test package circuit board 10 provided by the embodiment of the utility model, the plurality of first bonding pads and the plurality of second bonding pads 50 are arranged on the first surface of the circuit board 10, and the plurality of first bonding pads can correspond to ports of at least two different types of ASIC chips, and a plurality of ASIC designs are integrated on the same circuit handle, so that the same circuit board 10 is suitable for packaging different types of ASIC chips, the mass production package can be carried out, the package cost is reduced, the use is more convenient, and different test requirements can be met.

According to one embodiment of the present invention, the cross section of the wiring board 10 is square, and the first pad includes: the first VDD pad 21, the first DATA pad 22, the first CLK pad 23, the first L/R pad 24, and the first GND pad 25 are arranged at intervals in the length direction on the first long side close to the first surface of the wiring board 10, the first VDD pad 21, the first DATA pad 22, the first CLK pad 23, the first L/R pad 24, and the first GND pad 25.

That is, as shown in fig. 1, the cross section of the wiring board 10 may be designed in a square shape, the first pad having the first VDD pad 21, the first DATA pad 22, the first CLK pad 23, the first L/R pad 24, and the first GND pad 25. Wherein the first VDD pad 21, the first DATA pad 22, the first CLK pad 23, the first L/R pad 24, and the first GND pad 25 are vertically arranged on the first surface of the circuit board 10 on a side close to the first long side. The number of the first DATA pads 22 is two, and the first CLK pad 23 is disposed between the two first DATA pads 22. In the application, corresponding pins on the digital ASIC can be punched on the first VDD pad 21, the first DATA pad 22, the first CLK pad 23, the first L/R pad 24 and the first GND pad 25 to be electrically connected with the lines, so as to realize the package test of the digital ASIC. Of course, in the present application, it is understood by those skilled in the art that specific meanings and principles of VDD representing the device operating voltage, CLK representing the clock signal, DATA representing the DATA pin, L/R representing the channel selection, and GND representing the ground are not described in detail in the present application.

According to an embodiment of the present invention, the first pads further include a first SUB pad 31, a first MIC pad 32, a first INN pad 33, a first INP pad 34, and a first VMIC pad 41, and the first SUB pad 31, the first MIC pad 32, the first INN pad 33, the first INP pad 34, and the first VMIC pad 41 are distributed at intervals in a length direction on a second long side close to the first surface of the wiring board 10.

In other words, referring to fig. 1, the first pads may further include a first SUB pad 31, a first MIC pad 32, a first INN pad 33, and a first INP pad 34, wherein the first SUB pad 31, the first MIC pad 32, the first INN pad 33, and the first INP pad 34 are vertically arranged on the second long side of the first surface of the circuit board 10. Some of the first SUB pad 31, first MIC pad 32, first INN pad 33, and first INP pad 34 can be used to emulate an ASIC, e.g., first MIC pad 32, etc. The SUB bonding pad can conveniently match MEMS (Micro-Electro-Mechanical System), INN and INP represent input terminal, wherein the INP bonding pad is used for the ASIC chip of single-ended input, and the INN bonding pad is used for the ASIC chip of differential input, is convenient for be suitable for different types of ASIC chip encapsulation on same circuit board 10, can carry out volume production encapsulation, reduces the encapsulation cost, and it is more convenient to use, can satisfy different test demands. In the present application, SUB, MIC, INN, INP, VMIC, etc. are all technical names well known to those skilled in the art, and detailed description thereof is omitted.

According to an embodiment of the present invention, referring to fig. 1, the first pads may further include first VMIC pads 41, second INP pads 42, second INN pads 43, and second MIC pads 44, wherein the first VMIC pads 41, the second INP pads 42, the second INN pads 43, and the second MIC pads 44 are arranged at intervals in the width direction on the first short side close to the first surface of the wiring board 10. The first pad may further include: a third MIC pad 45, the third MIC pad 45 being arranged in-line with the second MIC pad 44. The MIC and VMIC PADs may be used for measuring voltage bias, and the design of multiple PADs (PADs) at multiple positions on the first surface of the circuit board 10 may be used for package testing of different types of ASIC chips, so as to effectively reduce the cost and facilitate package testing of various AC/DC signals.

According to an embodiment of the present invention, the number of the second pads 50 is two, and two second pads 50 are disposed on the second long side close to the first surface of the wiring board 10 and spaced apart along the length direction of the wiring board 10 for soldering a capacitor.

That is, the number of the second pads 50 may be two, and the two pads are mainly applied to the single-ended input ASIC type. Two second pads 50 are provided on the first surface of the wiring board 10 at positions close to the second long side, and the two second pads 50 are arranged at intervals along the length direction of the wiring board 10, the two second pads 50 can be used for welding a capacitor, mainly for replacing the MEMS, so that the ASIC chip can simulate a test conclusion under the result of the MEMS.

In some embodiments of the present invention, as shown in fig. 1, the number of the second pads 50 is four, and the present invention is mainly applied to an ASIC type of differential input. Four second pads 50 are disposed on the second long side of the circuit board 10 and spaced along the length of the circuit board 10 for soldering two capacitors, which facilitates the simulation of the ASIC chip to test results under the MEMS results. In the present application, the cross-sectional area of each second pad 50 is larger than the cross-sectional area of each first pad, facilitating the soldering of the capacitor.

According to an embodiment of the present invention, as shown in fig. 2, the third pads include a second VDD pad 61, a second DATA pad 62, a second CLK pad 63, a second L/R pad 64, and a second GND pad 65, the second VDD pad 61, the second DATA pad 62, the second CLK pad 63, the second L/R pad 64, and the second GND pad 65 are disposed on the first long side near the second surface of the wiring board 10, and the second VDD pad 61, the second DATA pad 62, the second CLK pad 63, the second L/R pad 64, and the second GND pad 65 are arranged spaced apart in the length direction.

The third pad further includes: the second SUB pad 71, the fourth MIC pad 72, the third INN pad 73, the third INP pad 74 and the second VMIC pad 75, and the second SUB pad 71, the fourth MIC pad 72, the third INN pad 73, the third INP pad 74 and the second MIC pad 44 are spaced apart along the length direction on the second long side close to the second surface of the wiring board 10. The second surface of the circuit board 10 is designed with 10 PADs (PAD) corresponding to the PADs on the first surface, and the PADs on the second surface of the circuit board 10 are used for connecting an external test tool to realize the package test of the ASIC chip.

According to an embodiment of the present invention, as shown in fig. 3 and 4, a first circuit connection layer 81 and a second circuit connection layer 82 are disposed between the first surface and the second surface, the first circuit connection layer 81 is close to the first surface, and the circuit design of the first circuit connection layer 81 corresponds to the layout position of the plurality of pads on the first surface. The second line connection layer 82 is close to the second surface, and the line design of the second line connection layer 82 corresponds to the layout position of the third pads on the second surface. The pads on the first surface and the pads on the second surface of the wiring board 10 are electrically connected through the first wiring connection layer 81 and the second wiring connection layer 82.

In summary, the test package circuit board 10 according to the embodiment of the present invention has a smaller volume, and a plurality of first pads and second pads 50 are disposed on the first surface of the circuit board 10, and the plurality of first pads can correspond to ports of at least two different types of ASIC chips, and a plurality of ASIC designs are integrated on the same circuit handle, so that it is ensured that different types of ASIC chips are suitable for packaging on the same circuit board 10, and the test package circuit board can be packaged in mass production, reduce the packaging cost, is more convenient to use, and can meet different test requirements.

Of course, other structures of the test package wiring board 10 and its operating principles are understood and appreciated by those skilled in the art and will not be described in detail herein.

Although some specific embodiments of the present application have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present application. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the present application. The scope of the application is defined by the appended claims.

Claims

1. A test package wiring board (10) for package testing of ASIC chips in MEMS microphones, characterized in that the wiring board (10) has a first surface and a second surface arranged opposite to each other, the first surface being provided with a plurality of first pads and second pads, wherein the plurality of first pads can correspond to ports of at least two different types of ASIC chips, and the plurality of second pads are used for soldering capacitors; the second surface is provided with a plurality of third bonding pads, and a plurality of third bonding pads are used for connecting an external test tool.

2. The test package wiring board (10) of claim 1, wherein the cross-section of the wiring board (10) is square, and the first pad comprises: a first VDD pad (21), a first DATA pad (22), a first CLK pad (23), a first L/R pad (24), and a first GND pad (25), the first VDD pad (21), the first DATA pad (22), the first CLK pad (23), the first L/R pad (24), and the first GND pad (25) being arranged at intervals in a length direction on a first long side close to the first surface of the wiring board (10).

3. The test package wiring board (10) of claim 2, wherein the first pad further comprises: first SUB pad (31), first MIC pad (32), first INN pad (33) and first INP pad (34), first SUB pad (31), first MIC pad (32), first INN pad (33) and first INP pad (34) are close to the second strip length side of the first surface of circuit board (10) along length direction spaced apart distribution.

4. The test package wiring board (10) of claim 2, wherein the first pad further comprises: a first VMIC pad (41), a second INP pad (42), a second INN pad (43) and a second MIC pad (44), the first VMIC pad (41), the second INP pad (42), the second INN pad (43) and the second MIC pad (44) being arranged close to the first short side of the first surface of the wiring board (10) at intervals in the width direction.

5. The test package wiring board (10) of claim 4, wherein the first pad further comprises: a third MIC pad (45), the third MIC pad (45) being arranged in a same row as the second MIC pad (44).

6. The test package wiring board (10) of claim 1, wherein the number of the second pads is two, and two of the second pads are provided on a second long side near the first surface of the wiring board (10) and are spaced apart along a length direction of the wiring board (10) for soldering one of the capacitors.

7. The test package wiring board (10) of claim 1, wherein the number of the second pads is four, and four of the second pads are provided on a second long side close to the wiring board (10) and spaced apart along a length direction of the wiring board (10) for soldering two of the capacitors.

8. The test package wiring board (10) of claim 1, wherein the third pads comprise: a second VDD pad (61), a second DATA pad (62), a second CLK pad (63), a second L/R pad (64), and a second GND pad (65), the second VDD pad (61), the second DATA pad (62), the second CLK pad (63), the second L/R pad (64), and the second GND pad (65) being arranged at intervals in a length direction on a first long side close to the second surface of the wiring board (10).

9. The test package wiring board (10) of claim 8, wherein the third pad further comprises: second SUB pad (71), fourth MIC pad (72), third INN pad (73), third INP pad (74) and second VMIC pad (75), second SUB pad (71), fourth MIC pad (72), third INN pad (73), third INP pad (74) and second VMIC pad (75) are close to circuit board (10) the second strip long side of second surface is along length direction spaced apart distribution.

10. The test package wiring board (10) of claim 1, wherein a first circuit connection layer (81) and a second circuit connection layer (82) are disposed between the first surface and the second surface, the first circuit connection layer (81) being adjacent to the first surface, the second circuit connection layer (82) being adjacent to the second surface.