CN216721168U - Time delay anti-shake circuit and electronic equipment - Google Patents
Time delay anti-shake circuit and electronic equipment Download PDFInfo
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- CN216721168U CN216721168U CN202122690608.XU CN202122690608U CN216721168U CN 216721168 U CN216721168 U CN 216721168U CN 202122690608 U CN202122690608 U CN 202122690608U CN 216721168 U CN216721168 U CN 216721168U
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Abstract
The application provides a time delay anti-shake circuit and electronic equipment has related to power technical field, has solved present circuit voltage jitter, leads to the problem of great surge easily, include: the voltage detection circuit comprises a signal detection end, a voltage detection circuit and a voltage detection circuit, wherein the signal detection end is used for providing a voltage detection signal; the device comprises a voltage stabilizing module, a voltage storage module, a first switch module and a second switch module. This application appears the short circuit in the circuit and resumes or appear contact failure again and when leading to the problem of voltage shake, through voltage stabilizing module and the one-way delay transmission of voltage storage module control voltage detection signal, through first switch module and the locking of second switch module with time delay anti-shake circuit, time delay a period, finish until surge voltage release, the locking of release time delay anti-shake circuit again, thereby reduce the harm of surge voltage to the circuit, effectively reduce the probability that surge current leads to the circuit damage.
Description
Technical Field
The application relates to the technical field of power supplies, in particular to a time-delay anti-shake circuit and electronic equipment.
Background
Existing electrical devices, control boxes, etc. have an input interface, such as a power input interface or an electrical connection interface of a male plug and a female plug, which is directly electrically connected to a driving board through the input interface.
Some equipment at present avoid the drive plate when carrying out the hot plug and insert, the very big surge current of drive plate input appearance leads to the circuit to damage, can set up a hot plug circuit at input interface, with the surge current at control input interface, with the protection drive plate, but current partial hot plug circuit is in the use, when signal output part short circuit resumes again, or power input end appears the contact or when pulling out the bad condition of inserting and leading to appearing the voltage shake, all still can lead to appearing great surge in the hot plug circuit, damage components and parts in the hot plug circuit easily.
SUMMERY OF THE UTILITY MODEL
The application provides a can reduce surge current and lead to the probability that the circuit damaged when inserting the power, reduce the condition that great surge appears in the hot plug circuit, improve circuit reliability's time delay anti-shake circuit and electronic equipment.
In one aspect, the present application provides a delay anti-jitter circuit, including:
in one possible implementation manner of the present application, the voltage regulator comprises a signal detection terminal, a voltage stabilization module, a voltage storage module, a first switch module and a second switch module,
the signal detection end is used for providing a voltage detection signal in the time delay anti-shake circuit;
the voltage stabilizing module is electrically connected with the signal detection end and is used for controlling the voltage detection signal to perform unidirectional transmission to the first switch module and the voltage storage module;
the voltage storage module is electrically connected with the voltage stabilizing module and is used for storing and releasing the voltage detection signal;
the first switch module is electrically connected with the voltage stabilizing module and the voltage storage module, and is used for controlling the on-off of the second switch module according to the voltage value of the voltage detection signal and a preset delay starting voltage value;
and the second switch module is electrically connected with the first switch module and the voltage stabilizing module and is used for controlling the on-off of the time-delay anti-shake circuit.
In one possible implementation manner of the present application, the voltage stabilizing module includes a voltage stabilizing diode, an anode of the voltage stabilizing diode is electrically connected to the signal detection terminal, and a cathode of the voltage stabilizing diode is electrically connected to the voltage storage module and the first switch module.
In one possible implementation manner of the present application, the voltage storage module includes a storage capacitor, one end of the storage capacitor is electrically connected to a negative electrode of the zener diode, and the other end of the storage capacitor is grounded.
In a possible implementation manner of the present application, the first switch module includes a fourth resistor, a fifth resistor, a sixth resistor, and a second triode, an emitter of the second triode is electrically connected to an electrical connection point of one end of the storage capacitor and a negative electrode of the zener diode, a collector of the second triode is electrically connected to one end of the fourth resistor, the other end of the fourth resistor is grounded through the fifth resistor, and a base of the second triode is electrically connected to the second switch module through the sixth resistor.
In a possible implementation manner of the present application, the second switch module includes a third resistor and a third triode, a base of the third triode is electrically connected to an electrical connection point of the fourth resistor and the fifth resistor, a collector of the third triode is electrically connected to the signal detection end through the third resistor, and an emitter of the third triode is grounded.
In one possible implementation manner of the present application, the delay anti-shake circuit further includes:
a power input terminal and a power output terminal;
the signal detection end is electrically connected with a detection module and used for outputting a first control signal, and generating the voltage detection signal at the signal detection end according to the voltage value of the first control signal and the preset voltage value range of the first control signal so as to control the on-off between the power input end and the power output end.
In a possible implementation manner of the present application, the detection module is electrically connected to a start module, and the start module is electrically connected to the power input end and the power output end, and is configured to output a constant current signal of a preset current value to charge the power output end.
In a possible implementation manner of the present application, the detection module is electrically connected to a switch module, and is electrically connected to the power input terminal, the power output terminal and the start module, so as to control the on/off of the electrical connection between the power input terminal and the power output terminal according to the voltage detection signal output by the detection module.
In one possible implementation manner of the present application, the power input end and the power output end are all electrically connected with a surge protection module, and the surge protection module is used for suppressing input to the power input end and the surge voltage of the power output end.
In another aspect, the present application provides an electronic device including a delay anti-shake circuit as described.
When the time delay jitter circuit operates normally, the voltage stabilizing module realizes the one-way transmission of the voltage detection signal, and the voltage storage module stores the voltage detection signal, when the short circuit is recovered or the poor contact is caused in the circuit to cause the problem of voltage jitter, the voltage drop occurs at the electric connection point of the first switch module and the voltage storage module, at the moment, the second switch module is controlled to be switched off according to the voltage value of the voltage detection signal of the first switch module and the preset delay starting voltage value, the delay anti-jitter circuit is locked by the second switch module, meanwhile, the voltage storage module and the first switch module release surge voltage, after the voltage is released to the first switch module to meet the conduction condition, after delaying a period of time promptly, then first switch module and second switch module switch on to release the locking of time delay anti-shake circuit, and then effectively reduce the probability that surge current leads to the circuit damage.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an embodiment of a delay anti-jitter circuit provided in an embodiment of the present application;
fig. 2 is a schematic structural diagram of an embodiment of a delay anti-jitter circuit provided in an embodiment of the present application;
FIG. 3 is a schematic structural diagram of an embodiment of a bias power supply module provided in an embodiment of the present application;
fig. 4 is a schematic structural diagram of an embodiment of a delay anti-jitter circuit provided in an embodiment of the present application;
fig. 5 is a schematic structural diagram of an embodiment of an electronic device provided in an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In this application, the word "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the application. In the following description, details are set forth for the purpose of explanation. It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes are not set forth in detail in order to avoid obscuring the description of the present application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
The embodiments of the present application provide a delay anti-shake circuit and an electronic device, which are described in detail below.
As shown in fig. 1, which is a schematic structural diagram of an embodiment of a delay anti-jitter circuit in an embodiment of the present application, the delay anti-jitter circuit includes:
in one possible implementation manner of the present application, the voltage regulator includes a signal detecting terminal 800, a voltage stabilizing module 801, a voltage storing module 802, a first switching module 803 and a second switching module 804,
a signal detection terminal 800 for providing a voltage detection signal in the delay anti-jitter circuit;
the voltage stabilizing module 801 is electrically connected with the signal detection terminal 800 and is used for controlling voltage detection signals to be transmitted to the first switch module 803 and the voltage storage module 802 in a single direction;
the voltage storage module 802 and the voltage stabilizing module 801 are electrically connected and used for storing and releasing voltage detection signals;
the first switch module 803 is electrically connected to the voltage stabilizing module 801 and the voltage storage module 802, and is configured to start a voltage value according to the voltage value of the voltage detection signal and a preset delay time, and control on/off of the second switch module 804;
and the second switch module 804 is electrically connected with the first switch module 803 and the voltage stabilizing module 801 and is used for controlling the on-off of the delay anti-shake circuit.
When the time delay jitter circuit operates normally, the voltage stabilizing module realizes the one-way transmission of the voltage detection signal, and the voltage storage module stores the voltage detection signal, when the short circuit is recovered or the poor contact is caused in the circuit to cause the problem of voltage jitter, the voltage drop occurs at the electric connection point of the first switch module and the voltage storage module, at the moment, the second switch module is controlled to be switched off according to the voltage value of the voltage detection signal of the first switch module and the preset delay starting voltage value, the delay anti-jitter circuit is locked by the second switch module, meanwhile, the voltage storage module and the first switch module release surge voltage, after the voltage is released to the first switch module to meet the conduction condition, after delaying a period of time promptly, then first switch module and second switch module switch on to release the locking of time delay anti-shake circuit, and then effectively reduce the probability that surge current leads to the circuit damage.
In one possible implementation manner of the present application, the voltage stabilizing module 801 includes a voltage stabilizing diode, an anode of the voltage stabilizing diode is electrically connected to the signal detecting terminal 800, and a cathode of the voltage stabilizing diode is electrically connected to the voltage storing module 802 and the first switch module 803.
In one possible implementation manner of the present application, the voltage storage module 802 includes a storage capacitor C5, one end of the storage capacitor C5 is electrically connected to the cathode of the zener diode D4, and the other end of the storage capacitor C5 is grounded.
In a possible implementation manner of the present application, the first switch module 803 includes a fourth resistor R12, a fifth resistor R14, a sixth resistor R8, and a second transistor Q9, an emitter of the second transistor Q9 is electrically connected to an electrical connection point between one end of the storage capacitor C5 and a cathode of the zener diode D4, a collector of the second transistor Q9 is electrically connected to one end of the fourth resistor R12, the other end of the fourth resistor R12 is grounded through the fifth resistor R14, a base of the second transistor Q9 is electrically connected to the second switch module 804 through the sixth resistor R8, where the preset delay start voltage value is a voltage value of a turn-on voltage of the second transistor Q9.
In a possible implementation manner of the present application, the second switching module 804 includes a third resistor R10 and a third transistor Q11, a base of the third transistor Q11 is electrically connected to an electrical connection point of the fourth resistor R12 and the fifth resistor R14, a collector of the third transistor Q11 is electrically connected to the signal detection terminal through the third resistor R10, and an emitter of the third transistor Q11 is grounded.
In the application process, when no voltage jitter occurs, the zener diode D4 transmits the voltage detection signal output by the signal detection terminal to the storage capacitor C5 for charging, when the circuit has jitter, the voltage division value of the voltage detection signal also drops in a corresponding proportion, and simultaneously the voltage of the base of the second triode Q9 also drops synchronously, but the voltage of the storage capacitor C5 remains unchanged at this time, and the zener diode D4 blocks the current backflow of the emitter of the second triode Q9, so the second triode Q9 is in an off state, when the voltage of the base of the second triode Q9 drops to a preset starting voltage value, that is, when the voltage of the base of the second triode Q9 drops to the conducting voltage of the second triode Q9, the second triode Q9 is conducted at this time, the fourth resistor R12 and the fifth resistor R14 divide the voltage, so that the third triode Q11 is conducted, and the voltage division point of the signal detection terminal is pulled to the ground, therefore, the whole detection module 500 is controlled to be locked, so that the detection unit 501 is turned off, after a period of time delay, the second triode Q9 is turned off until the storage capacitor C5 discharges to a voltage value which makes the delayed starting voltage value not meet the conduction voltage of the second triode Q9, and meanwhile, the third triode Q11 cannot be turned on, that is, locking is released. Therefore, when voltage jitter occurs in the circuit, the delay anti-jitter circuit is controlled to be disconnected, the damage of instantaneous high voltage to the whole circuit is avoided, other peripheral equipment electrically connected with the delay anti-jitter circuit is better protected, and the circuit is safer.
In one possible implementation manner of the present application, as shown in fig. 2, the delay anti-shake circuit further includes:
the power supply comprises a power supply input end 100 and a power supply output end 200, wherein the power supply input end 100 is electrically connected with power supply equipment for providing power supply signals, the power supply output end 200 is electrically connected with a corresponding drive board or drive circuit input end which needs to be connected with a power supply, the power supply output end 200 comprises one or more load capacitors C2 which are connected in parallel, the load capacitors C2 can also be arranged in a rear-stage circuit (such as a drive board, a drive circuit or other circuits), and the power supply of the drive board or the drive circuit is realized through the charging and discharging functions of the load capacitors C2.
The starting module 300 is electrically connected to the power input terminal 100 and the power output terminal 200, and is configured to output a constant current signal with a preset current value to charge the power output terminal 200, specifically, after the power output terminal 200 is connected to a power supply, the starting module 300 outputs the constant current signal with the preset current value to charge the load capacitor C2.
The switch module 400 is electrically connected to the power input terminal 100, the power output terminal 200 and the start module 300, and is configured to control on/off of electrical connection between the power input terminal 100 and the power output terminal 200.
The detection module 500 is electrically connected to the starting module 300, the switch module 400 and the power output end 200, and is configured to output a first control signal according to the constant current signal, and control on/off of the switch module 400 according to a voltage value of the first control signal and a preset voltage value range of the first control signal.
In this embodiment, the output terminal of the detection module 500 is the signal detection terminal 800, and the first control signal is the voltage detection signal output by the signal detection terminal 800.
In one embodiment of the present application, the surge protection module 700 is electrically connected to each of the power input terminal 100 and the power output terminal 200, and the surge protection module 700 is used for suppressing a surge voltage input to the power input terminal 100 and the power output terminal 200.
As shown in fig. 2, the surge protection module 700 includes a Transient diode D2 (TVS) and a Transient diode D3, the Transient diode D3 is electrically connected to the power input terminal 100, the other end of the Transient diode D3 is grounded, the Transient diode D3 is electrically connected to the power output terminal 200, and the other end of the Transient diode D3 is grounded. When two ends of the TVS tube are subjected to instant high-energy impact, the TVS tube can reduce the impedance thereof suddenly at a very high speed, and simultaneously absorb a large current to clamp the voltage between the two ends thereof at a predetermined value, thereby being capable of suppressing the surge voltage input to the power input terminal 100 and the power output terminal 200 and ensuring the damage caused by the impact of the surge voltage of elements in the time delay anti-shake circuit.
In an embodiment of the present application, the starting module 300 includes a first switch tube 301, a first voltage divider 302, a second voltage divider 303, and a voltage regulator tube 304, a first end of the first switch tube 301 and a first end of the second voltage divider 303 are both electrically connected to the power input terminal 100, a second end of the second voltage divider 303 is electrically connected to a first end of the voltage regulator tube 304, a second end of the first switch tube 301 is electrically connected to an electrical connection point where a second end of the second voltage divider 303 is electrically connected to a first end of the voltage regulator tube 304, a third end of the first switch tube 301 is electrically connected to a first end of the first voltage divider 302, and a second end of the first voltage divider 302 is electrically connected to a second end of the voltage regulator tube 304.
Specifically, the first switch tube 301 includes a first switch tube Q1, and the first switch tube Q1 may employ an N-channel mosfet, that is, an N-channel MOS tube, or a P-channel MOS tube. The resistor R1 used in the first voltage divider 302 may be a resistor R1 and a resistor R2 connected in parallel, or more resistors connected in parallel may be provided according to specific needs, which is not limited herein. The second voltage divider 303 uses a voltage divider resistor R3, and the voltage regulator 304 uses a voltage regulator D1. As shown in fig. 2, the drain of the first switch tube Q1 and one end of the voltage-dividing resistor R3 are electrically connected to the power input terminal 100, the other end of the voltage-dividing resistor R3 is electrically connected to one end of the voltage-regulator tube D1, the source of the first switch tube Q1 is electrically connected to one end of the resistor R2, the resistor R1 and the resistor R2 are connected in parallel, the other end of the resistor R2 and the other end of the voltage-regulator tube D1 are electrically connected to the power output terminal 200, and the gate of the first switch tube Q1 is electrically connected to the point of electrical connection between the voltage-dividing resistor R3 and the voltage-regulator tube D1.
In the application process, in the charging process, a fixed voltage point is formed between the voltage dividing resistor R3 and the voltage regulator tube D1, so that the voltage values at the two ends of the voltage regulator tube D1 are fixed, that is, the voltage value at the two ends of the first switch tube Q1 and the two ends of the resistor R1 and the resistor R2 which are electrically connected in parallel are the same as the voltage value at the two ends of the voltage regulator tube D1, and since the voltage value at the two ends of the resistor R1 and the resistor R2 which are electrically connected in parallel is constant, the current in the resistor R1 and the resistor R2 is also constant, a constant current circuit is formed, and after receiving a power supply signal input by the power supply input end 100, the starting module 300 outputs a constant current signal with a preset current value to the power supply output end 200, so as to realize constant current starting.
In this embodiment, the start module 300 further includes a decoupling capacitor C1, the voltage regulator tube D1 is electrically connected in parallel with the decoupling capacitor C1, as shown in fig. 2, one end of the decoupling capacitor C1 and the gate of the first switch tube Q1 are electrically connected to the electrical connection point of the voltage dividing resistor R3 and the voltage regulator tube D1, the other end of the decoupling capacitor C1 is electrically connected to the other end of the voltage regulator tube D1, and the decoupling capacitor C1 prevents the first switch tube Q1 from oscillating, so as to enhance the stability of the start module 300.
In this embodiment, the preset current value of the constant current signal output by the starting module 300 may be adjusted according to a specific actual situation, where the preset current value of the constant current signal is not specifically limited, and for example, the preset current value of the constant current signal may be adjusted by setting a parallel resistance value parameter of the resistor R1 and the resistor R2 or by selecting a zener diode D1 with different voltage stabilization value parameters, for example, increasing or decreasing the resistance values of the resistor R1 and the resistor R2, and selecting a diode D1 with a larger voltage stabilization value or a smaller voltage stabilization value.
In an embodiment of the present application, the switch module 400 is connected in parallel with the starting module 300, and specifically, the switch module 400 includes:
the first switch unit 401 is electrically connected with the power input end 100, the power output end 200 and the starting module 300, and is used for controlling the electrical connection and disconnection of the power input end 100 and the power output end 200;
and the first conversion unit 402, the first conversion unit 402 is electrically connected with the first switch unit 401 and the module, and is configured to receive a first control signal input by the detection module 500, output a second control signal to the first switch unit 401 according to the first control signal, and control on/off of the first switch unit 401.
In an embodiment of the present application, the first switch unit 401 includes one second switch tube or a plurality of second switch tubes electrically connected in parallel, as shown in fig. 2, the first switch unit 401 may be one second switch tube Q2, and may also be a plurality of second switch tubes electrically connected in parallel, that is, the second switch tube Q3, the second switch tube Q4, and the second switch tube Q6, in order to share the heating power with the second switch tube Q2.
The second switch tube comprises an N-channel metal oxide semiconductor field effect transistor and a P-channel metal oxide semiconductor field effect transistor. For example, the second switching tube Q2, the second switching tube Q3, the second switching tube Q4, and the second switching tube Q6 may all be N-channel MOS tubes, or may all be P-channel MOS tubes, which is not limited herein.
In this embodiment, as shown in fig. 2, the second switching transistor Q2, the second switching transistor Q3, the second switching transistor Q4 and the second switching transistor Q6 are all N-channel MOS transistors, wherein, the drain of the second switch tube Q2, the drain of the second switch tube Q3, the drain of the second switch tube Q4 and the drain of the second switch tube Q6 are electrically connected in parallel and then electrically connected to the power input terminal 100, and is connected in parallel to the electrical connection point between the start module 300 and the power input terminal 100, the source of the second switch transistor Q2, the source of the second switch transistor Q3, the source of the second switch transistor Q4 and the source of the second switch transistor Q6 are electrically connected to the power output terminal 200 after being connected in parallel, and is connected in parallel to the electrical connection point between the start module 300 and the power output terminal 200, and the gate of the second switching tube Q2, the gate of the second switching tube Q3, the gate of the second switching tube Q4, and the gate of the second switching tube Q6 are electrically connected to the first converting unit 402 after being connected in parallel.
The second switch tube Q2, the second switch tube Q3, the second switch tube Q4 and the second switch tube Q6 are used for controlling the on-off of the power input end 100 and the power output end 200, so that when surge voltage is input from the power input end 100, the second switch tube Q2, the second switch tube Q3, the second switch tube Q4 and the second switch tube Q6 are used for controlling the disconnection between the power input end 100 and the power output end 200, so that the surge voltage is inhibited from being output to the power output end 200, and other parts electrically connected with the power output end 200 are protected.
When the second switch tube is an N-channel mosfet, the corresponding first signal conversion unit 402 is specifically:
as shown in fig. 2, the first conversion unit 402 includes a resistor R5, a resistor R7, a resistor R9, a transistor Q7, and a transistor Q10, where the transistor Q7 may be a PNP-type transistor and may also be a P-channel MOS transistor, and the transistor Q10 may be an NPN-type transistor and may also be an N-channel MOS transistor, which is not limited herein.
In this embodiment, the transistor Q7 is a PNP transistor, the transistor Q10 is an NPN transistor, one end of the resistor R5 is electrically connected to one end of the resistor R9, the other end of the resistor R9 is electrically connected to a collector of the transistor Q10, an emitter of the transistor Q10 is grounded, a base of the transistor Q10 is electrically connected to the output terminal of the detection module 500, the other end of the resistor R5 is electrically connected to an emitter of the transistor Q7, a base of the transistor Q7 is electrically connected to an electrical connection point of the resistor R5 and the resistor R9, a collector of the transistor Q7 is electrically connected to one end of the resistor R7, and the other end of the resistor R7 is electrically connected to the first switch unit 401.
The base of the triode Q10 receives a first control signal input by the detection module 500, the triode Q10 is controlled to be conducted by the first control signal, the triode Q10 is conducted, the collector voltage of the triode Q10 is pulled down at the moment, due to the partial pressure effect of the resistor R5 and the resistor R9, the triode Q7 is conducted, and then a second control signal is output to the first switch unit 401, so that the conduction of the first switch unit 401 is controlled, when the base of the triode Q10 receives the conduction condition that the first control signal input by the detection module 500 does not satisfy the triode Q10, the corresponding triode Q7 and the first switch unit 401 are both turned off.
In order to enhance the driving signal of the first switch unit 401, a push-pull unit 403 may be added to the switch module 400, and the push-pull unit 403 controls the on/off of the first switch unit 401, and at the same time, the on speed or the off speed of each second switch tube in the first switch unit 401 may be increased.
Therefore, in one embodiment of the present application, when the second switch transistor is an N-channel mosfet, the switch module 400 includes:
and a push-pull unit 403 electrically connected between the first switching unit 401 and the first converting unit 402, for amplifying the second control signal output by the first converting unit 402.
Specifically, the push-pull unit 403 includes a transistor Q5, a transistor Q8, and a current-limiting resistor R6, in this application, the transistor Q5 is a PNP transistor, and the transistor Q8 is an NPN transistor, in this embodiment, the push-pull unit 403 may also be another switching transistor that can perform a switching function, for example, an mos transistor or a field effect transistor, which is not limited specifically here.
As shown in fig. 2, the transistor Q5 and the transistor Q8 are electrically connected back to back, that is, the base of the transistor Q5 is electrically connected to the base of the transistor Q8, the base of the transistor Q5 and the base of the transistor Q8 are electrically connected to a common parallel electrical connection point of the gate of the second switching tube Q2, the gate of the second switching tube Q3, the gate of the second switching tube Q4 and the gate of the second switching tube Q6, the emitter of the transistor Q5 is electrically connected to the emitter of the transistor Q8, the collector of the transistor Q5 is electrically connected to the emitter of the transistor Q7, and the collector of the transistor Q8 is electrically connected to the free end of the resistor R7.
One end of the current-limiting resistor R6 is electrically connected to the electrical connection point between the base of the transistor Q5 and the base of the transistor Q8, and the other end of the current-limiting resistor R6 is electrically connected to the electrical connection point between the collector of the transistor Q7 and the resistor R7.
The push-pull unit 403 is formed by the transistor Q5 and the transistor Q8 to amplify the second control signal output by the first conversion unit 402, so that the on/off speed of the switch unit can be increased.
In one embodiment of the present application, when the second switch tube is an N-channel mosfet, according to the characteristics of the N-channel MOS transistor, the push-pull unit 403 is required to output a high level to turn on the second switching transistor Q2, the second switching transistor Q3, the second switching transistor Q4, and the second switching transistor Q6 in the first switching unit 401, and the stability of the power voltage input from the power input terminal 100 is poor, which cannot satisfy the stable power supply of the push-pull unit 403 and the first converting unit 402, and thus the operation of the second switching transistor Q2, the second switching transistor Q3, the second switching transistor Q4, and the second switching transistor Q6 in the first switching unit 401 is unstable, when the second switching tube Q2, the second switching tube Q3, the second switching tube Q4, and the second switching tube Q6 in the first switching unit 401 may all be N-channel MOS tubes, the bias power supply module 600 needs to be added, the first conversion unit 402 and the push-pull unit 403 are powered by the bias power supply module 600.
Therefore, the delay anti-shake circuit in the present application further includes a bias power supply module 600, and the bias power supply module 600 is electrically connected to the switch module 400 for supplying power to the first conversion unit 402 and the push-pull unit 403.
As shown in fig. 3, the bias power supply module 600 includes a current limiting protection unit 601, an anti-surge slow start protection unit 602, a second push-pull unit 603, and a rectifying and filtering unit 604, which are electrically connected in sequence.
Specifically, the current limiting protection unit 601 includes a resistor R15 and a TVS tube D9, one end of the resistor R15 is electrically connected to the power output port of the power supply device, and the other end is grounded through the TVS tube D9. The current of the power supply input by the power supply device is limited by the resistor R15, and the input transient high voltage is suppressed by the TVS tube D9, so as to protect the components in the bias power supply module 600.
The bias power supply module 600 further includes a current limiting resistor R16, and two ends of the current limiting resistor R16 are electrically connected to the rectifying and filtering unit 604 and the output end of the bias power supply module 600, respectively.
The surge-prevention slow start protection unit 602 comprises a resistor R20, a resistor R18, a resistor R19, a resistor R21, a capacitor C14, a capacitor C15, a triode Q14 and a triode Q15.
The collector of the transistor Q14 is electrically connected to the point of electrical connection between the resistor R15 and the TVS tube D9 through the resistor R20, the emitter of the transistor Q14 is grounded, the base of the transistor Q14 is electrically connected to the collector of the transistor Q15 through the capacitor C14, and both ends of the resistor R18 are electrically connected between the collector and the base of the transistor Q14, respectively.
The collector of the transistor Q15 is electrically connected to the point of electrical connection between the resistor R15 and the TVS tube D9 through the resistor R21, the emitter of the transistor Q15 is grounded, the base of the transistor Q15 is electrically connected to the collector of the transistor Q14 through the capacitor C15, and both ends of the resistor R19 are electrically connected between the collector and the base of the transistor Q15, respectively.
In this embodiment, when the bias power supply module 600 is powered on, the two ends of the resistor R20 and the resistor R21 have a certain voltage value, the capacitor C15 is charged through the resistor R20, the capacitor C14 is charged through the resistor R21, after the power supply voltage accessed by the bias power supply module 600 drops, the capacitor C14 and the capacitor C15 start to discharge, when the capacitor C14 and the capacitor C15 discharge for a period of time, and the voltage across the resistor R18 reaches the on-state voltage of the transistor Q14 and the voltage across the resistor R19 reaches the on-state voltage of the transistor Q15, the transistor Q14 and the transistor Q15 are both turned on, thereby directing the voltages in the capacitor C14 and the capacitor C15 to be pulled down to ground, protecting the devices at the back end of the bias power module 600, if the bias power supply module 600 has an instantaneous high-voltage surge voltage after being connected to a power supply, the surge voltage can be rapidly input to the ground in the above manner, so that the back-end circuit is protected.
The second push-pull unit 603 includes a transistor Q13, a transistor Q12, a current-limiting resistor R17, and a capacitor C12, wherein the transistor Q13 and the transistor Q12 are electrically connected back to back, a base of the transistor Q13 is electrically connected to a base of the transistor Q12, an emitter of the transistor Q13 is electrically connected to an emitter of the transistor Q12, a collector of the transistor Q13 is electrically connected to an emitter of the transistor Q7, one end of the current-limiting resistor R17 is electrically connected to an electrical connection point between the base of the transistor Q13 and the base of the transistor Q12, the other end of the current-limiting resistor R17 is electrically connected to an electrical connection point between the resistor R21 and the collector of the transistor Q15, one end of the capacitor C12 is electrically connected to an electrical connection point between the emitter of the transistor Q13 and the emitter of the transistor Q12, and one end of the capacitor C12 is electrically connected to a cathode of a diode D7 (see below). Through the complementary push-pull amplification effect of the triode Q13 and the triode Q12, the capacitor C12 plays a role in assisting push-pull amplification, the output power of the bias power supply module 600 is enhanced, and the instantaneous response speed of output current and the voltage output characteristic are improved. In this embodiment, the second push-pull unit 603 may also be another type of switching tube that can function as a switch, and is not limited herein.
The rectifying and filtering unit 604 comprises a diode D7, a diode D6, a capacitor C13, a capacitor C10, a capacitor C6, a capacitor C7, a capacitor C8 and a capacitor C9. As shown in fig. 3, one end of a capacitor C13 and one end of a capacitor C10 are electrically connected to an electrical connection point between the resistor R15 and the TVS tube D9, the other end of a capacitor C13 and the other end of a capacitor C10 are electrically connected to ground, the diode D7 and the diode D6 are sequentially connected in series, an anode of the diode D7 is electrically connected to a collector of the transistor Q12, a cathode of the diode D7 is electrically connected to an anode of the diode D6, one end of a capacitor C12 is electrically connected to an electrical connection point between a cathode of the diode D7 and an anode of the diode D6, one end of the capacitors C6, C7, C8, and C9 which are connected in parallel is electrically connected to a cathode of the diode D6, and the other end of the capacitors C6, C7, C8, and C9 which are connected in parallel is connected to ground.
In an embodiment of the present application, since the second switch tube may also adopt a P-channel mosfet, when the second switch tube is a P-channel mosfet, according to the characteristics of the P-channel MOS, the push-pull unit 403 is not required to output a high level to ensure that the second switch unit 404 is turned on, and accordingly, the switch module 400 is different from the switch module in that the push-pull unit 403 is not included, and a bias power circuit for supplying power to the push-pull unit 403 and the first conversion unit 402 is not included.
Therefore, in the present embodiment, a second switch module 400 applicable to a delay anti-shake circuit is proposed, and the switch module 400 includes:
the second switch unit 404, the second switch unit 404 is electrically connected to the power input end 100, the power output end 200 and the starting module 300, and is used for controlling the electrical connection of the power input end 100 and the power output end 200;
and the second conversion unit 405 is electrically connected with the second switch unit 404 and the module, and is configured to receive the first control signal input by the detection module 500, output a third control signal to the second switch unit 404 according to the first control signal, and control on/off of the second switch unit 404.
In this embodiment, the second switch unit 404 includes a third switch tube or a plurality of third switch tubes electrically connected in parallel, and the third switch tube is a P-channel mosfet, as shown in fig. 4, that is, the third switch tube Q16, the third switch tube Q17, the third switch tube Q18, the third switch tube Q19 and the third switch tube Q20 in the second switch unit 404 are all P-channel MOS tubes.
The source of the third switching tube Q16, the source of the third switching tube Q17, the source of the third switching tube Q18, the source of the third switching tube Q19 and the source of the third switching tube Q20 are electrically connected to the power input 100 after being connected in parallel, and are connected to the electrical connection point of the start module 300 and the power input 100 in parallel, the drain of the third switching tube Q16, the drain of the third switching tube Q17, the drain of the third switching tube Q18, the drain of the third switching tube Q19 and the drain of the third switching tube Q20 are electrically connected to the power output 200 after being connected in parallel, and are connected to the electrical connection point of the start module 300 and the power output 200 in parallel, and the gate of the third switching tube Q16, the gate of the third switching tube Q17, the gate of the third switching tube Q18, the gate of the third switching tube Q19 and the gate of the third switching tube Q20 are electrically connected in parallel and are connected to the second conversion unit 405 after being connected in parallel. The third switching tube Q16, the third switching tube Q17, the third switching tube Q18, the third switching tube Q19 and the third switching tube Q20 control the on/off of the power input end 100 and the power output end 200, so that when the instantaneous high voltage is input at the power input end 100, the instantaneous high voltage is inhibited from being output to the power output end 200.
In this embodiment, the second converting unit 405 is specifically, as shown in fig. 4, the second converting unit 405 includes a transistor Q20, a resistor R22, a resistor R23, a voltage regulator D10, and a capacitor C16, a collector of the transistor Q21 is electrically connected to the power input terminal 100 through a resistor R22 and a resistor R23, an emitter of the transistor Q21 is grounded, a base of the transistor Q21 is electrically connected to the output terminal of the detecting module 500, and a gate of the third switch Q16, a gate of the third switch Q17, a gate of the third switch Q18, a gate of the third switch Q19, and a gate of the third switch Q20 in the second switching unit 404 are electrically connected in parallel and then electrically connected to an electrical connection point between the collector of the transistor Q21 and the resistor R23. One end of a capacitor C16 is electrically connected with the power input end 100, the other end of a capacitor C16 is electrically connected with the electric connection point of the collector of the triode Q21 and the resistor R23, the negative electrode of a voltage regulator tube D10 is electrically connected with the power input end 100, and the positive electrode of a voltage regulator tube D10 is electrically connected with the electric connection point of the collector of the triode Q21 and the resistor R23.
The base of the transistor Q21 receives the first control signal input by the detection module 500, the first control signal controls the transistor Q21 to be turned on, after the transistor Q21 is turned on, the collector voltage of the transistor Q21 is pulled down, due to the voltage dividing effect of the resistor R22 and the resistor R22, the third control signals are generated at the gate of the third switching tube Q16, the gate of the third switching tube Q17, the gate of the third switching tube Q18 and the gate of the third switching tube Q19, so as to control the turn-on of the second switching unit 404, and when the first control signal input by the base of the transistor Q21 receiving the detection module 500 does not satisfy the turn-on condition of the transistor Q21, the corresponding second switching unit 404 is also turned off.
In one embodiment of the present application, the detection module 500 includes:
the detection unit 501 is electrically connected to the start module 300 and the switch module 400, and is configured to output a first control signal and a third control signal according to the constant current signal, where the first control signal is used to control on/off of the switch module 400. Specifically, as shown in fig. 2 and 4, the detecting unit 501 includes a voltage dividing resistor R4, a voltage dividing resistor R11, and a voltage dividing resistor R13, which are electrically connected in sequence, the other end of the voltage dividing resistor R4 is electrically connected to an electrical connection point between the start module 300 and the power output end 200, and a base of the transistor Q10 (or the transistor Q21) is electrically connected to an electrical connection node between the voltage dividing resistor R11 and the voltage dividing resistor R13. The constant current signal output by the starting module 300 is detected at the electric connection point of the voltage dividing resistor R4, the starting module 300 and the power output end 200, a first control signal is formed by dividing voltage between the voltage dividing resistor R11 and the voltage dividing resistor R13, a third control signal is formed by dividing voltage between the voltage dividing resistor R4 and the voltage dividing resistor R11, and the on-off of the triode Q10 is controlled through the first control signal, so that the on-off of the switch module 400 is controlled.
In the application process, when the starting module 300 receives a power signal input by the power input terminal 100, the starting module 300 outputs a constant current signal with a preset current value, and the power output terminal 200 is charged, voltages with certain values are applied to two ends of the voltage dividing resistor R4, two ends of the voltage dividing resistor R11, and two ends of the voltage dividing resistor R13, when the voltage of the electrical connection node of the voltage dividing resistor R11 and the voltage dividing resistor R13 meets the conduction condition of the triode Q10 (or the triode Q21), the triode Q10 (or the triode Q21) is conducted, the switch module 400 is conducted, and the power output terminal 200 receives the power signal; on the contrary, when the power signal input by the input terminal is a surge voltage or the power output terminal 200 is short-circuited, and the voltage of the electrical connection node between the voltage dividing resistor R11 and the voltage dividing resistor R13 cannot satisfy the conduction condition of the transistor Q10 (or the transistor Q21), the corresponding transistor Q10 (or the transistor Q21) is turned off, and the power output terminal 200 cannot receive the power signal.
In this embodiment, the delay jitter circuit is electrically connected to the detection unit 501, and the signal detection terminal 800 in the delay jitter circuit is used for providing a third control signal and controlling the on/off of the detection unit 501 according to a voltage value of the third control signal and a preset delay start voltage value. In this embodiment, the third control signal is a divided signal formed between the voltage dividing resistor R4 and the voltage dividing resistor R11, and the preset delay start voltage value is a voltage value of the turn-on voltage of the transistor Q9.
In one embodiment of the present application, the present application provides a control apparatus, the apparatus includes a delay anti-shake circuit, and the delay anti-shake circuit is a delay anti-shake circuit.
In an embodiment of the present application, the present application further provides an electronic device, which includes a time-delay anti-shake circuit or a control device as described above.
In this embodiment, as shown in fig. 5, the electronic device may be a lighting device 800, the lighting device 800 has an input port 801, the input port 801 is used for being electrically connected with a control device 900 so as to control or drive or supply power to the lighting device 800 through the control device 900, and the time delay anti-shake circuit 802 may be disposed in the lighting device 800 and between the input port 801 and the light source driving board 803.
In this embodiment, the device may also be a control device 900, the control device 900 has an input port 901 and an output port 902, the input port 901 is used for receiving an external power input, the output port 902 is used for electrically connecting with the lighting device 800 to control, drive or supply power to the lighting device 800 through the control device 900, and the above-mentioned time-delay anti-shake circuit may be disposed in the control device 900 and located at the input port 901.
The foregoing detailed description is directed to a delay anti-shake circuit and an electronic device provided in the embodiments of the present application, and specific examples are applied in the detailed description to explain the principles and implementations of the present application, and the descriptions of the foregoing embodiments are only used to help understand the method and the core ideas of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A time-delay anti-shake circuit is characterized by comprising a signal detection terminal (800), a voltage stabilization module (801), a voltage storage module (802), a first switch module (803) and a second switch module (804),
a signal detection terminal (800) for providing a voltage detection signal in the time-delay anti-shake circuit;
the voltage stabilizing module (801) is electrically connected with the signal detection terminal (800) and is used for controlling the voltage detection signal to perform unidirectional transmission to the first switch module (803) and the voltage storage module (802);
the voltage storage module (802), the voltage stabilization module (801) is electrically connected and used for storing and releasing the voltage detection signal;
the first switch module (803) is electrically connected with the voltage stabilizing module (801) and the voltage storage module (802), and is used for controlling the on-off of the second switch module (804) according to the voltage value of the voltage detection signal and a preset delay starting voltage value;
and the second switch module (804) is electrically connected with the first switch module (803) and the voltage stabilizing module (801) and is used for controlling the on-off of the time-delay anti-shake circuit.
2. The delay anti-shake circuit according to claim 1, wherein the zener module (801) comprises a zener diode, an anode of the zener diode is electrically connected to the signal detection terminal (800), and a cathode of the zener diode is electrically connected to the voltage storage module (802) and the first switching module (803).
3. The time-delay anti-shake circuit of claim 2, wherein the voltage storage module (802) comprises a storage capacitor, one end of the storage capacitor is electrically connected to the cathode of the zener diode, and the other end of the storage capacitor is grounded.
4. The time-delay anti-shake circuit of claim 3, wherein the first switch module (803) comprises a fourth resistor, a fifth resistor, a sixth resistor, and a second triode, wherein an emitter of the second triode is electrically connected to an electrical connection point between one end of the storage capacitor and a cathode of the zener diode, a collector of the second triode is electrically connected to one end of the fourth resistor, the other end of the fourth resistor is grounded through the fifth resistor, and a base of the second triode is electrically connected to the second switch module (804) through the sixth resistor.
5. The time-delay anti-shake circuit of claim 4, wherein the second switch module (804) comprises a third resistor and a third transistor, a base of the third transistor is electrically connected to an electrical connection point of the fourth resistor and the fifth resistor, a collector of the third transistor is electrically connected to the signal detection terminal through the third resistor, and an emitter of the third transistor is grounded.
6. The delayed anti-jitter circuit of claim 1, wherein the delayed anti-jitter circuit further comprises:
a power input terminal (100) and a power output terminal (200);
the signal detection end (800) is electrically connected with a detection module (500) and used for outputting a first control signal, and generating a voltage detection signal at the signal detection end according to the voltage value of the first control signal and a preset voltage value range of the first control signal so as to control the on-off state between the power input end (100) and the power output end (200).
7. The time-delay anti-shake circuit of claim 6, wherein the detection module is electrically connected to a start module (300), and the start module (300) is electrically connected to the power input terminal (100) and the power output terminal (200) and is configured to output a constant current signal with a preset current value to charge the power output terminal (200).
8. The time-delay anti-shake circuit of claim 7, wherein the detection module is electrically connected to a switch module (400), and is electrically connected to the power input terminal (100), the power output terminal (200) and the start module (300), for controlling the electrical connection between the power input terminal (100) and the power output terminal (200) according to the voltage detection signal outputted by the detection module (500).
9. The time-delay anti-shake circuit of claim 6, wherein the power input terminal (100) and the power output terminal (200) are electrically connected with a surge protection module for suppressing a surge voltage input to the power input terminal (100) and the power output terminal (200).
10. An electronic device, characterized in that the electronic device comprises a time-delay anti-shake circuit as claimed in any one of claims 1 to 9.
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| CN202122690608.XU CN216721168U (en) | 2021-11-04 | 2021-11-04 | Time delay anti-shake circuit and electronic equipment |
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| CN202122690608.XU CN216721168U (en) | 2021-11-04 | 2021-11-04 | Time delay anti-shake circuit and electronic equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024060754A1 (en) * | 2022-09-19 | 2024-03-28 | 海信视像科技股份有限公司 | Lamp panel circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024060754A1 (en) * | 2022-09-19 | 2024-03-28 | 海信视像科技股份有限公司 | Lamp panel circuit |
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Address after: 518110 floors 2-4, building 21, Longjun Industrial Zone, Jiuwo, Longping community, Dalang street, Longhua District, Shenzhen City, Guangdong Province Patentee after: Shenzhen Aitushi Innovation Technology Co.,Ltd. Address before: 518110 floors 2-4, building 21, Longjun Industrial Zone, Jiuwo, Longping community, Dalang street, Longhua District, Shenzhen City, Guangdong Province Patentee before: APUTURE IMAGING INDUSTRIES Co.,Ltd. |