CN216718968U - Programmable control chip and drive circuit thereof - Google Patents
Programmable control chip and drive circuit thereof Download PDFInfo
- Publication number
- CN216718968U CN216718968U CN202220176381.9U CN202220176381U CN216718968U CN 216718968 U CN216718968 U CN 216718968U CN 202220176381 U CN202220176381 U CN 202220176381U CN 216718968 U CN216718968 U CN 216718968U
- Authority
- CN
- China
- Prior art keywords
- input
- voltage
- resistor
- control chip
- mos transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Dc-Dc Converters (AREA)
Abstract
The utility model provides a programmable control chip and a driving circuit thereof, wherein the driving circuit comprises a first resistor, a second resistor and a programmable control chip, one end of the second resistor is connected with an input voltage, and the other end of the second resistor is connected with the first resistor in series and then is grounded; connecting an over/under-voltage multiplexing pin of a programmable control chip to a series node of a first resistor and a second resistor, and setting an input under-voltage protection threshold and an input under-voltage protection recovery threshold of the programmable control chip by adjusting the resistance ratio of the first resistor and the second resistor; and setting an input overvoltage protection threshold value and an input overvoltage protection recovery threshold value of the programmable control chip by adjusting the resistance value of the second resistor. The utility model only needs one pin, and can program the input overvoltage protection threshold and the input undervoltage protection threshold by adjusting the resistance value of the peripheral resistor, thereby reducing the number of chip pins and facilitating the user to realize the program control of the protection function of the chip in the peripheral circuit.
Description
Technical Field
The utility model relates to the technical field of control chips, in particular to a programmable control chip and a driving circuit thereof.
Background
In the course of decades of silicon semiconductor integrated circuit technology, especially the featured technology suitable for power chip design, the technology has been developed from the first generation Biporlar technology, which originally includes only bipolar transistors, to the CMOS technology of insulated gate MOS transistors with higher integration, and then to the BCD technology including bipolar devices, CMOS devices and DMOS devices. In recent years, the characteristic process of simulating the semiconductor of the integrated circuit is rapidly developed, the BCD process of the third generation has remarkable advantages compared with the first two generations, and the most basic advantage is that a circuit designer can freely select between a bipolar device with high-precision simulation, a CMOS device with high integration and a DMOS device as a power output stage. Particularly, the resistivity of the LDMOS transistor is reduced significantly while maintaining the same withstand voltage, so that an intelligent power integrated circuit (SPIC) of an integrated circuit technology that integrates a high-voltage power device, a low-voltage signal processing circuit, a peripheral interface, a detection circuit, a protection circuit, and the like into a single chip is becoming a trend.
As shown in fig. 1, the simple schematic diagram of a flyback power control chip integrated with a power MOS transistor, and the flyback power control chip and a peripheral flyback transformer, a resistor, a capacitor, etc. form a flyback converter, and the operating principle of the flyback converter is as follows: n is a radical ofP、NS、NAThe primary winding, the secondary winding and the auxiliary winding of the flyback transformer respectively, when the power MOS tube NM0 is conducted, the primary winding N is conductedPThe transformer is excited to store energy through current, and the secondary winding and the auxiliary winding are cut off at the moment; when the power tube NM0 is turned off, the voltage of the primary winding is cut off in the reverse direction and passes through the secondary winding NSAnd NAIs demagnetized, and NAAnd NSThe voltage of the windings is proportional to their number of coil turns and energy is predominantly passed through NSIs transmitted to the output end V of the flyback converterOUT. When V isOUTWhen the voltage of (E) is high, the differential amplifier EAIs greater than the reference voltage VrefIts output voltage VCDecrease, then the current sampling resistance RsenseThe passing current is reduced, the energy stored in the flyback transformer is reduced when the flyback transformer is excited, and correspondingly the energy is released to V when the flyback transformer is demagnetizedOUTIs reduced so that VOUTThe voltage is reduced; conversely, when VOUTWhen the voltage of the differential amplifier is lower than the reference voltage V, the input negative terminal of the differential amplifier is lower than the reference voltage VrefIts output voltage VCMore energy is transferred to the output end V through the flyback transformer under the control of the voltageOUTCausing it to increase. The above steps are repeated continuously and can be continued continuouslyGround regulated converter output voltage VOUTA stable value is reached. Sampling the output voltage of the converter, amplifying the error voltage of the output voltage with the reference voltage to generate a modulation voltage VCVoltage and V of power tube peak current sampling resistorCThe comparison results in the pulse Width of the power tube being turned on, which is the basic principle of pwm (pulse Width modulation) control, and its simplified diagram of fig. 2 is shown, since the output voltage is realized by the auxiliary winding NA of the transformer, and NA is common to the input of the converter, which is often called primary Side feedback psr (primary Side feedback). As shown in fig. 3, TL431, an optical coupler and other resistor capacitors form an isolation transconductance amplifier, and act with a pull-up resistor at the feedback pin FB of the chip to generate a pulse width modulation voltage VCTherefore, the differential amplifier EA functions in the PSR feedback mode, but has a voltage dividing resistor RFB1And RFB2Direct detection of V at secondary of isolated flyback converterOUTThus, the secondary side feedback is obtained.
The flyback transformer is designed according to the input voltage range of the converter, and if the input voltage is lower than the minimum input voltage, the magnetic core of the transformer enters saturation operation, and finally the converter is damaged. Therefore, the DC-DC converter often needs an input undervoltage protection function, and once the input voltage is lower than the set value of the input undervoltage protection, the converter stops working, so as to avoid the damage beyond the rated working range.
According to the basic principle of the flyback topology, the drain waveform of the converter during operation is shown in fig. 4, and the drain voltage of the power tube is the input voltage V of the converter during the degaussing phase of the transformerINVoltage V reflected by the transformerORAnd the peak voltage V generated by the leakage inductance of the transformerLEAKAGESum of three, thus the converter input voltage V in operationINThe maximum input value is the difference between the withstand voltage and the reflection voltage of the power tube NMO and the leakage inductance peak voltage. The control circuit and the power tube are integrated on the same wafer in a single chip integration mode, the power tube can only be an LDMOS (laterally diffused Metal Oxide Semiconductor) tube with a Lateral diffusion structure, and one volt is added every timeThe withstand voltage is more than that of a Vertical Double-diffused Metal Oxide Semiconductor (VDMOS) tube with a longitudinal diffusion structure, the withstand voltage of the power tube generally meets the requirement of normal operation for smaller on-resistance of the power tube, but the input voltage of the converter often exceeds the voltage of normal operation for a short time, such as surge generated by lightning stroke, and the like. Therefore, input overvoltage protection is often used to increase the input short-time spike voltage capability of the flyback converter, the input voltage exceeds the maximum rated value, the converter stops working, and then the converter input voltage VINThe maximum input value is equal to the withstand voltage of the power tube, and the input impulse voltage is prevented from damaging the converter as much as possible.
If two chip pins are used to implement the input under-voltage protection and the over-voltage protection, as shown in fig. 5, the formulas of the input voltage protection and the over-voltage protection are respectively as follows:
visible through resistance RUV2And RUV1Proportional programmable input undervoltage protection threshold, resistance ROV2And a resistance ROV1The proportion of (2) can program the threshold of the input overvoltage protection, but the scheme needs two pins and has more peripheral resistance, and each path of resistance consumes power. It is easy to think that the input under-voltage and the input over-voltage protection are multiplexed together through one pin, as shown in fig. 6, then the formulas of the input over-voltage and the input under-voltage protection are:
it can be seen that by setting the resistance ROU2And ROU1The proportion can also program the threshold value of input undervoltage and input overvoltage protection, but the resistance proportion determines the undervoltage and overvoltage values at the same time, and the undervoltage and overvoltage values cannot be programmed respectively.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a programmable control chip and a driving circuit thereof, which can solve the problem that the prior art can not program an input undervoltage protection threshold and an overvoltage protection threshold respectively, so that the control chip can only be suitable for occasions with fixed overvoltage and undervoltage proportionality coefficients and can not adapt to occasions with variable input ranges.
The purpose of the utility model is realized by the following technical scheme:
in a first aspect, the present invention provides a programmable control chip, including a unity gain amplifier, a first hysteresis comparator, an overvoltage protection comparison module, a PWM control circuit, and a first MOS transistor (NM 0); the input end of the gain amplifier and the negative input port of the first hysteresis comparator are respectively connected with an over \ under voltage multiplexing pin (OUP) of a programmable control chip, and the output end of the gain amplifier is connected with the input end of the overvoltage protection comparison module; a second reference voltage is input to a high-order positive input end of the first hysteresis comparator, a first reference voltage is input to a low-order positive input end of the first hysteresis comparator, and an output end of the first hysteresis comparator is connected with a first input end of the PWM control circuit; the output end of the overvoltage protection comparison module is connected with the second input end of the PWM control circuit, and the third input end of the PWM control circuit is connected with a feedback pin (FB) of the programmable control chip; the output end of the PWM control circuit is connected with the grid electrode of a first MOS tube (NM0), the drain electrode of the first MOS tube (NM0) is connected with the drain electrode pin (DRN) of the programmable control chip, and the source electrode of the first MOS tube (NM0) is grounded.
Further, the unity gain amplifier comprises an operational amplifier and a second MOS (PM1), wherein the inverting input end of the operational amplifier and the source electrode of the second MOS (PM1) are used as the input ends of the unity gain amplifier; a third reference voltage is input to a non-inverting input end of the operational amplifier, and an output end of the operational amplifier is connected with a grid electrode of the second MOS transistor (PM 1); the drain electrode of the second MOS tube (PM1) is used as the output end of the unit gain amplifier.
Further, the unity gain amplifier comprises a third MOS transistor (PM0), a second MOS transistor (PM1) and a third current source; a source electrode of the third MOS transistor (PM0) inputs a third reference voltage, a gate electrode of the third MOS transistor (PM0) is respectively connected with a drain electrode of the third MOS transistor (PM0), a gate electrode of the second MOS transistor (PM1) and one end of a third current source, and the other end of the third current source is grounded; the source electrode of the second MOS transistor (PM1) is used as the input end of the unit gain amplifier, and the drain electrode of the second MOS transistor (PM1) is used as the output end of the unit gain amplifier.
Further, the overvoltage protection comparison module comprises a schmitt shaper, a first current source, a second current source and a switch, wherein an input end of the schmitt shaper, one end of the first current source and one end of the switch are connected and serve as input ends of the overvoltage protection comparison module, and the other end of the first current source is grounded; the other end of the switch is connected with one end of a second current source, and the other end of the second current source is grounded; and the output end of the Schmidt shaper is used as the output end of the overvoltage protection comparison module and controls the on-off of the switch.
Furthermore, the overvoltage protection comparison module comprises a second hysteresis comparator and a third resistor, a negative input port of the second hysteresis comparator is connected with one end of the third resistor and serves as an input end of the overvoltage protection comparison module, and the other end of the third resistor is grounded; a fifth reference voltage is input to a high-order positive input terminal of the second hysteresis comparator, and a fourth reference voltage is input to a low-order positive input terminal of the second hysteresis comparator.
Further, the third MOS transistor (PM0) and/or the second MOS transistor (PM1) are/is replaced by PNP transistors.
In a second aspect, the utility model provides a programmable control chip driving circuit, which includes a first resistor and a second resistor, and further includes the programmable control chip, wherein one end of the second resistor is connected to an input voltage, and the other end of the second resistor is connected in series with the first resistor and then grounded; an over/under voltage multiplexing pin (OUP) is connected to a series node of the first resistor and the second resistor; setting an input under-voltage protection threshold value and an input under-voltage protection recovery threshold value of the programmable control chip by adjusting the resistance value ratio of the first resistor and the second resistor; and setting an input overvoltage protection threshold value and an input overvoltage protection recovery threshold value of the programmable control chip by adjusting the resistance value of the second resistor.
Further, the calculation formula of the input undervoltage protection threshold value is as follows:
the calculation formula of the input undervoltage protection recovery threshold value is as follows:
wherein R isOU1Is the resistance value of the first resistor, wherein ROU2Is the resistance value of the second resistor, VREF1Is a first reference voltage value, VREF2Is the second reference voltage value.
Further, the input overvoltage protection threshold is calculated by the following formula:
the calculation formula of the input overvoltage protection recovery threshold value is as follows:
wherein R isOU1Is the resistance value of the first resistor, wherein ROU2Is the resistance value of the second resistor, VREF3Is a third reference voltage value; i isREFIs the current value of the first current source, IHYSIs the current value of the second current source.
Further, the input overvoltage protection threshold is calculated by the following formula:
the calculation formula of the input overvoltage protection recovery threshold value is as follows:
wherein R isOU1Is the resistance of the first resistor, wherein ROU2Is the resistance value of the second resistor, VREF3Is a third reference voltage value, VREF4Is a fourth reference voltage value, VREF5Is the fifth reference voltage value.
According to the programmable control chip and the driving circuit thereof, only one chip pin is needed, and the input overvoltage protection threshold value and the input undervoltage protection threshold value can be programmed respectively by adjusting the resistance values of the periphery, so that the number of the chip pins is reduced, and a user can conveniently realize the programming control of the protection function of the chip in the periphery circuit.
Drawings
FIG. 1 is a schematic diagram of the PSR loop feedback basic function of a flyback converter control chip in the prior art;
FIG. 2 is a simplified schematic diagram of PSR loop feedback PWM control of a flyback converter control chip in the prior art;
FIG. 3 is a simplified schematic diagram of SSR loop feedback PWM control of a flyback converter control chip in the prior art;
FIG. 4 is a waveform of a drain of a power transistor during operation of a prior art flyback converter;
FIG. 5 is a schematic diagram of parameter adjustment achieved by using two pins of input under-voltage protection and input over-voltage protection in the prior art;
FIG. 6 is a schematic diagram of a prior art implementation of input under-voltage and input over-voltage using a multiplexing pin;
FIG. 7 is a control chip for implementing input over-voltage and under-voltage protection by using a single pin according to an embodiment of the present invention;
fig. 8 is a control chip for implementing input over-voltage and under-voltage protection by using a single pin according to a second embodiment of the present invention;
fig. 9 is a control chip for implementing input over-voltage and under-voltage protection by using a single pin according to a third embodiment of the present invention.
Detailed Description
The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification. It is to be understood that the described embodiments are merely illustrative of some, and not restrictive, of the embodiments of the disclosure. The disclosure may be embodied or carried out in various other specific embodiments, and various modifications and changes may be made in the details within the description without departing from the spirit of the disclosure. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
In view of the prior art, two pins are required for simultaneously realizing input overvoltage protection and undervoltage protection, or two protection threshold voltages cannot be respectively programmed in a mode of multiplexing one pin. Therefore, the utility model provides a new input overvoltage/input undervoltage pin multiplexing mode, only one chip pin is needed, and the threshold values of overvoltage protection and input protection can be programmed respectively by adjusting the peripheral resistance. The PSR feedback type converter adopted in the example is used to describe the operation principle of the input overvoltage/input undervoltage protection pin multiplexing of the present invention, but the present invention is not intended to limit the application range thereof, and can also be applied to SSR feedback and BUCK topology converters.
Example one
A programmable control chip drive circuit comprises a first resistor ROU1A second resistor ROU2And the programmable control chip comprises an over/under-voltage multiplexing pin OUP, a feedback pin FB and a drain electrode pin DRN. A second resistor ROU2One end of which is connected to an input voltage VINThe other end of the resistor is connected with a first resistor ROU1After being connected in series, the over/under voltage multiplexing pin OUP is connected to the series node of the first resistor and the second resistor. By adjusting the first resistance ROU1And a second resistor ROU2Setting the input undervoltage protection threshold and the input undervoltage protection recovery threshold of the programmable control chip by adjusting the resistance ratio of the second resistor ROU2The input overvoltage protection threshold value and the input overvoltage protection recovery threshold value of the programmable control chip are set.
Fig. 7 shows a bold solid frame, which is a programmable control chip for implementing input overvoltage protection and input undervoltage protection by using a multiplexing pin according to the present embodiment, and fig. 7 also shows a peripheral circuit of the control chip to form a simplified schematic diagram of the flyback converter in order to better understand the working principle of the control chip of the present invention. The control chip of the utility model is suitable for other power converters.
The programmable control chip of the embodiment further includes an operational amplifier, a MOS transistor PM1, a hysteresis comparator 1, a schmitt shaper, and a first current source I in addition to the pinsREFA second current source IHYSSwitch K1, PWM control circuit and MOS pipe NM 0. The inverting input end of the operational amplifier, the source electrode of the MOS tube PM1 and the negative input port of the hysteresis comparator 1 are respectively connected with the over \ under voltage multiplexing pin OUP, and the non-inverting input end of the operational amplifier inputs a reference voltage VREF3And the output end of the operational amplifier is connected with the grid electrode of the MOS transistor PM 1. High positive input of hysteresis comparator 1Input reference voltage VREF2The low-order positive input end of the hysteresis comparator 1 is inputted with a reference voltage VREF1The output end of the hysteresis comparator 1 is connected with the first input end of the PWM control circuit. The drains of the MOS transistors PM1 are respectively connected with a first current source IREFOne end of the schmitt shaper, an input end of the schmitt shaper, and one end of the switch K1. A first current source IREFAnd the other end of the same is grounded. The other end of the switch K1 is connected with a second current source IHYSAt one end of (1), a second current source IHYSAnd the other end of the same is grounded. The output end of the Schmidt shaper is connected with the second input end of the PWM control circuit and controls the switch K1 to be switched on or switched off. And a third input end of the PWM control circuit is connected with a feedback pin FB of the control chip. The output end of the PWM control circuit is connected to the gate of the MOS transistor NM0, the drain of the MOS transistor NM0 is connected to the drain pin DRN of the control chip, and the source of the MOS transistor NM0 is grounded.
The operational amplifier and the MOS transistor PM1 form a unity gain amplifier, the inverting input terminal of the operational amplifier and the source of the MOS transistor PM1 are used as the input terminal of the unity gain amplifier in the embodiment, and the drain of the MOS transistor PM1 is used as the output terminal of the unity gain amplifier.
Schmidt shaper, first current source IREFA second current source IHYSAnd a switch K1 forming an overvoltage protection comparison module, the input of the Schmidt shaper, the first current source IREFAnd one end of the schmitt shaper is connected with one end of the switch K1 and serves as an input end of the overvoltage protection comparison module, and an output end of the schmitt shaper serves as an output end of the overvoltage protection comparison module.
The working principle of the control chip and the control circuit thereof is as follows:
when the voltage of the over \ under voltage multiplexing pin OUP is less than VREF1When the input voltage is low, the hysteresis comparator 1 outputs an input undervoltage protection signal to the PWM control circuit, and the MOS tube NM0 is forbidden to be switched on;
when the voltage of the over \ under voltage multiplexing pin OUP is larger than VREF2When the power is switched on, the hysteresis comparator 1 outputs and inputs a non-undervoltage protection signal to the PWM control circuit to allow the power tube NM0 to be switched on;
when the voltage of the over \ under voltage multiplexing pin OUP is larger than VREF3At first, the arithmetic is putThe unit gain amplifier formed by the amplifier and the MOS tube PM1 starts to absorb the current I from the over/under voltage multiplexing pin OUP pinclampThe current passes through PM1 and then passes through current source IREFAnd IHYSAnd flows into the ground. In IclampWhen the voltage of the over/under voltage multiplexing pin OUP pin is less than the sum of the two current sources, the voltage of the over/under voltage multiplexing pin OUP pin is clamped and is about VREF3. When I isclampWhen the current is larger than the sum of two current sources, the input voltage of the Schmidt shaper increases to cause the logic voltage output by the Schmidt shaper to reverse, indicating input overvoltage protection, inhibiting the power NM0 from being turned on, and turning off the current source IHYS；
After input overvoltage protection has taken place, IHYSHas been turned off, so that only when the current I isclampIs again less than IREFWhen the input voltage of the schmitt shaper is dropped, the output logic voltage of the schmitt shaper is restored, which indicates that the input is not over-voltage, and the power tube NM0 is allowed to be switched on;
reference voltage VREF3＞VREF2＞VREF1OUP voltage of over/under voltage multiplexing pin exceeds VREF3Just start to generate a clamping current IclampAnd the influence of the clamping current on the input undervoltage protection threshold is avoided.
According to the working principle, the OUP voltage of the over/under-voltage multiplexing pin is less than VREF3When there is no clamping current IclampThen, it is easy to calculate that the input undervoltage protection threshold and the input undervoltage protection recovery threshold voltage are respectively:
that is: when the converter input voltage VINLess than VINUVP(OFF)When the input voltage is low, the chip stops turning on the power tube NM 0; when V isINIs again greater than VINUVP(ON)The undervoltage protection logic is disabled. FromThe above two formulas can be seen that only R is changedOU1And ROU2The input undervoltage protection threshold and the protected recovery threshold voltage can be programmed separately.
When OUP voltage of multiplexing pin is larger than VREF3But IclampHas not exceeded the current source IREFAnd IHYSIn sum, the OUP voltage at the pin is only slightly larger than V due to the clamping effect of the unit gain amplifier including the operational amplifier and the MOS transistor PM1REF3And may be considered to be approximately equal. As shown in FIG. 7, I2Is through a resistance ROU2Current of (I)1Is through a resistance ROU1From the current of (d), I can be calculatedclampThe size of (A) is as follows:
and then respectively another IclampIs equal to IREF+IHYSAnd IREFThe input over-voltage protection threshold and the input over-voltage protection recovery threshold voltage can be calculated as follows:
as can be seen from the above, ROU2And ROU1After the proportion of (A) is determined, R can also be passedOU2The input overvoltage protection threshold and the recovery threshold voltage after protection are programmed according to the resistance value of the resistor.
Example two
First embodiment, a unit gain amplifier comprising an operational amplifier and a MOS transistor PM1 is adopted to clamp the voltage of a multiplexing pin to follow a reference voltage VREF3Clamping the absorbed current IclampComparing with reference power supply to determine converter input voltage VINWhether or not there is an overpressure. Benefits of using operational amplifiersThe method comprises the following steps: 1. reference voltage VREF3The input end does not need to provide current, and the voltage source can be obtained without adding extra circuits in the integrated circuit design; 2. the amplification factor of the operational amplifier is large, and the clamping voltage of the OUP can accurately follow the reference voltage VREF3。
However, VREF3Can be the voltage source existing in the chip, such as the power supply of the chip control circuit, the clamping voltage of OUP and VREF3When the deviation is small, for example, the deviation is 0.2V, if the input overvoltage protection threshold is 50V, the influence on the precision is about 0.4 percent, which is far less than the withstand voltage precision of a power MOS tube by 10 to 30 percent, so even if the clamping voltage and the V are equalREF3And the overvoltage protection can still effectively protect the power tube due to small deviation. Thus, a simpler clamp circuit of the second embodiment can be used, as shown in fig. 8.
The difference from the first embodiment is that: the internal circuit structure of the unity gain amplifier is changed, and the unity gain amplifier comprises a MOS transistor PM0, a MOS transistor PM1 and a third current source I in the embodimentB. Source input reference voltage V of MOS pipe PM0REF3The grid electrode of the MOS transistor PM0 is respectively connected with the drain electrode of the MOS transistor PM0, the grid electrode of the MOS transistor PM1 and the third current source IBTo a third current source IBAnd the other end of the same is grounded. The source electrode of the MOS transistor PM1 is connected with the over \ under voltage multiplexing pin OUP, and the drain electrode of the MOS transistor PM1 is connected with the input end of the Schmidt shaper and the third current source IREFTo the end of (a). In this embodiment, the source of the MOS transistor PM1 is used as the input terminal of the unity gain amplifier, and the drain of the MOS transistor PM1 is used as the output terminal of the unity gain amplifier.
Except for the unity gain amplifier, other components and connection relationships of the second embodiment are the same as those of the first embodiment, and are not described herein again.
The operating principle of the unity gain amplifier of the second embodiment is as follows: note that the width of the P-type channel MOS transistor PM0 is W, the channel length is L, and the width-length ratio of the MOS transistor PM0 to the MOS transistor PM1 is 1: m, a bias current source I provided for the MOS transistor PM0BThe current at PM1 is equal to IREF+IHYSThe time Schmidt shaper sends out an overvoltage protection signal, then the MOS transistors PM0 andthe source-to-gate voltage difference of the MOS transistor PM1 is related to the current,
wherein, VSG0Is the voltage difference between the source and the gate of the MOS transistor PM0, VSG1Is the voltage difference between the source and the gate of the MOS transistor PM1, upIs the hole mobility, COXIs a unit area gate oxide capacitance, VTHPIs the MOS transistor threshold voltage. From the equations (10) and (11), V is determinedSG0And VSG1Equally, the size ratios and currents of PM0 and PM1 should be designed to satisfy the following relationship, IREF+IHYS＝m*IB. Conversely, the circuit design satisfies this equation, then VSG0＝VSG1Since the gates of PM0 and PM1 are connected together, the source voltages of PM0 and PM1 are equal, i.e., the clamping voltage of OUP for over-voltage protection is equal to VREF3So that the over-voltage protection threshold voltage is the same as described in embodiment one. When the OUP voltage is low, the PM1 is also in an off state, and no clamping current I is generatedclampTherefore, the input undervoltage protection function is not affected, and the input undervoltage protection threshold voltage is the same as that described in the first embodiment, which is not described herein again.
EXAMPLE III
As shown in fig. 9, the third embodiment is a circuit diagram of the third embodiment, which is different from the first and second embodiments in that the internal circuit of the overvoltage protection comparison module is changed to change the clamp current IclampIn-chip resistor R0Up-conversion to a voltage, passing through a hysteresis comparator 2 and a reference voltage VREF5And VREF4Comparison, VREF5＞VREF4。
The overvoltage protection comparison module of the embodiment comprises a hysteresis comparator 2 and a third resistor R0Retardation ratioNegative input port of comparator 2 and third resistor R0One end of the third resistor R is connected with and used as the input end of the overvoltage protection comparison module0The other end of the first and second electrodes is grounded; the high-order positive input end of the hysteresis comparator 2 is inputted with a fifth reference voltage VREF5The fourth reference voltage V is input to the low-bit positive input terminal of the hysteresis comparator 2REF4。
IclampThe generation principle of the method is the same as that of the embodiment, and the protection working principle is as follows:
when R is0Voltage of greater than VREF5The time lag comparator 2 sends an input overvoltage signal to forbid the power tube NM0 from being turned on;
when R isOIs again less than the reference voltage VREF4The output voltage of the time lag comparator 2 is restored to the logic state that the input voltage is not over-voltage, and the power tube NM0 is allowed to be switched on;
will Iclamp*R0＝VREF5And Iclamp*R0＝VREF4Substituting equation (7) can obtain the input overvoltage protection threshold and the recovery threshold respectively as follows:
input undervoltage protection IclampSince 0, the input undervoltage protection threshold and its recovery threshold are still determined by expressions (5) and (6). It can be seen that by ROU2And ROU1The proportional coefficient of the voltage-loss protection circuit can be programmed to input an undervoltage protection threshold value and a recovery threshold value thereof, and then combined with formulas (12) and (13), the undervoltage protection circuit passes through a resistor ROU2To program the input over-voltage protection threshold and its recovery threshold.
The P-channel MOS transistors PM0 and PM1 may be replaced by P-type transistors.
The programmable control chip of the present invention is not limited to the above three embodiments, and those skilled in the art can implement the present inventionExamples provided that the adjustment by adjusting the first resistance R can be achievedOU1And a second resistor ROU2Setting an input undervoltage protection threshold value and an input undervoltage protection recovery threshold value of the control chip; by adjusting the second resistance ROU2The functions of setting the input overvoltage protection threshold value and the input overvoltage protection recovery threshold value of the control chip are all within the protection scope of the utility model.
The above description is for the purpose of illustrating embodiments of the utility model and is not intended to limit the utility model, and it will be apparent to those skilled in the art that any modification, equivalent replacement, or improvement made without departing from the spirit and principle of the utility model shall fall within the protection scope of the utility model.
Claims (7)
1. A programmable control chip is characterized by comprising a unity gain amplifier, a first hysteresis comparator, an overvoltage protection comparison module, a PWM control circuit and a first MOS (metal oxide semiconductor) transistor (NM 0); the input end of the gain amplifier and the negative input port of the first hysteresis comparator are respectively connected with an over \ under voltage multiplexing pin (OUP) of a programmable control chip, and the output end of the gain amplifier is connected with the input end of the overvoltage protection comparison module; a second reference voltage is input to a high-order positive input end of the first hysteresis comparator, a first reference voltage is input to a low-order positive input end of the first hysteresis comparator, and an output end of the first hysteresis comparator is connected with a first input end of the PWM control circuit; the output end of the overvoltage protection comparison module is connected with the second input end of the PWM control circuit, and the third input end of the PWM control circuit is connected with a feedback pin (FB) of the programmable control chip; the output end of the PWM control circuit is connected with the grid electrode of a first MOS tube (NM0), the drain electrode of the first MOS tube (NM0) is connected with the drain electrode pin (DRN) of the programmable control chip, and the source electrode of the first MOS tube (NM0) is grounded.
2. The programmable control chip of claim 1, wherein the unity gain amplifier comprises an operational amplifier and a second MOS transistor (PM1), wherein an inverting input of the operational amplifier and a source of the second MOS transistor (PM1) are used as input terminals of the unity gain amplifier; a third reference voltage is input to a non-inverting input end of the operational amplifier, and an output end of the operational amplifier is connected with a grid electrode of the second MOS transistor (PM 1); the drain electrode of the second MOS tube (PM1) is used as the output end of the unit gain amplifier.
3. The programmable control chip of claim 1, wherein the unity gain amplifier comprises a third MOS transistor (PM0), a second MOS transistor (PM1), and a third current source; a source electrode of the third MOS transistor (PM0) inputs a third reference voltage, a gate electrode of the third MOS transistor (PM0) is respectively connected with a drain electrode of the third MOS transistor (PM0), a gate electrode of the second MOS transistor (PM1) and one end of a third current source, and the other end of the third current source is grounded; the source electrode of the second MOS transistor (PM1) is used as the input end of the unit gain amplifier, and the drain electrode of the second MOS transistor (PM1) is used as the output end of the unit gain amplifier.
4. The programmable control chip according to any one of claims 1 to 3, wherein the over-voltage protection comparison module comprises a Schmidt shaper, a first current source, a second current source and a switch, wherein an input terminal of the Schmidt shaper, one terminal of the first current source and one terminal of the switch are connected and serve as input terminals of the over-voltage protection comparison module, and the other terminal of the first current source is grounded; the other end of the switch is connected with one end of a second current source, and the other end of the second current source is grounded; and the output end of the Schmidt shaper is used as the output end of the overvoltage protection comparison module and controls the on-off of the switch.
5. The programmable control chip according to any one of claims 1 to 3, wherein the overvoltage protection comparison module comprises a second hysteresis comparator and a third resistor, a negative input port of the second hysteresis comparator is connected with one end of the third resistor and serves as an input end of the overvoltage protection comparison module, and the other end of the third resistor is grounded; a fifth reference voltage is input to a high-order positive input terminal of the second hysteresis comparator, and a fourth reference voltage is input to a low-order positive input terminal of the second hysteresis comparator.
6. The programmable control chip of claim 3, wherein the third MOS transistor (PM0) and/or the second MOS transistor (PM1) are each replaced by a PNP transistor.
7. A programmable control chip drive circuit, comprising a first resistor and a second resistor, characterized by further comprising the programmable control chip of any one of claims 1 to 6, wherein one end of the second resistor is connected with an input voltage, and the other end is connected with the first resistor in series and then grounded; an over/under voltage multiplexing pin (OUP) is connected to a series node of the first resistor and the second resistor; setting an input under-voltage protection threshold value and an input under-voltage protection recovery threshold value of the programmable control chip by adjusting the resistance value ratio of the first resistor and the second resistor; and setting an input overvoltage protection threshold value and an input overvoltage protection recovery threshold value of the programmable control chip by adjusting the resistance value of the second resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220176381.9U CN216718968U (en) | 2022-01-21 | 2022-01-21 | Programmable control chip and drive circuit thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220176381.9U CN216718968U (en) | 2022-01-21 | 2022-01-21 | Programmable control chip and drive circuit thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216718968U true CN216718968U (en) | 2022-06-10 |
Family
ID=81872827
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220176381.9U Active CN216718968U (en) | 2022-01-21 | 2022-01-21 | Programmable control chip and drive circuit thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216718968U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117459052A (en) * | 2023-11-15 | 2024-01-26 | 北京中科格励微科技有限公司 | Output circuit of I2C interface circuit and I2C interface circuit |
-
2022
- 2022-01-21 CN CN202220176381.9U patent/CN216718968U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117459052A (en) * | 2023-11-15 | 2024-01-26 | 北京中科格励微科技有限公司 | Output circuit of I2C interface circuit and I2C interface circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7777553B2 (en) | Simplified switching circuit | |
| US7099163B1 (en) | PWM controller with constant output power limit for a power supply | |
| WO2020038016A1 (en) | Short-circuit protection detection circuit and detection method | |
| US4652809A (en) | Switched regulator circuit having an extended duty cycle range | |
| WO2018006769A1 (en) | Hysteresis power supply circuit | |
| CN113067469B (en) | Quick response loop compensation circuit, loop compensation chip and switching power supply | |
| CN107943182B (en) | Band gap reference start-up circuit | |
| US20100302813A1 (en) | Dual-mode constant load control circuits and associated methods | |
| CN216718968U (en) | Programmable control chip and drive circuit thereof | |
| CN102141816A (en) | Current-mode current induction circuit externally connected with MOS (metal oxide semiconductor) and method for realizing current mode | |
| Dutta et al. | A novel predictive phase shift controller for bidirectional isolated dc to dc converter for high power applications | |
| CN113434002B (en) | High-voltage low dropout regulator (LDO) circuit with clamping current-limiting function | |
| Biswas et al. | GaN based switched capacitor three-level buck converter with cascaded synchronous bootstrap gate drive scheme | |
| CN109343644A (en) | A kind of automatic adjustment current-limiting protection circuit | |
| TWI696339B (en) | Switching power converter circuit and cascoded transistor circuit thereof | |
| CN114337304A (en) | Control chip and built-in MOS tube driving speed control method thereof | |
| CN111917307B (en) | Soft start circuit based on current limiting of current mirror | |
| CN102664516A (en) | Switching power supply for driving MOS (Metal Oxide Semiconductor) tube | |
| WO2024060614A1 (en) | Circuit for sampling target current passing through target resistor | |
| CN207677621U (en) | A kind of reference voltage output device and Switching Power Supply | |
| JP2005151793A (en) | Capacitor voltage measurement device and method | |
| US11336191B1 (en) | Power supply device with low loss | |
| CN205232030U (en) | Input undervoltage protection circuit and switching power supply | |
| CN114421745A (en) | Depletion type power circuit and cascade type leakage current matching circuit | |
| CN208673174U (en) | A kind of constant-current device applied to AC-DC system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |