CN2165575Y - Acquisition transmitter for monitoring wave carrier machine - Google Patents

Abstract

The utility model belongs to an automatic monitoring device of an electric power dispatching communication network. 64 monitoring points of a communication device which is monitored are connected with 64 input interface circuits of the device; output end feet of the 64 input interface circuits are correspondingly connected with 64 changeover switches; the 64 changeover switches which are controlled by a control processor are connected with the control processor by a common transformation transferring circuit. The utility model has the advantages that a communication device can be monitored thoroughly; the accuracy of fault diagnosis is high; the 64 input interface circuits are universal; circuits are simple; the whole device is only provided with a set of transformation transferring circuits; automatic scale can be realized; labor intensity for operators can be lightened at the time of installation.

Description

Acquisition transmitter for monitoring wave carrier machine

The utility model belongs to the automated watch-keeping facility of electric power conduct and communication net.

Power line carrier is the common equipment in the communication system of power grids, is used for it is monitored to become with the collection of failure diagnosis sending device, comprises mainly usually that Acquisition Circuit (being input interface circuit), multipath conversion are opened to send and transmission circuit three parts.Each monitoring point (simulation) signal that enters interface circuit is varied, cause existing scheme in the design of input interface circuit and transmission circuit, to be forced to take to treat with a certain discrimination processing method respectively, that is: at first the monitoring point signal is divided into several classes by amplitude, frequency or polarity, designs special input interface circuit and transmission circuit respectively for each class signal then.Because the concrete design during design is different with the sorting technique to signal, therefore in fact be difficult to describe with a simple circuit form.Existing scheme needs multiple input interface circuit and multiple transmission circuit, therefore the circuit design difficulty is big, each side such as cost and volume factor has all finally limited the expansion of input way, can't carry out comprehensive monitoring to every communication equipment at all, and its failure diagnosis accuracy is relatively poor.Be that an input signal from each monitoring point carries out the normalization on the amplitude during installation, palpus pointwise gain pre-adjustment (calibration).It is not only wasted time and energy, and high to the calibration precision requirement, is directly restricting the precision of each point monitoring numerical value.

The purpose of this utility model is the shortcoming at above-mentioned existence, provides a kind of input interface circuit and transmission circuit all general, and circuit is simple, but auto-scaling, and the higher collection of failure diagnosis accuracy becomes send device.

The purpose of this utility model is to adopt following measure to realize: 64 monitoring points of monitored communication equipment, with 64 road input interface circuits of this device join (referring to Fig. 1), corresponding 64 road change over switches that connect of the output pin of 64 road input interface circuits, be controlled by that 64 road change over switches of processor controls are each connects one the tunnel, through public transmission circuit to processor controls.It is characterized in that analog signal from 64 monitoring points of communication equipment, link to each other with the input interface circuit separately that constitutes by two resistance in this device respectively, input interface circuit output is connected to two cutter spacing Z and the Y of 64 road change over switch U00～U63 respectively, control end A, the B that analog switch U00～U63 is every, C tandem and be coupled to the decoding output of decoder component U100～U103, decoder component U100～U104 data input pin pin connects processor controls reconnaissance sign indicating number output port SC; The Z0 of every analog switch, Y0 meet Y, Z respectively among U00～U63, the analog switch U200 that is connected to public transmission circuit after the throw-bit side Z1 tandem of 64 road change over switch U00～U63 throws a Y1 and X0, the cutter spacing X of U200 send analog switch U201 to throw the inverting input of a Y1, Y0 and X0 and operational amplifier A 1, amplifier A1 output and analog switch U201 cutter spacing Y, X are divided into two-way after joining, and one the tunnel meets analog switch U202 throws a Y3, X3; Another road is through resistance pressure-dividing network R12, R13 meets the X0 that throws of U202, X1, X2, Y0, Y1, Y2, U202 cutter spacing Y, X connects amplifier A2 in-phase input end through resistance R 16, the A2 output connects amplifier A3, the in-phase input end of A4, A3, the A4 output is thrown a Z0 and Y0 and A3 through what transistor T1 and T2 met analog switch U203 respectively, the inverting input of A4, amplifier A10, A11 all constitutes voltage follower, two outputs send analog switch U203 to throw a Z1 and Y1 respectively, U203 cutter spacing Z and Y meet amplifier A5 respectively, the in-phase input end of A6 and through capacitor C 2, C3 respectively cross-over connection its throw a Z1 and Y1, A5, inverting input and the in-phase input end of amplifier A7 sent in the output of A6 respectively through R22 and R23, the reference voltage input terminal of D/A U207 is sent in the output one tunnel of A7, another road is through divider resistance R26, R27 send the in-phase input end of amplifier A8, the current output terminal of D/A U207 connects the inverting input of amplifier A9, the output of amplifier A9 is connected to the inverting input of amplifier A8 through R28, the cutter spacing Z of the output termination analog switch U200 of A8, two of U200 throw a Z0 and Z1 and send A/D converter in-phase input end Vi+ and inverting input Vi-in the processor controls through resistance R 30 and R31 respectively; NOR gate U205 and U206 constitute rest-set flip-flop, the trigger end of the U206 one side tandem processor controls secondary latch pulse output CLK that links to each other with control end A, B, the C of analog switch U200 wherein, the data input pin of D/A U207 meets the gain code output port SA of processor controls, and control end A, the B of analog switch U201 joins with control end A, the B of analog switch U202 respectively and be connected to the gear sign indicating number output port SB of processor controls.

The utility model has the advantages that: can realize comprehensive monitoring to communication equipment, 64 input interface circuits are general, and circuit is simple and direct; The transmission circuit of whole device has only a cover, can realize auto-scaling, alleviates the labour intensity of operator when installing.It is simple to have circuit structure, to the failure diagnosis accuracy advantages of higher of communication equipment.

Description of drawings:

Fig. 1 is a circuit structure block diagram of the present utility model;

Fig. 2 is circuit theory diagrams of the present utility model;

Fig. 3 carries out the software reduction block diagram of auto-scaling for the control and treatment device makes the utility model;

The software reduction block diagram that Fig. 4 monitors the utility model for the control and treatment device.

From the solid box of Fig. 1 as seen, the utility model comprises 64 road input interface circuits, 64 road change over switches, public transmission circuit and decoder etc.; Frame of broken lines is monitored communication equipment (left frame) and processor controls (right frame).Symbol among Fig. 2 is the equipment under test signal ground, is equipment under test frame ground, for digitally, is simulation ground.

Its operation principle is:

64 road input interface circuits are by R00A, R00B～R63A, R63B constitutes, two resistance on every road constitute a voltage/current converter, analog signal from the monitoring point is become corresponding with it electric current by voltage, decoded device U100～U104(model is 74HC139 and CD4514 in 64 road change over switches then) output of the path analoging switch chosen, this moment, analog switch U200(model was CD4053) X0 and X connection, it is OP-27 that this electric current send amplifier A1(model) become voltage signal, and its gain is CD4052 with analog switch U201(model) interior contacts break-make situation relevant, 10 times of attenuation networks that the A1 output signal send that R12 and R13 form and be CD4052 through analog switch U202(model) to give amplifier A2(model be OP-37) 10 times of in-phase amplifiers constituting, the on off operating mode that whether depends on the U202 interior contacts for the A1 attenuated output signal, therefore to have four gains (being gear) rank for selected monitoring point input signal under the gear sign indicating number control from port SB be 0.04 to the output signal of A2,0.4,4,40, so input signal for 5mVp-p to 50Vp-p, all can find a suitable gear, the amplitude output signal of A2 is dropped between the 0.2Vp-p to 2Vp-p.This signal is given by A3, the A4(model is OP-37), the U203(model is CD4053), A5, A6, the A7(model is OP-07), U204～U206(model is CD4001) and A10, the A11(model is TL072) fast quick-recovery ac/dc/absolute value translation circuit of constituting, A4 wherein, T2, the positive peak sampling that the Y0-Y of C3 and U203 finishes the A2 output signal keeps, A3, T1, the negative peak sampling that the Z0-Z of C2 and U203 finishes the A2 output signal keeps, form and A3, the A4 input signal just, negative peak is just corresponding, negative dc voltage, and give the in-phase input end of A6 and A5 respectively by the Y of U203 and Z output, A5, A6, A7 has been connected into the differential amplifier of high impedance input, so for AC signal, output at A7 can obtain and A3, the corresponding positive voltage of A4 input signal peak-to-peak value, and, obtain and A3 at the output of A7 for direct current signal, the corresponding absolute value of A4 input voltage.A10 and A11 all are connected into voltage follower, export small positive voltage and negative voltage respectively, are used to improve the sensitivity of circuit when the input small-signal, to improve the linearity of ac/dc/absolute value circuit.The rest-set flip-flop that U205 and U206 form is used to control the interior contacts of U203, utilize the rising edge of secondary latch pulse CLK to make foregoing circuit be in ac/dc/absolute value transition state, and the trailing edge that utilizes the EOC index pulse INTR of A/D converter is released the voltage on C2, the C3 rapidly, for getting ready next monitoring point.Amplifier A8, A9(model are OP-07) and D/A U207(model be DAC0832) constitute the window type gain-programmed amplifier, it is gain controlled in the gain controlling sign indicating number of being sent into U207 data input pin D0～D7 by processor controls port SA, the voltage gain of this part circuit changes between 1.25 times and 12.5 times, has 256 grades.So for the 5mVp-p～50Vp-p AC signal of monitoring point input or ± 5mV～± direct current signal of 50V, utilize processor controls port SA, SB to send suitable gear control code and gain controlling sign indicating number here, finally can make the direct voltage of A8 output very approaching+2.5V, finished auto-scaling, its slight error is then utilized the software correction of control and treatment device.The effect of U200 is each total null offset in the bucking circuit, when under secondary latch pulse CLK control, the A of U200, B, its inner X1, Y1, Z1 communicated with X, Y, Z respectively when C was logical one, gone into ground from the signal of monitoring point by the Y1-Y short circuit this moment, the inverting input of A1 is gone into ground by connecing certain road input interface circuit reconfiguration through R1, therefore A8 output is the null offset of circuit own, and is sent to the inverting input Vi-of A/D converter in the processor controls by Z-Z1, the R31 of U200; As A, the B of U200, when C is logical zero, the Z1 of U200 and Z disconnect, but because the maintenance effect of C5, A/D converter inverting input Vi-still remains on the voltage value of above-mentioned null offset, this moment, Z0 communicated with Z, the collection that has the same zero point drift of A8 output become send output voltage, give the in-phase input end Vi+ of analog to digital converter, offset null offset total in the circuit in the transformation result of A/D converter thereby make through resistance R 30.

Support the processor controls of the utility model work can select general purpose single sheet developing engine for use, also can be to carrying out specialized designs, its software configuration mainly is made of following two large divisions.Fig. 3 is installed on the monitored equipment when the utility model for the first time, the software reduction block diagram of processor controls when each monitoring point signal is carried out auto-scaling, at first the reconnaissance control code is latching to data-out port SC after the initialization, then gain controlling sign indicating number and gear control code are latching to data-out port SA and SB respectively, restart A/D converter, read the A/D transformation result after the end to be converted, judge then whether this result has approached the pairing digital quantity of setting of 2.5V, as approaching then this result is calibrated sign indicating number as this point, gain controlling sign indicating number and gear control code together with this moment deposit the software form in, and this some calibration finishes; As do not approach then and revise gain controlling sign indicating number or gear sign indicating number by specific rule, and repeat said process, until satisfying the condition of approaching.When some calibration finishes, and after the calibration sign indicating number that will put, gain controlling sign indicating number and gear control code deposit the software form in, the reconnaissance control code is added 1, and gain controlling sign indicating number and gear control code are put initial value.Carry out the calibration of next monitoring point then, so circulation finishes Automatic Program steering monitoring software section until whole some calibrations.

Fig. 4 is the software reduction block diagram that the utility model enters processor controls behind the normal monitoring state.Sensing by the reconnaissance control code after the initialization accesses the gear control code of this point, gain controlling sign indicating number from the software form, and be latching to data-out port SB, SA, SC respectively together with the reconnaissance control code, start A/D converter A/D then, after the end to be converted, read the A/D transformation result.Calculate relative error and absolute error between A/D transformation result and this deposit the software form in when calibration the calibration sign indicating number afterwards.If error transfinites, then send alarm signal and send Reflector; Do not transfinite then to descend a bit as error, and repeat said process, finish, will carry out the work that repeats in next cycle after the zero clearing of reconnaissance control code until whole monitoring points.

Claims (1)

1, a kind of collection transmitter of monitoring carrier terminal equipment, has Acquisition Circuit, circuit is closed in multicircuit switch and change, it is characterized in that analog signal from 64 monitoring points of communication equipment, link to each other with the input interface circuit separately that constitutes by two resistance in this device respectively, input interface circuit output is connected to two cutter spacing Z and the Y of 64 road change over switch U00～U63 respectively, the control end A that analog switch U00～U63 is every, B, C tandem and be coupled to the decoding output of decoder component U100～U103, decoder component U100～U104 data input pin pin connects processor controls reconnaissance sign indicating number output port SC; The Z0 of every analog switch, Y0 meet Y, Z respectively among U00～U63, the analog switch U200 that is connected to public transmission circuit after the throw-bit side Z1 tandem of 64 road change over switch U00～U63 throws a Y1 and X0, the cutter spacing X of U200 send analog switch U201 to throw the inverting input of a Y1, Y0 and X0 and operational amplifier A 1, amplifier A1 output and analog switch U201 cutter spacing Y, X are divided into two-way after joining, and one the tunnel meets analog switch U202 throws a Y3, X3; Another road is through resistance pressure-dividing network R12, R13 meets the X0 that throws of U202, X1, X2, Y0, Y1, Y2, U202 cutter spacing Y, X connects amplifier A2 in-phase input end through resistance R 16, the A2 output connects amplifier A3, the in-phase input end of A4, A3, the A4 output is thrown a Z0 and Y0 and A3 through what transistor T1 and T2 met analog switch U203 respectively, the inverting input of A4, amplifier A10, A11 all constitutes voltage follower, two outputs send analog switch U203 to throw a Z0 and Y0 and A3 respectively, the inverting input of A4, amplifier A10, A11 all constitutes voltage follower, two outputs send analog switch U203 to throw a Z1 and Y1 respectively, U203 cutter spacing Z and Y meet amplifier A5 respectively, the in-phase input end of A6 and through capacitor C 2, C3 respectively cross-over connection its throw a Z1 and Y1, A5, inverting input and the in-phase input end of amplifier A7 sent in the output of A6 respectively through R22 and R23, the reference voltage input terminal of D/A U207 is sent in the output one tunnel of A7, another road is through divider resistance R26, R27 send the in-phase input end of amplifier A8, the current output terminal of D/A U207 connects the inverting input of amplifier A9, the output of amplifier A9 is connected to the inverting input of amplifier A8 through R28, the cutter spacing Z of the output termination analog switch U200 of A8, two of U200 throw a Z0 and Z1 and send A/D converter in-phase input end Vi+ and inverting input Vi-in the processor controls through resistance R 30 and R31 respectively; NOR gate U205 and U206 constitute rest-set flip-flop, the trigger end of the U206 one side tandem processor controls secondary latch pulse output CLK that links to each other with control end A, B, the C of analog switch U200 wherein, the data input pin of D/A U207 meets the gain code output port SA of processor controls, and control end A, the B of analog switch U201 joins with control end A, the B of analog switch U202 respectively and be connected to the gear sign indicating number output port SB of processor controls.

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