CN216531252U - Radio frequency circuit and power amplifier circuit - Google Patents
Radio frequency circuit and power amplifier circuit Download PDFInfo
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- CN216531252U CN216531252U CN202123255050.9U CN202123255050U CN216531252U CN 216531252 U CN216531252 U CN 216531252U CN 202123255050 U CN202123255050 U CN 202123255050U CN 216531252 U CN216531252 U CN 216531252U
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Abstract
The utility model discloses a radio frequency circuit, which comprises a matching circuit and a power amplifying circuit, wherein the matching circuit is connected with the power amplifying circuit, the matching circuit comprises at least one LC circuit, and the matching circuit is configured to suppress harmonic signals in radio frequency signals.
Description
Technical Field
The present invention relates to the field of radio frequency technologies, and in particular, to a radio frequency circuit and a power amplifier circuit.
Background
The matching circuit is an important component in a radio frequency circuit, and the main function of most matching circuits is to meet the impedance matching requirement of the input end or the output end of the power amplifier. In order to ensure the maximum transmission power of the power amplifier, it is often necessary to filter out harmonic signals mixed with the radio frequency signals in the circuit. At present, the harmonic signals mixed with the radio frequency signals in the circuit are filtered mainly by arranging a filter circuit at the output end. However, the filter circuit often includes components with a large occupied area, so that the occupied area of the whole radio frequency circuit is large, which is not favorable for the integrated design of the radio frequency circuit, and further limits the application range of the radio frequency circuit.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides a radio frequency circuit, which aims to solve the problem that the radio frequency circuit cannot give consideration to both area and performance.
A radio frequency circuit comprising a matching circuit and a power amplification circuit, the matching circuit and the power amplification circuit connected, the matching circuit comprising at least one LC circuit, the matching circuit configured to suppress harmonic signals in a radio frequency signal.
Further, the matching circuit includes a first node configured to receive a radio frequency input signal and a second node connected to the input node of the power amplification circuit, and is configured to suppress harmonic signals in the radio frequency input signal; or, the first node is configured to be connected to an output node of the power amplification circuit, and the second node is configured to output a radio frequency amplified signal; the matching circuit is configured to suppress harmonic signals in the radio frequency amplified signal.
Further, the LC circuit includes a first LC series circuit, a second LC series circuit, and a first LC parallel circuit, a first end of the first LC series circuit is coupled to the first node, a second end of the first LC series circuit is coupled to the second node;
the first LC series circuit comprises a first inductor and a second capacitor, a first end of the first inductor is coupled to the first node, a second end of the first inductor is connected with a first end of the second capacitor, and a second end of the second capacitor is coupled to the second node;
a first end of the second LC series circuit is connected with a first end of the second capacitor, and a second end of the second LC series circuit is grounded;
and the first end of the first LC parallel circuit is connected with the second end of the second capacitor, and the second end of the first LC parallel circuit is grounded.
Further, the LC circuit comprises a first LC series circuit and a first LC parallel circuit, the matching circuit further comprises a first capacitor,
a first end of the first LC series circuit is coupled to a first node of the matching circuit, a second end of the first LC series circuit is coupled to a second node of the matching circuit, a first end of the first LC parallel circuit is coupled to a second end of the first LC series circuit, and a second end of the first LC parallel circuit is grounded;
the first LC series circuit comprises a first inductor and a second capacitor connected in series;
a first end of the first inductor is coupled to the first node, a second end of the first inductor is connected with a first end of the second capacitor, and a second end of the second capacitor is coupled to the second node;
the first LC parallel circuit comprises a second inductor and a third capacitor which are connected in parallel;
a first terminal of the third capacitor is connected to the second terminal of the second capacitor, a second terminal of the third capacitor is grounded, a first terminal of the second inductor is coupled to the second node, and a second terminal of the second inductor is grounded,
one end of the first capacitor is connected with the first end of the second capacitor, and the other end of the first capacitor is grounded.
Further, the LC circuit further comprises a second LC series circuit and a second LC parallel circuit;
a first end of the second LC series circuit is connected with the first node, and a second end of the second LC series circuit is connected with a first end of the first LC series circuit;
the first end of the second LC parallel circuit is connected with the second end of the second LC series circuit, and the second end of the second LC parallel circuit is grounded.
Further, the second LC series circuit comprises a third inductance and a fourth capacitance connected in series; the second LC parallel circuit comprises a fourth inductor and a fifth capacitor which are connected in parallel;
a first end of the third inductor is connected with the first node, a second end of the third inductor is connected with a first end of the fourth capacitor, a second end of the fourth capacitor is connected with a first end of the fifth capacitor, and a second end of the fifth capacitor is grounded; the first end of the fourth inductor is connected with the first end of the first LC series circuit, and the second end of the fourth inductor is grounded.
Furthermore, the matching circuit further comprises a sixth capacitor, one end of the sixth capacitor is connected with the first end of the fourth capacitor, and the other end of the sixth capacitor is grounded.
Further, the matching circuit further comprises a fifth inductor, and the fifth inductor is connected in parallel with the second capacitor.
Further, the matching circuit further comprises a sixth inductor, and the sixth inductor is connected with the first capacitor in series.
Further, the matching circuit further comprises a seventh inductor, and the seventh inductor is connected with the third capacitor in series.
The radio frequency circuit comprises a matching circuit and a power amplifying circuit, wherein the matching circuit is connected with the power amplifying circuit, the matching circuit comprises at least one LC circuit, the matching circuit is configured to suppress harmonic signals in the radio frequency signals, the embodiment arranges the at least one LC circuit in the matching circuit, so as to suppress the harmonic signals in the radio frequency signals, and therefore, the matching circuit cannot adjust the impedance of an input node or an output node of the power amplifying circuit, so as to realize impedance matching of the power amplifying circuit, and can also suppress the harmonic signals in the radio frequency input signals or the radio frequency output signals, without additionally arranging a filter circuit, so as to solve the problem that the radio frequency circuit cannot consider both area and performance.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
FIG. 1 is a circuit diagram of an RF circuit according to an embodiment of the present invention;
FIG. 2 is another circuit diagram of a matching circuit according to an embodiment of the utility model;
FIG. 3 is another circuit diagram of the matching circuit according to an embodiment of the utility model;
FIG. 4 is another circuit diagram of the matching circuit according to an embodiment of the utility model;
FIG. 5 is another circuit diagram of the matching circuit according to an embodiment of the utility model;
FIG. 6 is another circuit diagram of the matching circuit according to an embodiment of the utility model;
FIG. 7 is another circuit diagram of the matching circuit according to an embodiment of the utility model;
FIG. 8 is another circuit diagram of a matching circuit according to an embodiment of the utility model;
FIG. 9 is another circuit diagram of the matching circuit according to an embodiment of the utility model;
fig. 10 is another circuit diagram of the matching circuit according to an embodiment of the utility model.
In the figure: 11. a first LC series circuit; 12. a first LC parallel circuit; 21. a second LC series circuit; 22. a second LC parallel circuit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the utility model to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity to indicate like elements throughout.
It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under …," "under …," "below," "under …," "over …," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the utility model, however, the utility model is capable of other embodiments in addition to those detailed.
The present embodiment provides a radio frequency circuit, as shown in fig. 1, including a matching circuit 10 and a power amplifying circuit 20, where the matching circuit 10 is connected to the power amplifying circuit 20, and the matching circuit 10 includes at least one LC circuit, and the matching circuit is configured to suppress a harmonic signal in a radio frequency signal.
Further, the matching circuit 10 in the present embodiment is mainly used for suppressing harmonic signals outside the intermediate frequency band of the radio frequency signal, and therefore, the matching circuit 10 in the present embodiment is a matching circuit 10 having a bandpass filter structure.
In the present embodiment, at least one LC circuit is disposed in the matching circuit 10, so as to suppress a harmonic signal in the radio frequency signal, and thus, the matching circuit 10 can not only adjust the impedance of the input node or the output node of the power amplification circuit to achieve impedance matching of the power amplification circuit, but also suppress the harmonic signal in the radio frequency signal without additionally disposing a filter circuit, so as to solve the problem that the radio frequency circuit cannot consider both the area and the performance.
In a specific embodiment, the matching circuit 10 includes a first node configured to receive a radio frequency input signal and a second node connected to the input node of the power amplifying circuit 10, and the matching circuit is configured to suppress harmonic signals in the radio frequency input signal. Therefore, the matching circuit 10 can not only adjust the impedance of the input node of the power amplifying circuit to realize the impedance matching of the power amplifying circuit, but also suppress the harmonic signal in the radio frequency input signal without additionally providing a filter circuit, so as to solve the problem that the radio frequency circuit cannot consider both the area and the performance.
In another specific embodiment, the first node is configured to be connected to an output node of the power amplification circuit, and the second node is configured to output a radio frequency amplified signal; the matching circuit is configured to suppress harmonic signals in the radio frequency amplified signal. Therefore, the matching circuit 10 can not only adjust the impedance of the output node of the power amplifying circuit to realize the impedance matching of the power amplifying circuit, but also suppress the harmonic signal in the radio frequency output signal without additionally providing a filter circuit, so as to solve the problem that the radio frequency circuit cannot consider both the area and the performance.
In a specific embodiment, as shown in fig. 2, the LC circuit includes a first LC series circuit 11, a second LC series circuit 21, and a first LC parallel circuit 12, a first end of the first LC series circuit 11 is coupled to the first node, and a second end of the first LC series circuit 11 is coupled to the second node;
the first LC series circuit 11 comprises a first inductor L111 and a second capacitor C111, a first end of the first inductor L111 is coupled to the first node, a second end of the first inductor L111 is connected to a first end of the second capacitor C111, and a second end of the second capacitor C111 is coupled to the second node;
a first end of the second LC series circuit 21 is connected to a first end of the second capacitor C111, and a second end of the second LC series circuit 21 is grounded;
a first end of the first LC parallel circuit 12 is connected to a second end of the second capacitor C111, and a second end of the first LC parallel circuit 12 is grounded.
In the present embodiment, the first LC series circuit 11, the second LC series circuit 21 and the first LC parallel circuit 12 are disposed in the matching circuit 10, so as to suppress the harmonic signal in the radio frequency input signal, and thus, the matching circuit 10 can not only adjust the impedance of the input node of the power amplification circuit to achieve impedance matching of the power amplification circuit, but also suppress the harmonic signal in the radio frequency input signal without additionally disposing a filter circuit, so as to solve the problem that the radio frequency circuit cannot achieve both area and performance.
In a specific embodiment, as shown in fig. 3, the LC circuit includes a first LC series circuit 11 and a first LC parallel circuit 12, and the matching circuit 10 further includes a first capacitor C10. A first terminal of the first LC series circuit 11 is coupled to a first node, a second terminal of the first LC series circuit 11 is coupled to a second node, a first terminal of the first LC parallel circuit 12 is coupled to a second terminal of the first LC series circuit 11, and a second terminal of the first LC parallel circuit 12 is grounded. The first LC series circuit 11 includes a first inductance L111 and a second capacitance C111 connected in series. A first terminal of the first inductor L111 is coupled to the first node RF1, a second terminal of the first inductor L111 is connected to a first terminal of a second capacitor C111, and a second terminal of the second capacitor C111 is coupled to a second node RF 2. The first LC parallel circuit 12 includes a second inductance L121 and a third capacitance C121 connected in parallel. The first terminal of the third capacitor C121 is connected to the second terminal of the second capacitor C111, the second terminal of the third capacitor C121 is grounded, the first terminal of the second inductor L121 is coupled to the second node RF2, the second terminal of the second inductor L121 is grounded, one terminal of the first capacitor C10 is connected to the first terminal of the second capacitor C111, and the other terminal of the first capacitor C10 is grounded.
Optionally, the order of the matching circuit 10 is at least two, i.e. the matching circuit 10 comprises at least one first LC series circuit 11 connected between a first node and a second node, and at least one first LC parallel circuit 12 connected between the first LC series circuit 11 and ground. Preferably, the present embodiment will be described by taking the matching circuit 10 as a second-order matching circuit 10 as an example.
In one embodiment, the matching circuit may be an input matching circuit for matching an impedance of an input terminal of the rf power amplifier; or an input matching circuit, for matching the impedance of the output terminal of the radio frequency power amplifier.
In the present embodiment, the matching circuit 10 includes a first node RF1, a second node RF2, a first LC series circuit 11, and a first LC parallel circuit 12. A first end of the first LC series circuit 11 is coupled to a first node RF1 and a second end of the first LC parallel circuit 12 is coupled to a second node RF 2. A first terminal of the first LC parallel circuit 12 is connected to a second terminal of the first LC series circuit 11, and a second terminal of the first LC parallel circuit 12 is grounded.
In another specific embodiment, the matching circuit 10 further includes a second LC series circuit 21 and a second LC parallel circuit 22; a first terminal of the second LC series circuit 21 is connected to the first node RF1, and a second terminal of the second LC series circuit 21 is connected to a first terminal of the first LC series circuit 11; a first terminal of the second LC parallel circuit 22 is connected to a second terminal of the second LC series circuit 21, and a second terminal of the second LC parallel circuit 22 is grounded.
In a specific embodiment, the first LC series circuit 11 includes a first inductor L111 and a second capacitor C111 connected in series. A first terminal of the first inductor L111 is coupled to the first node RF1, a second terminal of the first inductor L111 is connected to a first terminal of the second capacitor C111, and a second terminal of the second capacitor C111 is coupled to the second node RF 2.
In another specific embodiment, the first LC parallel circuit 12 includes a second inductance L121 and a third capacitance C121 connected in parallel. A first terminal of the third capacitor C121 is connected to the second terminal of the second capacitor C111, a second terminal of the third capacitor C121 is grounded, a first terminal of the second inductor L121 is coupled to the second node RF2, and a second terminal of the second inductor L121 is grounded.
In this embodiment, for the purpose of flexibly adjusting the impedance value at two ends of the matching circuit 10, the matching circuit 10 in this embodiment further includes a first capacitor C10, one end of the first capacitor C10 is connected to the first end of the second capacitor C111, and the other end of the first capacitor C10 is connected to ground, so that the first capacitor C10, the second capacitor C111, and the third capacitor C121 can be equivalent to a circuit formed by one capacitor and one transformer according to the Norton's first transformation principle, that is, the radio frequency circuit of the band-pass filter structure is formed by only the first capacitor C10, the second capacitor C111, and the third capacitor C121, and the impedance at the first node RF1 and/or the second node RF2 of the radio frequency circuit can be adjusted, for example: the impedance of the first node RF1 and/or the second node RF2 of the radio frequency circuit is matched to 50 ohms from non-50 ohms, so that the aim of flexibly adjusting the impedance values of the two ends of the radio frequency circuit is fulfilled.
In the present embodiment, the matching circuit 10 includes a first node RF1, a second node RF2, a first LC series circuit 11, a first LC parallel circuit 12, and a first capacitance C10. A first terminal of the first LC series circuit 11 is coupled to a first node, a second terminal of the first LC series circuit 11 is coupled to a second node, a first terminal of the first LC parallel circuit 12 is coupled to a second terminal of the first LC series circuit 11, and a second terminal of the first LC parallel circuit 12 is grounded. The first LC series circuit 11 includes a first inductance L111 and a second capacitance C111 connected in series. A first terminal of the first inductor L111 is coupled to the first node RF1, a second terminal of the first inductor L111 is connected to a first terminal of the second capacitor C111, and a second terminal of the second capacitor C111 is coupled to the second node RF 2. The first LC parallel circuit 12 includes a second inductance L121 and a third capacitance C121 connected in parallel. The first terminal of the third capacitor C121 is connected to the second terminal of the second capacitor C111, the second terminal of the third capacitor C121 is grounded, the first terminal of the second inductor L121 is coupled to the second node RF2, the second terminal of the second inductor L121 is grounded, one terminal of the first capacitor C10 is connected to the first terminal of the second capacitor C111, and the other terminal of the first capacitor C10 is grounded. In the present embodiment, by connecting one end of the first capacitor C10 in the matching circuit 10 to the first end of the second capacitor C111 in the first LC series circuit 11, connecting the other end of the first capacitor C10 to ground, connecting the first end of the third capacitor C121 in the first LC parallel circuit 12 to the second end of the second capacitor C111 in the first LC series circuit 11, and connecting the second end of the third capacitor C121 to ground, the impedance of the first node RF1 and/or the second node RF2 of the matching circuit 10 can be adjusted by using the matching circuit 10 of the band-pass filter structure, for example: the impedance of the first node RF1 and/or the second node RF2 of the matching circuit 10 is matched from non-50 ohms to 50 ohms, so that the purpose of flexibly adjusting the impedance value of the two ends of the matching circuit 10 is achieved.
In this embodiment, by connecting one end of the first capacitor C10 to the first end of the second capacitor C111, connecting the other end of the first capacitor C10 to ground, connecting the first end of the third capacitor C121 to the second end of the second capacitor C111, and connecting the second end of the third capacitor C121 to ground, the impedance of the first node RF1 and/or the second node RF2 of the matching circuit 10 can be adjusted by using the matching circuit 10 in the band-pass filter structure, for example: the impedance of the first node RF1 and/or the second node RF2 of the matching circuit 10 is matched from non-50 ohms to 50 ohms, so that the purpose of flexibly adjusting the impedance value of the two ends of the matching circuit 10 is achieved.
In one embodiment, as shown in FIG. 2, the first node RF1 is an input node and the second node RF2 is an output node; alternatively, the first node RF1 is an output node, and the second node RF2 is an input node.
In an embodiment, the first node RF1 is an input node, the second node RF2 is an output node, that is, the first node RF1 of the matching circuit 10 is connected to the output terminal of the RF power amplifier, and the second node RF2 of the matching circuit 10 is connected to the RF signal output terminal, since the impedance of the second node RF2 of the matching circuit 10 is adjusted through the first capacitor C10, the second capacitor C111 and the third capacitor C121, the second node RF2 of the matching circuit 10 can implement impedance matching, that is, the impedance of the second node RF2 of the matching circuit 10 is adjusted to 50 ohms, thereby achieving the purpose of flexibly adjusting the impedance value at both ends of the matching circuit 10.
In another embodiment, the first node RF1 is an output node, the second node RF2 is an input node, that is, the first node RF1 of the matching circuit 10 is connected to a radio frequency signal input terminal, and the second node RF2 of the matching circuit 10 is connected to an input terminal of a radio frequency power amplifier, since the impedance of the second node RF2 of the matching circuit 10 is adjusted through the first capacitor C10, the second capacitor C111 and the third capacitor C121, the second node RF2 of the matching circuit 10 can implement impedance matching, that is, the impedance of the second node RF2 of the matching circuit 10 is adjusted to 50 ohms, thereby achieving the purpose of flexibly adjusting the impedance value of the two terminals of the matching circuit 10.
In the present embodiment, the first node RF1 is an input node, and the second node RF2 is an output node; alternatively, the first node RF1 is an output node, and the second node RF2 is an input node, when the matching circuit 10 is applied to the input terminal of the RF power amplifier, the impedance matching is performed on the input terminal of the RF power amplifier.
In one embodiment, as shown in fig. 4, the second LC series circuit 21 includes a third inductor L211 and a fourth capacitor C211 connected in series; the second LC parallel circuit 22 includes a fourth inductance L221 and a fifth capacitance C221 connected in parallel; a first terminal of the third inductor L211 is connected to the first node RF1, a second terminal of the third inductor L211 is connected to a first terminal of a fourth capacitor C211, a second terminal of the fourth capacitor C211 is connected to a first terminal of a fifth capacitor C221, and a second terminal of the fifth capacitor C221 is grounded; a first terminal of the fourth inductance L221 is connected to the first terminal of the first LC series circuit 11, and a second terminal of the fourth inductance L221 is grounded.
In the present embodiment, the second LC series circuit 21 includes a third inductance L211 and a fourth capacitance C211 connected in series; the second LC parallel circuit 22 includes a fourth inductance L221 and a fifth capacitance C221 connected in parallel. In this embodiment, the first terminal of the third inductor L211 is connected to the first node RF1, the second terminal of the third inductor L211 is connected to the first terminal of the fourth capacitor C211, the second terminal of the fourth capacitor C211 is connected to the first terminal of the fifth capacitor C221, and the second terminal of the fifth capacitor C221 is grounded; and the first terminal of the fourth inductance L221 is connected to the first terminal of the first LC series circuit 11, and the second terminal of the fourth inductance L221 is grounded.
In one embodiment, as shown in fig. 5, the matching circuit 10 further includes a sixth capacitor C20, one end of the sixth capacitor C20 is connected to the first end of the fourth capacitor C211, and the other end of the sixth capacitor C20 is grounded.
In an embodiment, the matching circuit 10 further includes a sixth capacitor C20, one end of the sixth capacitor C20 is connected to the first end of the fourth capacitor C211, and the other end of the sixth capacitor C20 is connected to ground, so that the fourth capacitor C211, the fifth capacitor C221, and the sixth capacitor C20 can be equivalent to a circuit formed by a capacitor and a transformer according to the Norton's first transformation principle, that is, the impedance at the first node RF1 of the matching circuit 10 can be adjusted only by the fourth capacitor C211, the fifth capacitor C221, and the sixth capacitor C20, for example, the impedance at the first node RF1 of the matching circuit 10 is adjusted to an impedance of 13.5 ohms at the first node RF1 of the matching circuit 10, so as to achieve the purpose of flexibly adjusting the impedance values at the two ends of the matching circuit 10.
In one embodiment, as shown in fig. 6, the matching circuit 10 further includes a fifth inductor L10, and the fifth inductor L10 is connected in parallel with the second capacitor C111.
In this embodiment, the matching circuit 10 further includes a fifth inductor L10, the fifth inductor L10 is connected in parallel with the second capacitor C111, and the fifth inductor L10 and the second capacitor C111 can form a first LC resonant circuit for suppressing noise and improving harmonics. Alternatively, the first resonance frequency point of the first LC resonance circuit may be configured by configuring the inductance value of the fifth inductor L10 and the capacitance value of the second capacitor C111 so that the first resonance frequency point of the first LC resonance circuit resonates at a frequency point where harmonics/noise exists, to achieve harmonic and noise suppression. In the embodiment, by adding a matching network pressure point, the impedance matching is realized, and meanwhile, the spatial noise can be filtered, and the out-of-band rejection capability is improved.
In one embodiment, as shown in fig. 7, the matching circuit 10 further includes a sixth inductor L20, and the sixth inductor L20 is connected in series with the first capacitor C10.
In this embodiment, the matching circuit 10 further includes a sixth inductor L20, the sixth inductor L20 is connected in series with the first capacitor C10, and the sixth inductor L20 and the first capacitor C10 can form a second LC resonant circuit for suppressing noise and improving harmonics. Optionally, the second resonant frequency point of the second LC resonant circuit may be configured by configuring the inductance value of the sixth inductor L20 and the capacitance value of the first capacitor C10, so that the second resonant frequency point of the second LC resonant circuit resonates at the frequency point where the harmonic/noise exists, so as to implement harmonic and noise suppression; this embodiment is through increasing two matching network pressure points to when realizing impedance matching, the filtering space noise that can also be better further improves out-of-band rejection ability.
In an embodiment, as shown in fig. 8, the matching circuit 10 further includes a seventh inductor L30, and the seventh inductor L30 is connected in series with the third capacitor C121.
In this embodiment, the matching circuit 10 further includes a seventh inductor L30, the seventh inductor L30 is connected in series with the third capacitor C121, and the seventh inductor L30 and the third capacitor C121 can form a third LC resonant circuit for suppressing noise and improving harmonics. Alternatively, the third resonance frequency point of the third LC resonance circuit may be configured by configuring the inductance value of the seventh inductor L30 and the capacitance value of the third capacitor C121, so that the third resonance frequency point of the third LC resonance circuit resonates at a frequency point where the harmonic/noise exists, to achieve harmonic and noise suppression; this embodiment is through increasing three matching network pressure points to when realizing impedance matching, the spatial noise of filtering that can also be better further improves out-of-band rejection ability.
In an embodiment, as shown in fig. 9, the matching circuit 10 further includes an eighth inductor L40, and the eighth inductor L40 is connected in parallel with the fourth capacitor C211.
In this embodiment, the matching circuit 10 further includes an eighth inductor L40, the eighth inductor L40 is connected in series with the fourth capacitor C211, and the eighth inductor L40 and the fourth capacitor C211 can form a fourth LC resonant circuit for suppressing noise and improving harmonics. Alternatively, the fourth resonance frequency point of the fourth LC resonance circuit may be configured by configuring the inductance value of the eighth inductor L40 and the capacitance value of the fourth capacitor C211, so that the fourth resonance frequency point of the fourth LC resonance circuit resonates at a frequency point where the harmonic/noise exists, so as to implement harmonic suppression and noise suppression; this embodiment is through increasing four matching network pressure points to when realizing impedance matching, the filtering space noise that can also be better further improves out-of-band rejection ability.
In one embodiment, as shown in fig. 10, the matching circuit 10 further includes a ninth inductor L50, and the ninth inductor L50 is connected in series with the fifth capacitor C221.
In this embodiment, the matching circuit 10 further includes a ninth inductor L50, the ninth inductor L50 is connected in series with the fifth capacitor C221, and the ninth inductor L50 and the fifth capacitor C221 can form a fifth LC resonant circuit for suppressing noise and improving harmonics. Alternatively, the fifth resonance frequency point of the fifth LC resonance circuit may be configured by configuring the inductance value of the ninth inductor L50 and the capacitance value of the fifth capacitor C221, so that the fifth resonance frequency point of the fifth LC resonance circuit resonates at a frequency point where the harmonic/noise exists, so as to achieve harmonic and noise suppression; in the embodiment, five matching network pressure points are added, so that the impedance matching is realized, meanwhile, the spatial noise can be better filtered, and the out-of-band rejection capability is further improved.
It should be noted that, according to the present application, the capacitance parallel inductance on the serial branch between the first node and the second node and/or the capacitance series inductance on the parallel branch between the serial branch and the ground terminal in the matching circuit 10 may be implemented according to actual situations, so as to form one or more harmonic/noise suppression points, so as to perform comprehensive and effective suppression on the harmonic/noise of the radio frequency power amplifier, and further improve the out-of-band suppression capability.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (10)
1. A radio frequency circuit comprising a matching circuit and a power amplification circuit, the matching circuit and the power amplification circuit being connected, the matching circuit comprising at least one LC circuit, the matching circuit being configured to suppress harmonic signals in a radio frequency signal.
2. The radio frequency circuit of claim 1, wherein the matching circuit comprises a first node configured to receive a radio frequency input signal and a second node connected to the input node of the power amplification circuit, the matching circuit configured to suppress harmonic signals in the radio frequency input signal; or, the first node is configured to be connected to an output node of the power amplification circuit, and the second node is configured to output a radio frequency amplified signal; the matching circuit is configured to suppress harmonic signals in the radio frequency amplified signal.
3. The radio frequency circuit of claim 2, wherein the LC circuit comprises a first LC series circuit, a second LC series circuit, and a first LC parallel circuit, a first end of the first LC series circuit coupled to the first node, a second end of the first LC series circuit coupled to the second node;
the first LC series circuit comprises a first inductor and a second capacitor, a first end of the first inductor is coupled to the first node, a second end of the first inductor is connected with a first end of the second capacitor, and a second end of the second capacitor is coupled to the second node;
a first end of the second LC series circuit is connected with a first end of the second capacitor, and a second end of the second LC series circuit is grounded;
and the first end of the first LC parallel circuit is connected with the second end of the second capacitor, and the second end of the first LC parallel circuit is grounded.
4. The radio frequency circuit of claim 2, wherein the LC circuit comprises a first LC series circuit and a first LC parallel circuit, the matching circuit further comprising a first capacitance,
a first end of the first LC series circuit is coupled to a first node of the matching circuit, a second end of the first LC series circuit is coupled to a second node of the matching circuit, a first end of the first LC parallel circuit is coupled to a second end of the first LC series circuit, and a second end of the first LC parallel circuit is grounded;
the first LC series circuit comprises a first inductor and a second capacitor connected in series;
a first end of the first inductor is coupled to the first node, a second end of the first inductor is connected with a first end of the second capacitor, and a second end of the second capacitor is coupled to the second node;
the first LC parallel circuit comprises a second inductor and a third capacitor which are connected in parallel;
a first terminal of the third capacitor is connected to the second terminal of the second capacitor, a second terminal of the third capacitor is grounded, a first terminal of the second inductor is coupled to the second node, and a second terminal of the second inductor is grounded,
one end of the first capacitor is connected with the first end of the second capacitor, and the other end of the first capacitor is grounded.
5. The radio frequency circuit of claim 4, wherein the LC circuit further comprises a second LC series circuit and a second LC parallel circuit;
a first end of the second LC series circuit is connected with the first node, and a second end of the second LC series circuit is connected with a first end of the first LC series circuit;
the first end of the second LC parallel circuit is connected with the second end of the second LC series circuit, and the second end of the second LC parallel circuit is grounded.
6. The radio frequency circuit of claim 5, wherein the second LC series circuit comprises a third inductance and a fourth capacitance connected in series; the second LC parallel circuit comprises a fourth inductor and a fifth capacitor which are connected in parallel;
a first end of the third inductor is connected with the first node, a second end of the third inductor is connected with a first end of the fourth capacitor, a second end of the fourth capacitor is connected with a first end of the fifth capacitor, and a second end of the fifth capacitor is grounded; the first end of the fourth inductor is connected with the first end of the first LC series circuit, and the second end of the fourth inductor is grounded.
7. The radio frequency circuit according to claim 6, wherein the matching circuit further comprises a sixth capacitor, one terminal of the sixth capacitor is connected to the first terminal of the fourth capacitor, and the other terminal of the sixth capacitor is grounded.
8. The radio frequency circuit of claim 4, wherein the matching circuit further comprises a fifth inductor, the fifth inductor being connected in parallel with the second capacitor.
9. The radio frequency circuit of claim 8, wherein the matching circuit further comprises a sixth inductor connected in series with the first capacitor.
10. The radio frequency circuit of claim 9, wherein the matching circuit further comprises a seventh inductor, the seventh inductor being connected in series with the third capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123255050.9U CN216531252U (en) | 2021-12-22 | 2021-12-22 | Radio frequency circuit and power amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123255050.9U CN216531252U (en) | 2021-12-22 | 2021-12-22 | Radio frequency circuit and power amplifier circuit |
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| Publication Number | Publication Date |
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| CN216531252U true CN216531252U (en) | 2022-05-13 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202123255050.9U Active CN216531252U (en) | 2021-12-22 | 2021-12-22 | Radio frequency circuit and power amplifier circuit |
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| Country | Link |
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| CN (1) | CN216531252U (en) |
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