CN216531249U - GaN power amplifier tube driving circuit - Google Patents
GaN power amplifier tube driving circuit Download PDFInfo
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- CN216531249U CN216531249U CN202122634995.5U CN202122634995U CN216531249U CN 216531249 U CN216531249 U CN 216531249U CN 202122634995 U CN202122634995 U CN 202122634995U CN 216531249 U CN216531249 U CN 216531249U
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Abstract
The utility model relates to the technical field of GaN power amplifier tube control, and provides a GaN power amplifier tube driving circuit which comprises a temperature compensation circuit, an over-voltage and under-voltage protection circuit, a time sequence protection circuit, a DC-DC power supply module, an over-current threshold setting resistor, a power supply current sampling resistor, a first capacitor, a second capacitor, a third capacitor, a first resistor, a second resistor, an MOS (metal oxide semiconductor) tube, a GaN power amplifier tube, an analog switch and an electrifying time sequence control chip in order to avoid damage of the power amplifier tube under abnormal conditions and reduce property loss. Overvoltage, undervoltage, overcurrent and power-on time sequence protection of the GaN power amplification tube are realized through the connection relation among the devices, the damage of the power amplification tube under abnormal conditions is effectively avoided, and property loss is reduced.
Description
Technical Field
The utility model relates to the technical field of control of GaN power amplification tubes, in particular to a GaN power amplification tube driving circuit.
Background
GaN power amplifier tubes have the characteristics of high breakdown voltage, high power density, high heat dissipation performance, high efficiency, high operating frequency and switching frequency, and are often used in the field of radio frequency for power amplification of radio frequency signals and for manufacturing high-power radio frequency power amplifiers. However, the existing GaN power amplifier tube has poor reliability and high price.
SUMMERY OF THE UTILITY MODEL
The utility model provides a GaN power amplifier tube driving circuit, which avoids the damage of a power amplifier tube under abnormal conditions and reduces the property loss.
The technical scheme adopted by the utility model for solving the problems is as follows:
the GaN power amplifier tube driving circuit comprises a temperature compensation circuit, an over-voltage and under-voltage protection circuit, a time sequence protection circuit, a DC-DC power supply module, an over-current threshold setting resistor, a power supply current sampling resistor, a first capacitor, a second capacitor, a third capacitor, a first resistor, a second resistor, an MOS tube, a GaN power amplifier tube, an analog switch and an electrifying time sequence control chip;
the DC-DC power supply module is connected with a grid electrode of the GaN power amplifying tube through an analog switch, one end of the temperature compensation circuit is connected with the DC-DC power supply module, the other end of the temperature compensation circuit is connected with the grid electrode of the GaN power amplifying tube through the analog switch, the over-under voltage protection circuit is connected with the power-on time sequence control chip, one end of the time sequence protection circuit is connected with the power-on time sequence control chip, the other end of the time sequence protection circuit is connected with the grid electrode of the GaN power amplifying tube, a radio frequency input signal is connected with the grid electrode of the GaN power amplifying tube through a first capacitor, a current setting pin of the power-on time sequence control chip is connected with an over-current threshold setting resistor and then is grounded, one end of a power supply current sampling resistor is connected with a voltage input end and a positive electrode of a current detection comparator of the power-on time sequence control chip, the other end of the power supply current sampling resistor is also connected with a drain electrode of the MOS tube, the source electrode of the MOS tube is connected with the drain electrode of the GaN power amplification tube, the drain electrode of the GaN power amplification tube is further connected with a second capacitor, radio frequency output is completed through the second capacitor, the source electrode of the GaN power amplification tube is grounded, one end of a third capacitor is grounded, the other end of the third capacitor is connected with a pull-up pin of a high-current gate driver of the power-on time sequence control chip through a first resistor, the other end of the third capacitor is connected with a pull-down pin of the high-current gate driver of the power-on time sequence control chip through a second resistor, and the other end of the third capacitor is further connected with a grid electrode of the MOS tube.
Furthermore, the temperature compensation circuit comprises a sliding rheostat, a first diode, a third resistor and a fourth capacitor, one end of the sliding rheostat is grounded, the other end of the sliding rheostat is connected with the anode of the first diode, the cathode of the first diode is connected with the analog switch, one end of the third resistor is grounded through the fourth capacitor after being connected with the cathode of the first diode, and the other end of the third resistor is connected with the DC-DC power supply module.
Furthermore, the overvoltage and undervoltage protection circuit comprises a first sampling resistor, a second sampling resistor and a third sampling resistor, one end of the first sampling resistor is connected with the voltage input end, the other end of the first sampling resistor is connected with one end of the power-on time sequence control chip and one end of the second sampling resistor respectively, the other end of the second sampling resistor is connected with one end of the power-on time sequence control chip and one end of the third sampling resistor respectively, and the other end of the third sampling resistor is grounded.
Furthermore, the timing protection circuit comprises a second diode, a fourth resistor, a fifth resistor and a triode, one end of the fourth resistor is connected with the voltage input end, the other end of the fourth resistor is grounded after being connected with the fifth resistor in series, a collector of the triode is connected between the first sampling resistor and the second sampling resistor, an emitter of the triode is grounded, a base of the triode and a negative electrode of the second diode are both connected between the fourth resistor and the fifth resistor, and a positive electrode of the second diode is connected with a grid electrode of the GaN power amplifier tube.
Further, the model of the power-on time sequence control chip is SE 7003.
Compared with the prior art, the utility model has the beneficial effects that: overvoltage and undervoltage damage of the GaN power amplifier tube is avoided through overvoltage and undervoltage protection; overcurrent protection is adopted to avoid overcurrent damage of the GaN power amplifier tube; the abnormal damage of the power-on time sequence of the GaN power amplifying tube is avoided through the power-on time sequence control of the grid voltage and the drain voltage; the damage of the power amplifier tube under the abnormal condition is effectively avoided through the protection, so that the property loss is reduced. The gain consistency of the GaN power amplifier tube is ensured through gate voltage temperature compensation; when the radio frequency does not work, the leakage voltage and the grid voltage can be cut off, the electric energy loss is reduced, and the service efficiency of the power supply is improved.
Drawings
Fig. 1 is a schematic structural diagram of a GaN power amplifier tube driving circuit.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the utility model and are not intended to limit the utility model.
As shown in fig. 1, the GaN power amplifier tube driving circuit includes a temperature compensation circuit, an over-voltage and under-voltage protection circuit, a timing protection circuit, a DC-DC power module, an over-current threshold setting resistor R7, a power current sampling resistor R1, a first capacitor C6, a second capacitor C5, a third capacitor C3, a first resistor R2, a second resistor R6, a MOS tube U2, a GaN power amplifier tube U3, an analog switch U5, and an power-on timing control chip U1, where the power-on timing control chip U1 is of a type SE 7003;
the DC-DC power supply module is connected with a grid electrode of a GaN power amplifying tube U3 through an analog switch U5, one end of the temperature compensation circuit is connected with the DC-DC power supply module, the other end of the temperature compensation circuit is connected with a grid electrode of the GaN power amplifying tube U3 through an analog switch U5, the over-voltage and under-voltage protection circuit is connected with an electrifying time sequence control chip U1, one end of the time sequence protection circuit is connected with an electrifying time sequence control chip U1, the other end of the time sequence protection circuit is connected with the grid electrode of the GaN power amplifying tube U3, a radio frequency input signal is connected with the grid electrode of the GaN power amplifying tube U3 through a first capacitor C INS 6, an Iset pin of the electrifying time sequence control chip U1 is grounded after being connected with an overcurrent threshold setting resistor R7, one end of a power supply current sampling resistor R1 is connected with an anode SNS pin and a voltage input end of a current detection comparator of the electrifying time sequence control chip U1, and the other end of the power supply current sampling resistor is connected with a cathode SNS-pin of a current detection comparator of the electrifying time sequence control chip U1, the other end of the power current sampling resistor R1 is also connected with the drain of a MOS tube U2, the source of the MOS tube U2 is connected with the drain of a GaN power amplification tube U3, the drain of the GaN power amplification tube U3 is also connected with a second capacitor C5, radio frequency output is completed through the second capacitor C5, the source of the GaN power amplification tube U3 is grounded, one end of the third capacitor C3 is grounded, the other end of the third capacitor C3 is connected with a high-current gate driver pull-up pin TGUP pin of the power-on time sequence control chip U1 through a first resistor R2, the other end of the third capacitor C3 is connected with a high-current gate driver pull-down pin TGDN pin of the power-on time sequence control chip U1 through a second resistor R6, and the other end of the third capacitor C3 is also connected with the gate of the MOS tube U2.
The input signal INP controls the on-off of the MOS tube U2 through the power-on time sequence control chip U1 to provide drain voltage for the GaN power amplification tube U3, the input signal EN gates temperature compensation voltage through the analog switch U5 to provide gate voltage Vgs for the GaN power amplification tube U3, and under the condition that the gate voltage and the drain voltage are normal, the radio-frequency input signal amplifies and outputs a high-power radio-frequency signal through the GaN power amplification tube U3.
In this embodiment, the DC-DC power module U6 converts the Vin input voltage of +28V to a voltage of-5V, and finally generates the gate voltage of the GaN power amplifier U3. When Vin loses power, the power module can normally work in a very low voltage range, and the output of the power module has large capacitance energy storage, so that the circuit ensures that the power failure time sequence of the GaN power amplifier tube U3 is to drop the leakage voltage firstly and then the grid voltage. The time sequence protection circuit ensures that the power-on time sequence of the GaN power amplification tube U3 is firstly gate voltage and then leakage voltage.
The overcurrent threshold setting resistor R7 and the internal circuit of the power-on time sequence control chip U1 form an overcurrent threshold voltage. When the voltage difference between the two ends of the power supply current sampling resistor R1 is greater than the overcurrent threshold voltage, the power-on time sequence control chip U1 turns off the MOS tube U2, so that the GaN power tube U3 is protected from being damaged, and overcurrent protection is realized.
Specifically, the temperature compensation circuit comprises a sliding rheostat RW1, a first diode D2, a third resistor R13 and a fourth capacitor C7, one end of the sliding rheostat RW1 is grounded, the other end of the sliding rheostat RW1 is connected with the anode of a first diode D2, the cathode of the first diode D2 is connected with a pin A1 of an analog switch U5, one end of the third resistor R13 is connected with the cathode of the first diode D2, the other end of the third resistor R13 is connected with a DC-DC power supply module U6, and the pin A1 of the analog switch U5 is further grounded through the fourth capacitor C7. The analog switch U5 is an alternative switch, the devices RW1, D2 and R13 form the normal static operating voltage of the GaN power amplifier tube U3, the slide rheostat RW1 is used for adjusting the voltage, and the first diode D2 utilizes the special temperature effect of the internal PN junction to realize the gate voltage temperature compensation function. When the GaN power amplifier is used, when an input signal EN is low, the U5 outputs a grid voltage of-5V, so that the GaN power amplifier tube U3 is in a cut-off state; when EN is high, U5 outputs temperature compensation gate voltage to make GaN power amplifier tube U3 in normal amplification state.
The overvoltage and undervoltage protection circuit comprises a first sampling resistor R8, a second sampling resistor R9 and a third sampling resistor R10, one end of the first sampling resistor R8 is connected with a voltage input end, the other end of the first sampling resistor R8 is respectively connected with a Vccuv pin of the power-on time sequence control chip U1 and one end of the second sampling resistor R9, the other end of the second sampling resistor R9 is respectively connected with an OVLO pin of the power-on time sequence control chip U1 and one end of the third sampling resistor R10, and the other end of the third sampling resistor R10 is grounded. The voltage of the power-on time sequence control chip U1Vccuv pin end is LV, the voltage is Vin x (R9+ R10)/(R8+ R9+ R10), the voltage is an under-voltage threshold, and compared with the internal threshold of U1, when the LV is lower than the internal threshold of U1, an alarm is generated, the U2 output is closed, and under-voltage protection is achieved. The voltage of the power-on time sequence control chip U1OVLO end is OV, and the OV is Vin multiplied by R10/(R8+ R9+ R10), and the voltage is an overvoltage threshold, and is compared with the internal threshold of U1, when the OV is higher than the internal threshold of U1, an alarm is generated, the output of U2 is closed, and overvoltage protection is realized.
The timing protection circuit comprises a second diode D1, a fourth resistor R11, a fifth resistor R12 and a triode U4, one end of the fourth resistor R11 is connected with a voltage input end, the other end of the fourth resistor R11 is connected with a fifth resistor R12 in series and then is grounded, a collector of the triode U4 is connected between a first sampling resistor R8 and a second sampling resistor R9, an emitter of the triode U4 is grounded, a base of the triode U4 and a cathode of a second diode D1 are both connected between a fourth resistor R11 and the fifth resistor R12, and an anode of the second diode D1 is connected with a gate of the GaN power amplifier U3. When Vgs is not electrified, the voltage is 0V, at the moment, the triode U4 is conducted, the LV is pulled to the ground, the power-on time sequence control chip U1 generates an under-voltage alarm, the output of the MOS tube U2 is closed, and namely the drain voltage of the GaN power amplification tube U3 is 0V; when Vgs is normally powered on, the voltage is-2V to-5V, the triode U4 is not conducted at the moment, the power-on time sequence control chip U1 normally works, and the power is output through the MOS tube U2, namely the drain voltage of the GaN power amplification tube U3 is the input voltage Vin. The circuit ensures that the power-on sequence of the GaN power amplifying tube U3 is firstly gate voltage and then leakage voltage.
The utility model avoids the overvoltage and undervoltage damage of the GaN power amplifier tube through overvoltage and undervoltage protection; overcurrent protection is adopted to avoid overcurrent damage of the GaN power amplifier tube; the abnormal damage of the power-on time sequence of the GaN power amplifying tube is avoided through the power-on time sequence control of the grid voltage and the drain voltage; the gain consistency of the GaN power amplifier tube is ensured through gate voltage temperature compensation; when the radio frequency does not work, the leakage voltage and the grid voltage can be cut off, the electric energy loss is reduced, and the service efficiency of the power supply is improved.
Claims (5)
- The GaN power amplifier tube driving circuit is characterized by comprising a temperature compensation circuit, an over-voltage and under-voltage protection circuit, a time sequence protection circuit, a DC-DC power supply module, an over-current threshold setting resistor, a power supply current sampling resistor, a first capacitor, a second capacitor, a third capacitor, a first resistor, a second resistor, an MOS tube, a GaN power amplifier tube, an analog switch and an electrifying time sequence control chip;the DC-DC power supply module is connected with a grid electrode of the GaN power amplifying tube through an analog switch, one end of the temperature compensation circuit is connected with the DC-DC power supply module, the other end of the temperature compensation circuit is connected with the grid electrode of the GaN power amplifying tube through the analog switch, the over-under voltage protection circuit is connected with the power-on time sequence control chip, one end of the time sequence protection circuit is connected with the power-on time sequence control chip, the other end of the time sequence protection circuit is connected with the grid electrode of the GaN power amplifying tube, a radio frequency input signal is connected with the grid electrode of the GaN power amplifying tube through a first capacitor, a current setting pin of the power-on time sequence control chip is connected with an over-current threshold setting resistor and then is grounded, one end of a power supply current sampling resistor is connected with a voltage input end and a positive electrode of a current detection comparator of the power-on time sequence control chip, the other end of the power supply current sampling resistor is also connected with a drain electrode of the MOS tube, the source electrode of the MOS tube is connected with the drain electrode of the GaN power amplification tube, the drain electrode of the GaN power amplification tube is further connected with a second capacitor, radio frequency output is completed through the second capacitor, the source electrode of the GaN power amplification tube is grounded, one end of a third capacitor is grounded, the other end of the third capacitor is connected with a pull-up pin of a high-current gate driver of the power-on time sequence control chip through a first resistor, the other end of the third capacitor is connected with a pull-down pin of the high-current gate driver of the power-on time sequence control chip through a second resistor, and the other end of the third capacitor is further connected with a grid electrode of the MOS tube.
- 2. The GaN power tube driving circuit of claim 1, wherein the temperature compensation circuit comprises a sliding varistor, a first diode, a third resistor and a fourth capacitor, the sliding varistor has one end grounded and the other end connected to the anode of the first diode, the cathode of the first diode is connected to the analog switch, the third resistor has one end connected to the cathode of the first diode and then grounded via the fourth capacitor, and the other end connected to the DC-DC power module.
- 3. The GaN power amplifier tube driving circuit of claim 1, wherein the over-voltage and under-voltage protection circuit comprises a first sampling resistor, a second sampling resistor and a third sampling resistor, one end of the first sampling resistor is connected to the voltage input terminal, the other end of the first sampling resistor is connected to one end of the power-on timing control chip and one end of the second sampling resistor, the other end of the second sampling resistor is connected to one end of the power-on timing control chip and one end of the third sampling resistor, and the other end of the third sampling resistor is grounded.
- 4. The GaN power amplifier tube driving circuit of claim 3, wherein the timing protection circuit comprises a second diode, a fourth resistor, a fifth resistor and a triode, one end of the fourth resistor is connected to the voltage input terminal, the other end of the fourth resistor is connected to the fifth resistor in series and then grounded, a collector of the triode is connected between the first sampling resistor and the second sampling resistor, an emitter of the triode is grounded, a base of the triode and a cathode of the second diode are both connected between the fourth resistor and the fifth resistor, and an anode of the second diode is connected to a gate of the GaN power amplifier tube.
- 5. The GaN power amplifier tube driving circuit as claimed in any of claims 1 to 4, wherein the power-on timing control chip is of type SE 7003.
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CN202122634995.5U CN216531249U (en) | 2021-10-29 | 2021-10-29 | GaN power amplifier tube driving circuit |
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CN202122634995.5U CN216531249U (en) | 2021-10-29 | 2021-10-29 | GaN power amplifier tube driving circuit |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN115241859A (en) * | 2022-06-30 | 2022-10-25 | 陕西省电子技术研究所有限公司 | Surge-resistant reverse-connection-preventing overvoltage, undervoltage and overcurrent protection device |
CN116505888A (en) * | 2023-06-28 | 2023-07-28 | 江苏展芯半导体技术有限公司 | Negative pressure protection circuit of GaN power amplifier |
-
2021
- 2021-10-29 CN CN202122634995.5U patent/CN216531249U/en active Active
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN115241859A (en) * | 2022-06-30 | 2022-10-25 | 陕西省电子技术研究所有限公司 | Surge-resistant reverse-connection-preventing overvoltage, undervoltage and overcurrent protection device |
CN116505888A (en) * | 2023-06-28 | 2023-07-28 | 江苏展芯半导体技术有限公司 | Negative pressure protection circuit of GaN power amplifier |
CN116505888B (en) * | 2023-06-28 | 2023-09-01 | 江苏展芯半导体技术有限公司 | Negative pressure protection circuit of GaN power amplifier |
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