SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a multi-type video interface conversion device which can realize the arbitrary conversion of five video formats, namely MIPI, LVDS, SDI, parallel port and PAL, by using only one set of device, and solves the problems of high cost and low use efficiency caused by the need of a plurality of video signal conversion devices in the conventional conversion of various video signals.
The technical scheme adopted by the utility model is as follows:
a multi-type video interface conversion device comprises a video format conversion module, a video input interface group, a key module, a video output interface group and a power module;
the video format conversion module is respectively connected with the video input interface group, the key module, the video output interface group and the power supply module;
the video input interface group comprises an MIPI video input interface, an LVDS video input interface, an SDI video input interface, a parallel port video input interface and a PAL video input interface, and is used for receiving an externally input MIPI video signal, an LVDS video signal, an SDI video signal, a parallel port video signal or a PAL video signal;
the video format conversion module receives a command transmitted by the key module and converts an input video signal into an MIPI video signal, an LVDS video signal, an SDI video signal, a parallel port video signal or a PAL video signal;
the video output interface group comprises an MIPI video output interface, an LVDS video output interface, an SDI video output interface, a parallel interface video output interface and a PAL video output interface, and is used for receiving the video signal output by the video format conversion module and sending the video signal to an external display device for display;
the key module is used for sending a video input format and a converted target format command to the video format conversion module;
and the power supply module is used for providing various types of required power supplies for the video format conversion module.
According to the scheme, the key module comprises a key, a first gear switch and a second gear switch; the key is used for turning on and turning off the computer, the first gear switch is used for selecting an input video format, and the second gear switch is used for selecting an output video format.
According to the scheme, the video format conversion module comprises a 5CEFA7 chip, an EDB1332 chip, an MT25QL512 chip, an ADV7391 chip, a TC358775 chip, an LT9211 chip, an ADV7180 chip and an AD8602 chip; the 5CEFA7 chip is respectively connected with an EDB1332 chip, an MT25QL512 chip, an ADV7391 chip, a TC358775 chip, an LT9211 chip, an ADV7180 chip, an AD8602 chip, an LVDS video input interface, an SDI video input interface, a parallel port video input interface, an LVDS video output interface, an SDI video output interface and a parallel port video output interface;
the ADV7391 chip is connected with the PAL video input interface;
the TC358775 chip is connected with the MIPI video input interface;
the LT9211 chip is connected with the MIPI video output interface;
the ADV7391 chip is connected with the PAL video output interface;
the 5CEFA7 chip is used for receiving the video signal transmitted by the video input interface group, performing data format conversion and generating a corresponding video signal to output to the video output interface group;
the EDB1332 chip is used for caching temporary data generated in the data number conversion process;
the MT25QL512 chip is used for storing the running program and the parameters of the 5CEFA7 chip;
the ADV7391 chip is used for converting the digital video signal into a PAL analog video signal and outputting the PAL analog video signal to a PAL video output interface;
the TC358775 chip is used for converting the MIPI signal level into a level format which can be recognized by the 5CEFA7 chip;
the LT9211 chip is used for converting LVDS signals output by the 5CEFA7 chip into signals in MIPI format;
the ADV7180 chip is used for converting the PLA video signal into a digital signal which can be identified by the 5CEFA7 chip;
the AD8602 chip is used for AD conversion of the divided battery voltage, then the divided battery voltage is sent to the 5CEFA7 for electric quantity monitoring, and the 5CEFA7 controls the power module to automatically close power output when the electric quantity is low.
According to the scheme, the power supply module comprises 6 sections 18650 of batteries and an LT8602 chip; the 6-section 18650 battery adopts a 3-string and 2-parallel mode and provides electric energy to the LT8602 chip; the LT8602 chip provides 1.2V, 1.8V and 3.3V power supply voltage for the video format conversion module; the battery is adopted for power supply, so that the whole device has the portability.
According to the scheme, the MIPI video input interface, the LVDS video input interface and the parallel port video input interface adopt PCI-E slots; the SDI video input interface and the PAL video input interface adopt BNC plugs.
According to the scheme, the MIPI video output interface, the LVDS video output interface and the parallel port video output interface adopt PCI-E slots; and the SDI video output interface and the PAL video output interface adopt BNC plugs.
The utility model has the beneficial effects that:
the video interconversion of five systems of MIPI, LVDS, SDI, parallel port and PAL is realized on a single device, the number of video conversion devices is reduced, the use cost of conversion of various video formats is effectively reduced, and the integration level and the use efficiency are improved;
the operation is convenient and fast, and the application range is wide.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the utility model and are not intended to limit the utility model.
Referring to fig. 1-3, a multi-type video interface conversion device includes a video format conversion module, a video input interface set, a key module, a video output interface set, and a power module. The video format conversion module is respectively connected with the video input interface group, the key module, the video output interface group and the power module. The video input interface group comprises an MIPI video input interface, an LVDS video input interface, an SDI video input interface, a parallel interface video input interface and a PAL video input interface, and is used for receiving an externally input MIPI video signal, an LVDS video signal, an SDI video signal, a parallel interface video signal or a PAL video signal. The video format conversion module receives a command transmitted by the key module and converts an input video signal into an MIPI video signal, an LVDS video signal, an SDI video signal, a parallel port video signal or a PAL video signal. The video output interface group comprises an MIPI video output interface, an LVDS video output interface, an SDI video output interface, a parallel interface video output interface and a PAL video output interface, and is used for receiving the video signal output by the video format conversion module and sending the video signal to the external display equipment for display. The key module is used for sending the video input format and the converted target format command to the video format conversion module. The power supply module is used for providing various types of required power supplies for the video format conversion module and comprises a key, a first gear switch and a second gear switch; the key is used for turning on and turning off the machine, the first gear switch is used for selecting an input video format, and the second gear switch is used for selecting an output video format.
In this embodiment, the video format conversion module includes a 5CEFA7 chip, an EDB1332 chip, an MT25QL512 chip, an ADV7391 chip, a TC358775 chip, an LT9211 chip, an ADV7180 chip, and an AD8602 chip. The 5CEFA7 chip is respectively connected with an EDB1332 chip, an MT25QL512 chip, an ADV7391 chip, a TC358775 chip, an LT9211 chip, an ADV7180 chip, an AD8602 chip, an LVDS video input interface, an SDI video input interface, a parallel port video input interface, an LVDS video output interface, an SDI video output interface and a parallel port video output interface; the ADV7391 chip is connected with the PAL video input interface; the TC358775 chip is connected with the MIPI video input interface; the LT9211 chip is connected with the MIPI video output interface; the ADV7391 chip is connected with the PAL video output interface. The 5CEFA7 chip is used for receiving the video signal transmitted by the video input interface group, performing data format conversion and generating a corresponding video signal to output to the video output interface group; the EDB1332 chip is used for caching temporary data generated in the data number conversion process; the MT25QL512 chip is used for storing the running program and the parameters of the 5CEFA7 chip; the ADV7391 chip is used for converting the digital video signal into a PAL analog video signal and outputting the PAL analog video signal to a PAL video output interface; the TC358775 chip is used for converting the MIPI signal level into a level format which can be recognized by the 5CEFA7 chip; the LT9211 chip is used for converting LVDS signals output by the 5CEFA7 chip into signals in MIPI format; the ADV7180 chip is used for converting the PLA video signal into a digital signal which can be identified by the 5CEFA7 chip; the AD8602 chip is used for AD conversion of the divided battery voltage, then the divided battery voltage is sent to the 5CEFA7 for electric quantity monitoring, and the 5CEFA7 controls the power module to automatically close power output when the electric quantity is low.
In this embodiment, the power module includes 6 batteries 18650 and LT8602 chips; the 6-section 18650 battery adopts a 3-string and 2-parallel mode and provides electric energy to the LT8602 chip; the LT8602 chip provides 1.2V, 1.8V and 3.3V power supply voltage for the video format conversion module; the battery is adopted for power supply, so that the whole device has the portability.
In the embodiment, the MIPI video input interface, the LVDS video input interface and the parallel port video input interface adopt PCI-E slots; the SDI video input interface and the PAL video input interface adopt BNC plugs. The MIPI video output interface, the LVDS video output interface and the parallel port video output interface adopt PCI-E slots; and the SDI video output interface and the PAL video output interface adopt BNC plugs.
The method for converting the multi-type video interface by adopting the multi-type video interface conversion device comprises the following steps:
s1, determining the input format and the output format of the video signal, and connecting the cable to the corresponding video signal input interface and the video signal output interface;
s2, toggling the first gear switch to make the option indicated by the first gear switch consistent with the video input signal format; shifting the second gear switch to make the option indicated by the second gear switch consistent with the format of the video output signal;
s3, pressing down a key, converting the battery voltage analog signal into a digital signal which can be identified by a 5CEFA7 chip by an AD8602 chip, transmitting the digital signal to a 5CEFA7 chip, controlling the turn-off time of the power supply module by the 5CEFA7 chip according to the digital signal of the battery voltage so as to prevent the over-discharge of the battery, reading the gear information of the first gear switch and the second gear switch by the video format conversion module, and performing corresponding format conversion.
The video format conversion module reads the gear information of the first gear switch and the second gear switch, and the corresponding format conversion steps are as follows:
when the input interface signal is an MIPI signal, the TC358775 chip converts the MIPI signal into an LVDS signal and transmits the LVDS signal to the 5CEFA7 chip for identification, and the signal can be identified by the 5CEFA7 chip;
1) if the MIPI signal needs to be converted into an LVDS signal, the 5CEFA7 chip directly outputs the LVDS signal to an LVDS video output interface of the video output interface set after being converted by the TC358775 chip;
2) if the MIPI signal needs to be converted into an SDI signal, the 5CEFA7 chip is matched with the EDB1332 chip to analyze the LVDS signal into a parallel digital signal, then the parallel digital signal is converted into an SDI serial digital signal, and the SDI serial digital signal is output to an SDI video output interface of the video output interface group;
3) if the MIPI signal needs to be converted into a parallel port signal, the 5CEFA7 chip is matched with the EDB1332 chip to analyze the LVDS signal into a parallel digital signal and output the parallel digital signal to a parallel port video output interface of the video output interface group;
4) if the MIPI signal needs to be converted into a PAL signal, the 5CEFA7 chip is matched with the EDB1332 chip, the LVDS signal is analyzed into a parallel digital signal, the parallel digital signal is transmitted to the ADV7391 chip, and the PAL signal is generated by the ADV7391 chip and then output to the PAL video output interface of the video output interface group;
when the input signal is an LVDS signal, the signal can be directly recognized by the 5CEFA7 chip:
1) if the LVDS signals need to be converted into MIPI signals, the 5CEFA7 chip transmits the signals to the LT9211 chip after receiving the LVDS signals, and the LT9211 chip converts the signals into MIPI signals and outputs the MIPI signals to the LVDS video output interface of the video output interface group;
2) if the LVDS signals need to be converted into SDI signals, the 5CEFA7 chip is matched with the EDB1332 chip to analyze the LVDS signals into parallel digital signals, then the parallel digital signals are converted into SDI serial digital signals, and the SDI serial digital signals are output to an SDI video output interface of the video output interface group;
3) if LVDS signals need to be converted into PAL signals, the 5CEFA7 chip is matched with the EDB1332 chip, the LVDS signals are analyzed into parallel digital signals, then the parallel digital signals are transmitted to the ADV7391 chip, and the PAL signals are generated by the ADV7391 chip and then output to the PAL video output interface of the video output interface group;
4) if the LVDS signals need to be converted into parallel port signals, the 5CEFA7 chip is matched with the EDB1332 chip to analyze the LVDS signals into parallel digital signals and output the parallel port signals to a parallel port video output interface of the video output interface group;
when the input signal is a parallel port signal, the signal can be directly identified by a 5CEFA7 chip;
1) if the parallel port signal needs to be converted into an LVDS, the 5CEFA7 chip is matched with the EDB1332 chip, and the parallel port signal is analyzed (coded) into the LVDS and then directly output to the LVDS video output interface of the video output interface group;
2) if the parallel port signal needs to be converted into the MIPI signal, the 5CEFA7 chip is matched with the EDB1332 chip, the parallel port signal is analyzed (coded) into an LVDS signal and is transmitted to the LT9211 chip, and the LT9211 chip converts the signal into the MIPI signal and then outputs the MIPI signal to an MIPI video output interface of the video output interface group;
3) if the parallel port signal needs to be converted into an SDI signal, the 5CEFA7 chip is matched with the EDB1332 chip, the parallel port signal is analyzed (coded) into an SDI signal, and then the SDI signal is output to an SDI video output interface of the video output interface group;
4) if the parallel port signal needs to be converted into a PAL signal, the 5CEFA7 chip is matched with the EDB1332 chip to transmit the parallel port signal to the ADV7391 chip, and the ADV7391 chip outputs the PAL signal to the PAL video output interface of the video output interface group;
when the input signal is an SDI signal, the signal can be directly identified by a 5CEFA7 chip;
1) if the SDI signal needs to be converted into the LVDS signal, the 5CEFA7 chip is matched with the EDB1332 chip, the SDI signal is analyzed (coded) into a parallel digital signal and then is analyzed into an LVDS differential signal, and the LVDS differential signal is output to an LVDS video output interface of the video output interface group;
2) if the SDI signal needs to be converted into the MIPI signal, the 5CEFA7 chip is matched with the EDB1332 chip, the SDI signal is analyzed into the LVDS signal and transmitted to the LT9211 chip, and the LT9211 chip converts the signal into the MIPI signal and then outputs the MIPI signal to an MIPI video output interface of the video output interface group;
3) if the SDI signal needs to be converted into a parallel port signal, the 5CEFA7 chip is matched with the EDB1332 chip to analyze the SDI signal into a parallel digital signal and output the parallel digital signal to a parallel port video output interface of the video output interface group;
4) if the SDI signal needs to be converted into the PAL signal, the 5CEFA7 chip is matched with the EDB1332 chip, and after the SDI signal is analyzed into a parallel digital signal, the 5CEFA7 chip transmits the parallel digital signal to the ADV7391 chip, and the ADV7391 chip generates an analog video signal and then transmits the signal to the PAL video output interface of the video output interface group;
when the input signal is a PAL signal, the signal needs to be converted into a parallel digital signal by an ADV7180 chip and then transmitted to a 5CEFA7 chip;
1) if the PAL signal needs to be converted into the parallel port signal, the 5CEFA7 chip directly transmits the parallel digital signal transmitted from the ADV7180 chip to the parallel port video output interface of the video output interface set.
2) If the PAL signal needs to be converted into an LVDS signal, the 5CEFA7 chip is matched with the EDB1332 chip to analyze the parallel digital signal transmitted by the ADV7180 chip into an LVDS signal, and the LVDS signal is directly output to an LVDS video output interface of the video output interface group;
3) if the PAL signal needs to be converted into the MIPI signal, the 5CEFA7 chip is matched with the EDB1332 chip, the parallel digital signal transmitted by the ADV7180 chip is analyzed into an LVDS signal and transmitted to the LT9211 chip, and the LT9211 chip converts the signal into the MIPI signal and then outputs the MIPI signal to an MIPI video output interface of the video output interface group;
4) if the PAL signal needs to be converted into the SDI signal, the 5CEFA7 chip is matched with the EDB1332 chip, and the parallel digital signal transmitted by the ADV7180 chip is analyzed into the SDI signal, and then the SDI signal is output to the SDI video output interface of the video output interface group.
The EDB1332 chip is mainly used for buffering the differential digital signals, de-paralleling the signals and re-encoding temporary data generated in the process of serial signals.
The utility model can carry out arbitrary conversion among five video formats of MIPI, LVDS, SDI, parallel port and PAL without using a plurality of video conversion devices, thereby effectively improving the video format conversion efficiency and the integration level of the devices.
It will be understood that modifications and variations can be made by persons skilled in the art in light of the above teachings and all such modifications and variations are intended to be included within the scope of the utility model as defined in the appended claims.