CN216351676U

CN216351676U - Array substrate and display device

Info

Publication number: CN216351676U
Application number: CN202121495654.8U
Authority: CN
Inventors: 李必奇; 先建波; 江亮亮; 周茂秀; 程敏
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2021-07-02
Filing date: 2021-07-02
Publication date: 2022-04-19
Anticipated expiration: 2031-07-02

Abstract

An array substrate and a display device. The array substrate comprises data lines and signal lines, each sub-pixel unit comprises a pixel electrode, the distance between the pixel electrode and the data lines is a first distance D1, the distance between the pixel electrode and the signal lines is a second distance D2, the side length of the pixel electrode close to the data lines is L1, and the side length of the pixel electrode close to the signal lines is L2; each sub-pixel unit also comprises a driving transistor, the source electrode of the driving transistor is connected with one of the data line and the signal line, and the drain electrode of the driving transistor is connected with the pixel electrode; the distance between the drain and the source of the driving transistor is a third distance D3, the distance between the drain and the other of the data line and the signal line is a fourth distance D4, the size of the source in the second direction is L3, the size of the drain in the second direction is L4, (E1L 1/D1+ E2L 3/D3) and the ratio of (E1L 2/D2+ E2L 4/D4) are in the range of 0.9-1.1, and therefore gray scale crosstalk can be effectively avoided.

Description

Array substrate and display device

Technical Field

The embodiment of the disclosure relates to an array substrate and a display device.

Background

With the continuous development of the technology, the display panel is widely applied to various electronic devices, such as a smart phone, a tablet computer, a notebook computer, a car navigation, and the like. General Display panels can be classified into Liquid Crystal Display (LCD) panels and Organic Light Emitting Diode (OLED) Display panels. The liquid crystal display panel has the advantages of high response speed, high resolution, high integration level, low power consumption, low cost and the like, thereby occupying a larger market share.

In general, a liquid crystal display panel generally includes an array substrate, a counter substrate, a liquid crystal layer, a first polarizer and a second polarizer; the array substrate and the opposite substrate are oppositely arranged, the liquid crystal layer is located between the array substrate and the opposite substrate, the first polaroid is located on one side, far away from the opposite substrate, of the array substrate, and the second polaroid is located on one side, far away from the array substrate, of the opposite substrate. The array substrate is provided with a Thin Film Transistor (TFT) and a pixel electrode, the liquid crystal display panel can provide driving voltage for the pixel electrode through the TFT to generate an electric field, the electric field can change the molecular arrangement of liquid crystal molecules in the liquid crystal layer, and the liquid crystal light valve can be formed by matching the first polaroid and the second polaroid which are arranged at two sides of the liquid crystal display panel, so that the display function is realized. In addition, the liquid crystal display panel can further realize color display by matching with the color film layer formed on the array substrate or the opposite substrate.

SUMMERY OF THE UTILITY MODEL

The embodiment of the disclosure provides an array substrate and a display device. The array substrate enables the parasitic capacitance generated by the pixel electrode in each sub-pixel unit to be approximately equal to that generated by other conductive structures on the left side and the right side, so that poor gray scale V-Crosstalk (Crosstalk) can be effectively avoided, and the display quality is improved.

At least one embodiment of the present disclosure provides an array substrate, which includes a substrate; the array substrate comprises a plurality of sub-pixel units, a plurality of first alignment layers and a plurality of second alignment layers, wherein the plurality of sub-pixel units are positioned on a substrate and are arranged in an array along a first direction and a second direction so as to form sub-pixel rows extending in the first direction and sub-pixel columns extending in the second direction; a gate line on the substrate, extending in the first direction, and configured to provide a gate signal to the subpixel row; the data line is positioned on the substrate base plate and extends along the second direction; and a signal line on the substrate base plate and extending along the second direction; the data line and the signal line are respectively located at two sides of the sub-pixel column in the first direction, each sub-pixel unit comprises a pixel electrode, the distance between the pixel electrode and the data line is a first distance D1, the distance between the pixel electrode and the signal line is a second distance D2, the side length of the pixel electrode close to the data line is S1, the side length of the pixel electrode close to the signal line is L2, each sub-pixel unit further comprises a driving transistor, the driving transistor comprises a source electrode and a drain electrode, the source electrode is connected with one of the data line and the signal line, the drain electrode is connected with the pixel electrode, the distance between the drain electrode and the source electrode in the first direction is a third distance D3, and the distance between the drain electrode and the other of the data line and the signal line is a fourth distance D4, the size of the source electrode in the second direction is L3, the size of the drain electrode in the second direction is L4, (E1 × L1/D1+ E2 × L3/D3) and (E1 × L2/D2+ E2 × L4/D4) are in a ratio range of 0.9-1.1, E1 is a dielectric constant of a film layer between the pixel electrode and the data line or the signal line, and E2 is a dielectric constant of a film layer between the signal line and the source electrode or the drain electrode.

For example, in an array substrate provided in an embodiment of the present disclosure, a ratio of (E1 × L1/D1+ E2 × L3/D3) to (E1 × L2/D2+ E2 × L4/D4) is in a range of 0.95 to 1.05.

For example, in an array substrate provided in an embodiment of the present disclosure, (E1 × L1/D1+ E2 × L3/D3) ═ E1 × L2/D2+ E2 × L4/D4.

For example, in an array substrate provided by an embodiment of the present disclosure, the data line and the signal line are both configured to transmit a data signal, the source of some of the sub-pixel units in the sub-pixel column is connected to the data line, and the source of another part of the sub-pixel units in the sub-pixel column is connected to the signal line.

For example, in an array substrate provided by an embodiment of the present disclosure, the data line located on one side of the jth sub-pixel column in the first direction is configured to provide a data signal to the jth sub-pixel column, and the signal line located on the other side of the jth sub-pixel column in the first direction is configured to provide a data signal to the j +1 th sub-pixel column, where j is a positive integer greater than or equal to 1.

For example, in an array substrate provided by an embodiment of the present disclosure, the signal line located on one side of the jth sub-pixel column in the first direction and the data line located on one side of the (j +1) th sub-pixel column in the first direction are configured to be connected to the same signal terminal.

For example, in an array substrate provided in an embodiment of the present disclosure, the signal line is configured to transmit a common electrode signal.

For example, in an array substrate provided by an embodiment of the present disclosure, a connection portion between the pixel electrode and the drain electrode is located on an area bisector of the pixel electrode in the first direction.

For example, in an array substrate provided by an embodiment of the present disclosure, a side length L1 of the pixel electrode close to the data line is equal to a side length L2 of the pixel electrode close to the signal line, and the first distance D1 is equal to the second distance D2.

For example, in an array substrate provided by an embodiment of the present disclosure, a dimension L3 of the source electrode in the second direction is equal to a dimension L4 of the drain electrode in the second direction, and the third distance D3 is equal to the fourth distance D4.

For example, in an array substrate provided in an embodiment of the present disclosure, each of the sub-pixel units includes a first region and a second region sequentially arranged along the second direction, the pixel electrode is located in the first region, and the driving transistor is located in the second region.

For example, in an array substrate provided in an embodiment of the present disclosure, the source electrode and the data line or the signal line connected to the source electrode are oppositely disposed at an interval, the array substrate further includes a conductive connection block, the source electrode is connected to the data line or the signal line connected to the source electrode through the conductive connection block, a distance between the source electrode and the data line or the signal line connected to the source electrode is a fifth distance D5, and the fifth distance D5 is equal to the fourth distance D4.

For example, in an array substrate provided in an embodiment of the present disclosure, a width of the sub-pixel unit in the first direction is Wpixel, the driving transistor includes an active layer, a length of a channel region of the active layer in the first direction is L, a length of a channel region of the active layer in the second direction is W, a width of the source electrode in the first direction is Wsource, a width of the drain electrode in the first direction is Wdrain, widths of the data line and the signal line in the first direction are Wdata, and a length of a channel region of the active layer in the first direction is L, which satisfies the following formula: wsource + Wdrain < L < (Wpixel-2 Wdata-Wsource-Wdrain)/3.

For example, in an array substrate provided in an embodiment of the present disclosure, a length L of a channel region of the active layer in the first direction satisfies the following formula:

Wsource+Wdrain＜L＜(Wpixel-2Wdata-Wsource-Wdrain)/4。

for example, in an array substrate provided in an embodiment of the present disclosure, the source electrode is a portion of the data line or the signal line connected to the source electrode.

For example, in an array substrate provided in an embodiment of the present disclosure, a width of the sub-pixel unit in the first direction is Wpixel, the driving transistor includes an active layer, a length of a channel region of the active layer in the first direction is L, a length of a channel region of the active layer in the second direction is W, a width of the source electrode in the first direction is Wsource, a width of the drain electrode in the first direction is Wdrain, widths of the data line and the signal line in the first direction are Wdata, and a length of a channel region of the active layer in the first direction is L, which satisfies the following formula: wsource + Wdrain < L < (Wpixel-2 Wdata-Wdrain)/2.

For example, in an array substrate provided by an embodiment of the present disclosure, an orthographic projection of the pixel electrode on the substrate is axisymmetric with respect to a bisector of an area of the pixel electrode in the first direction.

For example, in an array substrate provided by an embodiment of the present disclosure, the pixel electrode includes a first domain, a second domain, a third domain, and a fourth domain, where the first domain and the second domain are axisymmetric with respect to a bisector of an area of the pixel electrode in the first direction, the third domain and the fourth domain are axisymmetric with respect to a bisector of an area of the pixel electrode in the first direction, the first domain and the third domain are sequentially disposed along the second direction, and the second domain and the fourth domain are sequentially disposed along the second direction.

For example, in an array substrate provided by an embodiment of the present disclosure, the pixel electrode includes a middle portion extending along the second direction and located between the first domain and the second domain, between the third domain and the fourth domain, and the drain electrode is connected to the middle portion of the pixel electrode.

For example, in an array substrate provided in an embodiment of the present disclosure, the pixel electrode includes: a plurality of first slits arranged at intervals and positioned in the first domain; a plurality of second slits arranged at intervals and positioned in the second domain; a plurality of third slits arranged at intervals and positioned in the third domain; and a plurality of fourth slits arranged at intervals and positioned in the fourth domain.

For example, in an array substrate provided in an embodiment of the present disclosure, the plurality of sub-pixel units form n sub-pixel rows arranged in a second direction, the array substrate includes n gate lines, the gate lines are arranged in one-to-one correspondence with the n sub-pixel rows, a k-th gate line and a k + 1-th gate line form a (k + 1)/2-th gate line group, the array substrate further includes a first vertical gate line and a second vertical gate line, the first vertical gate line and the second vertical gate line are respectively located at two sides of the plurality of sub-pixel units in the first direction, in the (k + 1)/2-th gate line group, the k-th gate line and the k + 1-th gate line are connected through the first vertical gate line and the second vertical gate line, k may be an odd number greater than or equal to 1, and n is a positive integer greater than k.

For example, in an array substrate provided in an embodiment of the present disclosure, the first vertical gate line and the second vertical gate line are disposed on the same layer as the data line.

For example, in an array substrate provided in an embodiment of the present disclosure, the first vertical gate line is connected to the kth gate line through a first via connection structure, the first vertical gate line is connected to the (k +1) th gate line through a second via connection structure, the second vertical gate line is connected to the kth gate line through a third via connection structure, and the second vertical gate line is connected to the (k +1) th gate line through a fourth via connection structure.

For example, in an array substrate provided in an embodiment of the present disclosure, the array substrate further includes at least one middle vertical gate line located between two adjacent sub-pixel columns, and in the (k +1)/2 th gate line group, the kth gate line and the (k +1) th gate line are connected through the middle vertical gate line.

For example, in an array substrate provided in an embodiment of the present disclosure, the middle vertical gate line and the gate line are disposed on the same layer.

For example, an array substrate provided in an embodiment of the present disclosure further includes: a first common electrode line extending in the first direction; and a second common electrode line extending along the second direction, each sub-pixel unit comprises a first area and a second area which are sequentially arranged along the second direction, the pixel electrode is located in the first area, the driving transistor is located in the second area, the first common electrode line is located between two adjacent sub-pixel units in the second direction, and the second common electrode line is located between the first area and the second area of the same sub-pixel unit, and the second common electrode line is located between two adjacent sub-pixel columns.

For example, in an array substrate provided in an embodiment of the present disclosure, the first common electrode line and the gate line are disposed on the same layer, the first common electrode line includes at least one first notch and first sub-common electrode lines located at two sides of the first notch, and the middle vertical gate line passes through the first notch and is separately spaced from the first sub-common electrode line in an insulating manner.

For example, in an array substrate provided in an embodiment of the present disclosure, the second common electrode lines include a gate layer common electrode line and a data line layer common electrode line, the gate layer common electrode line and the gate line are disposed on the same layer, the data line layer common electrode line and the data line are disposed on the same layer, and the gate layer common electrode line is connected to the data line layer common electrode line through a fifth via connection structure.

For example, in an array substrate provided in an embodiment of the present disclosure, two first common electrode lines are disposed between the kth gate line and the kth +1 gate line in the (k +1)/2 th gate line group and respectively include the first notch, and the middle vertical gate line passes through the two first notches of the two first common electrode lines to connect the kth gate line and the kth +1 gate line.

For example, in an array substrate provided in an embodiment of the present disclosure, a width of a portion of the second common electrode line located in the first area is greater than a width of a portion of the second common electrode line located in the second area.

For example, in an array substrate provided in an embodiment of the present disclosure, the second common electrode line is located between the ith sub-pixel column and the (l +1) th sub-pixel column, a distance between the second common electrode line and the signal line corresponding to the ith sub-pixel column is equal to a distance between the second common electrode line and the data line corresponding to the (l +1) th sub-pixel column, or a distance between the second common electrode line and the data line corresponding to the ith sub-pixel column is equal to a distance between the second common electrode line and the signal line corresponding to the (l +1) th sub-pixel column, where l is a positive integer greater than or equal to 1.

For example, in an array substrate provided by an embodiment of the present disclosure, each of the sub-pixel units includes a first region and a second region sequentially arranged along the second direction, the pixel electrode is located in the first region, the driving transistor is located in a second region, a distance between a portion of the data line in the first region and a portion of the signal line in the first region in the first direction is smaller than a distance between a portion of the data line in the second region and a portion of the signal line in the second region in the first direction, the data line includes a first inclined connection part connecting a portion of the data line in the first region and a portion of the data line in the second region, the signal line includes a second inclined connection portion connecting a portion of the signal line in the first region and a portion of the signal line in the second region.

For example, an array substrate provided in an embodiment of the present disclosure further includes: a plurality of gate lead-out lines, each of the gate lead-out lines being located between two adjacent sub-pixel rows, each of the gate lead-out lines including: a first gate lead-out line disposed on the same layer as the data line and configured to connect a gate signal; and the second grid outgoing line is arranged on the same layer as the grid line and is configured to be connected with the corresponding grid line, and the first grid outgoing line and the second grid outgoing line are connected through a fifth via hole structure.

For example, in an array substrate provided in an embodiment of the present disclosure, the gate outgoing line is configured to be electrically connected to an (m +1)/2 th gate line group, the second gate outgoing line is directly connected to the mth gate line, m is an odd number greater than or equal to 1, the m-1 th gate line includes a second notch, three first common electrode lines are disposed between the mth gate line and the m-2 th gate line and each include a first notch, the second gate outgoing line passes through the second notch of the m-1 th gate line and three first notches of the three first common electrode lines and extends to a position where the sixth via connection structure is located, the sixth via connection structure is located between the m-2 th gate line and the first common electrode line, and the first grid outgoing line is connected with the second grid outgoing line through the sixth through hole connecting structure.

For example, an array substrate provided in an embodiment of the present disclosure further includes: and the shielding electrode is positioned on the substrate and arranged on the same layer with the grid line.

For example, in an array substrate provided by an embodiment of the present disclosure, an orthogonal projection of the shielding electrode on the substrate is located between an orthogonal projection of the second common electrode line on the substrate and an orthogonal projection of the data line on the substrate, and between an orthogonal projection of the second common electrode line on the substrate and an orthogonal projection of the signal line on the substrate.

For example, in an array substrate provided by an embodiment of the present disclosure, an orthogonal projection of the shielding electrode on the substrate is further located between an orthogonal projection of the data line on the substrate and an orthogonal projection of the signal line on the substrate.

At least one embodiment of the present disclosure also provides a display device including the array substrate of any one of the above.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1 is a schematic plan view of an array substrate;

fig. 2 is a schematic plan view of an array substrate according to an embodiment of the present disclosure;

fig. 3 is an enlarged schematic view of a driving transistor in an array substrate according to an embodiment of the present disclosure;

fig. 4 is a schematic plan view of another array substrate according to an embodiment of the present disclosure;

fig. 5 is an enlarged schematic view of a driving transistor in another array substrate according to an embodiment of the disclosure;

fig. 6A is a schematic plan view of another array substrate according to an embodiment of the present disclosure;

fig. 6B is a schematic plan view of another array substrate according to an embodiment of the disclosure;

fig. 7A is a schematic view of another array substrate according to an embodiment of the present disclosure;

fig. 7B is a schematic view of another array substrate according to an embodiment of the disclosure;

fig. 8A is a schematic cross-sectional view of an array substrate taken along line AB in fig. 7A according to an embodiment of the present disclosure;

fig. 8B is a schematic cross-sectional view of an array substrate along the CD line in fig. 7A according to an embodiment of the disclosure;

fig. 9 is a schematic plan view of another array substrate according to an embodiment of the present disclosure;

fig. 10 is a schematic plan view of another array substrate according to an embodiment of the present disclosure;

fig. 11 is a schematic diagram of a display device according to an embodiment of the disclosure; and

fig. 12 is a schematic cross-sectional view of a display device according to an embodiment of the disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.

Fig. 1 is a schematic plan view of an array substrate. As shown in fig. 1, the array substrate 10 includes a substrate 11, a plurality of gate lines 12 and a plurality of data lines 13; a plurality of gate lines 12 and a plurality of data lines 13 are arranged to cross each other to define a plurality of pixel units 20; each pixel unit 20 includes a pixel electrode 14, a common electrode 15, and a driving transistor 16; the gate line 12 is connected to a gate electrode of the driving transistor 16, the data line 13 is connected to a source electrode of the driving transistor 16, and the pixel electrode 14 is connected to a drain electrode of the driving transistor 16. In order to perform continuous light emission, a storage capacitor needs to be formed between the pixel electrode 14 and the common electrode 15 in the pixel unit 20. However, in an actual array substrate, the pixel electrode 14 may form a parasitic capacitance with other conductive structures in addition to the storage capacitance for normal display. For example, a parasitic capacitance Cpd1 is formed between the pixel electrode 14 and the data line 13, and a parasitic capacitance Cpd2 is formed between the pixel electrode 14 and the source of the driving transistor 16.

As shown in fig. 1, since the driving transistor 16 is usually disposed close to the data line 13, it is easy to cause the parasitic capacitance difference between the pixel electrode 14 and other conductive structures on the left and right sides. On the left side, the pixel electrode 14 forms a parasitic capacitance Cpd1 with the data line 13 on the left side, and forms a parasitic capacitance Cpd2 with the source of the driving transistor 16; on the right side, the pixel electrode 14 forms a parasitic capacitance Cpd3 with the right data line 13. At this time, the parasitic capacitance C1 between the pixel electrode 14 and the left conductive structure is Cpd1+ Cpd2, and the parasitic capacitance C2 between the pixel electrode 14 and the right conductive structure is Cpd 3. Generally, Cpd1 and Cpd3 are substantially equal, and the parasitic capacitance C1 generated by the pixel electrode 14 and the left conductive structure is larger than the parasitic capacitance C2 generated by the pixel electrode 14 and the right conductive structure.

The pixel electrode 14 and other conductive structures on the left and right sides generate different parasitic capacitances, which may result in poor gray scale V-Crosstalk; in addition, for a high-resolution product, such as an 8K product, since the size of the pixel unit is small and the storage capacitance of the pixel unit is small, the pixel unit is more easily pulled by the parasitic capacitance, and the poor V-cross caused by the difference between the parasitic capacitance generated by the pixel electrode and the parasitic capacitance generated by other conductive structures on the left and right sides is more obvious.

In view of the above, the embodiment of the present disclosure provides an array substrate and a display device. The array substrate comprises a substrate, a plurality of sub-pixel units, a grid line, a data line and a signal line; the plurality of sub-pixel units are positioned on the substrate and arranged in an array along a first direction and a second direction to form sub-pixel rows extending in the first direction and sub-pixel columns extending in the second direction; the grid line is positioned on the substrate, extends along a first direction and is configured to provide grid signals for the sub-pixel row; the data line is positioned on the substrate base plate and extends along a second direction; the signal line is positioned on the substrate base plate and extends in the second direction; the data lines and the signal lines are respectively positioned on two sides of the sub-pixel columns in the first direction, each sub-pixel unit comprises a pixel electrode, the distance between the pixel electrode and the data line is a first distance D1, the distance between the pixel electrode and the signal line is a second distance D2, the side length of the pixel electrode close to the data line is L1, and the side length of the pixel electrode close to the signal line is L2; each sub-pixel unit further comprises a driving transistor, the driving transistor comprises a source electrode and a drain electrode, the source electrode is connected with one of the data line and the signal line, and the drain electrode is connected with the pixel electrode; the distance between the drain and the source in the first direction is a third distance D3, the distance between the drain and the other of the data line and the signal line is a fourth distance D4, the size of the source in the second direction is L3, the size of the drain in the second direction is L4, (E1L 1/D1+ E2L 3/D3) and (E1L 2/D2+ E2L 4/D4) have a ratio ranging from 0.9 to 1.1, E1 is a dielectric constant of a film between the pixel electrode and the data line or the signal line, and E2 is a dielectric constant of a film between the drain and the source or the signal line. Therefore, the ratio of (E1 × L1/D1+ E2 × L3/D3) to (E1 × L2/D2+ E2 × L4/D4) is in the range of 0.9-1.1, so that parasitic capacitances generated by the pixel electrode in each sub-pixel unit and other conductive structures on the left side and the right side are approximately equal, and therefore, the defect of gray scale V-Crosstalk (Crosstalk) can be effectively avoided, and the display quality is improved.

Hereinafter, an array substrate and a display device provided in the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

An embodiment of the present disclosure provides an array substrate. Fig. 2 is a schematic plan view of an array substrate according to an embodiment of the present disclosure. As shown in fig. 2, the array substrate 100 includes a substrate 110, a plurality of sub-pixel units 120, a gate line 130, a data line 141, and a signal line 142; a plurality of sub-pixel units 120 are positioned on the substrate base plate 110, the plurality of sub-pixel units 120 are arranged in an array along a first direction X and a second direction Y to form sub-pixel rows 210 extending in the first direction X and sub-pixel columns 220 extending in the second direction Y; the gate line 130 is positioned on the substrate 110, extends in a first direction, and is configured to provide a gate signal to the sub-pixel row 210; the data line 141 is located on the substrate base plate 110 and extends along a second direction; the signal line 142 is located on the substrate base plate 110 and extends in the second direction; the data lines 141 and the signal lines 142 are respectively located at two sides of the sub-pixel column 220 in the first direction, and each sub-pixel unit 120 includes a pixel electrode 122.

As shown in fig. 2, the distance between the pixel electrode 122 and the data line 141 is a first distance D1, the distance between the pixel electrode 122 and the signal line 142 is a second distance D2, the side length of the pixel electrode 122 close to the data line 141 is L1, and the side length of the pixel electrode 122 close to the signal line 142 is L2; each sub-pixel unit 120 further includes a driving transistor T1, the driving transistor T1 includes a Source1 and a Drain1, the Source1 is connected to one of the data line 141 and the signal line 142, and the Drain1 is connected to the pixel electrode 122; the distance between the Drain1 and the Source1 in the first direction X is a third distance D3, the distance between the Drain Drain1 and the other of the data line 141 and the signal line 142 is a fourth distance D4, the size of the Source Source1 in the second direction is L3, the size of the Drain Drain1 in the second direction is L4, (E1. L1/D1+ E2. L3/D3) and (E1. L2/D2+ E2. L4/D4) are in the range of 0.9-1.1, E1 is the dielectric constant of the film between the pixel electrode 122 and the data line 141 or the signal line 142, and E2 is the dielectric constant of the film between the signal line 142 and the Source Source 73758 or Drain 1.

In the array substrate provided by the embodiment of the present disclosure, the pixel electrode 122 is provided with the data line 141 on a first side (for example, the left side in fig. 2) in the first direction X, and is provided with the signal line 142 on a second side (for example, the right side in fig. 2) in the first direction X. On the first side of the pixel electrode 122, the parasitic capacitance Cpd1 between the pixel electrode 122 and the data line 141, E1L 1/D1, and the parasitic capacitance Cpd2 between the Drain1 and the Source1, which are connected to the pixel electrode 122, E2L 3/D3; at this time, the parasitic capacitance C1 between the pixel electrode 122 and the first side conductive structure of the pixel electrode 122 is E1 × L1/D1+ E2 × L3/D3. On the second side of the pixel electrode 122, the parasitic capacitance Cpd3 between the pixel electrode 122 and the signal line 142 is E1L 2/D2, and the parasitic capacitance Cpd4 between the Drain1 connected to the pixel electrode 122 and the data line 141 or the signal line 142 is E2L 4/D4; at this time, the parasitic capacitance C2 between the pixel electrode 122 and the conductive structure on the second side of the pixel electrode 122 is E1 × L2/D2+ E2 × L4/D4. Because the ratio of (E1 × L1/D1+ E2 × L3/D3) to (E1 × L2/D2+ E2 × L4/D4) is in the range of 0.9-1.1, parasitic capacitances generated by the pixel electrode in each sub-pixel unit and other conductive structures on the first side and the second side (e.g., the left side and the right side in fig. 2) of the pixel electrode in the first direction are approximately equal, so that the defect of gray scale V-Crosstalk can be effectively avoided, and the display quality can be improved. The first side and the second side of the pixel electrode are divided by an area bisector of the pixel electrode in the first direction.

In some examples, the ratio of (E1 × L1/D1+ E2 × L3/D3) to (E1 × L2/D2+ E2 × L4/D4) is in the range of 0.95 to 1.05, so that poor gray scale V-Crosstalk can be better avoided and display quality can be improved.

In some examples, the ratio of (E1 × L1/D1+ E2 × L3/D3) to (E1 × L2/D2+ E2 × L4/D4) is in the range of 0.99 to 1.01, so that poor gray scale V-Crosstalk can be better avoided and display quality can be improved.

In some examples, the ratio of (E1 × L1/D1+ E2 × L3/D3) to (E1 × L2/D2+ E2 × L4/D4) is in the range of 0.995 to 1.005, so that poor gray scale V-Crosstalk can be better avoided and display quality can be improved.

In some examples, the ratio of (E1 × L1/D1+ E2 × L3/D3) to (E1 × L2/D2+ E2 × L4/D4) is equal to 1, so that poor gray scale V-Crosstalk can be better avoided and display quality can be improved.

In some examples, as shown in fig. 2, the data line 141 located at one side of the jth sub-pixel column 220 in the first direction is configured to provide a data signal to the jth sub-pixel column 220, and the signal line 142 located at the other side of the jth sub-pixel column 220 in the first direction is configured to provide a data signal to the j +1 th sub-pixel column 220, where j is a positive integer greater than or equal to 1. That is, the data line 141 and the signal line 142 are each configured to transmit a data signal.

In some examples, as shown in fig. 2, the signal line 142 located at one side of the jth sub-pixel column 220 in the first direction and the data line 141 located at one side of the (j +1) th sub-pixel column 220 in the first direction are configured to be connected to the same signal terminal. At this time, the signal line 142 positioned at one side of the jth sub-pixel column 220 in the first direction is configured to transmit the same data signal as the data line 141 positioned at one side of the j +1 th sub-pixel column 220 in the first direction.

In some examples, the signal lines may also be used to transmit other signals, e.g., the signal lines are configured to transmit common electrode signals. For example, as shown in fig. 2, the gate line 130 is disposed to be insulated from the data line 141 and the signal line 142; for example, the data line 141 and the signal line 142 are disposed at the same layer, and an insulating layer may be disposed between the layer where the gate line 130 is disposed and the layer where the data line 141 and the signal line 142 are disposed.

For example, the film layer between the pixel electrode 122 and the data line 141 or the signal line 142 may be an optical adhesive layer; the material of the optical glue layer comprises polyethylene, and the dielectric constant of the optical glue layer can be in the range of 2.2-2.5.

For example, the film between the signal line 142 and the Source1 or the Drain1 may be a passivation layer; the passivation layer may be made of silicon nitride, silicon oxide or silicon oxynitride, and may have a dielectric constant ranging from 1.56 to 3.9.

For example, the substrate base plate 110 may be a glass base plate, a plastic base plate, a quartz base plate, or a polyimide base plate. Of course, the embodiments of the present disclosure include but are not limited thereto, and other substrates may be used as the substrate.

For example, the gate line 130, the data line 141, and the signal line 142 may be made of the same conductive material, or may be made of different conductive materials. For example, the material of the gate line 130, the data line 141, and the signal line 142 includes one or more selected from aluminum, aluminum alloy, copper alloy, molybdenum, and molybdenum-aluminum alloy.

For example, the first distance D1 between the pixel electrode 122 and the data line 141 may have a value in a range of 10-12 micrometers, for example, 10.9 micrometers; the second distance D2 between the pixel electrode 122 and the signal line 142 may also be 10-12 microns, such as 10.9 microns; the third distance D3 between the Drain1 and the Source1 in the first direction X may range from 5.1 to 6.4 micrometers, for example, 5.79 micrometers; the fourth distance D4 between the Drain1 and the signal line 142 may be in a range of 5.1-6.4 microns, such as 5.79 microns.

For example, the length L1 of the side of the pixel electrode 122 close to the data line 141 may be in a range of 110 microns and 120 microns, for example, 114 microns; the side length L2 of the pixel electrode 122 near the signal line 142 may also be 110-120 microns, such as 114 microns; the dimension L3 of the Source1 in the second direction can range from 20 microns to 24 microns, such as 22 microns; the dimension L4 of the Drain in the second direction may range from 20 to 24 microns, such as 22 microns.

In some examples, E1 ═ 2.3, E2 ═ 1.6, D1 ═ 11 μm, L1 ═ 114 μm, D2 ═ 10.1 μm, L2 ═ 119 μm, D3 ═ 5.2 μm, L3 ═ 22.1 μm, D4 ═ 5.1 μm, and L4 ═ 22.1 μm, so (E1 ═ L1/D1+ E2 ═ L3/D3)/(E1 ═ L2/D2+ E2 ═ L4/D4) ═ 0.900.

In some examples, E1 ═ 2.3, E2 ═ 1.6, D1 ═ 11 μm, L1 ═ 114 μm, D2 ═ 10.6 μm, L2 ═ 114 μm, D3 ═ 5.2 μm, L3 ═ 22.1 μm, D4 ═ 5.1 μm, L4 ═ 23.9 μm, and thus, (E1 ═ L1/D1+ E2 ═ L3/D3)/(E1 ═ L2/D2+ E2 ═ L4/D4) ═ 0.950.

In some examples, E1 ═ 2.3, E2 ═ 1.6, D1 ═ 11 μm, L1 ═ 114 μm, D2 ═ 11 μm, L2 ═ 114 μm, D3 ═ 5.2 μm, L3 ═ 22.1 μm, D4 ═ 5.2 μm, and L4 ═ 22.1 μm, so (E1 ═ L1/D1+ E2 ═ L3/D3)/(E1 ═ L2/D2+ E2 ═ L4/D4) ═ 1.

In some examples, E1 ═ 2.3, E2 ═ 1.6, D1 ═ 11 μm, L1 ═ 114 μm, D2 ═ 11.1 μm, L2 ═ 114 μm, D3 ═ 5.2 μm, L3 ═ 22.1 μm, D4 ═ 6.4 μm, and L4 ═ 22.1 μm, so (E1 ═ L1/D1+ E2 ═ L3/D3)/(E1 ═ L2/D2+ E2 ═ L4/D4) ═ 1.051.

In some examples, E1 ═ 2.3, E2 ═ 1.6, D1 ═ 11 μm, L1 ═ 114 μm, D2 ═ 11.8 μm, L2 ═ 114 μm, D3 ═ 5.2 μm, L3 ═ 22.1 μm, D4 ═ 6.4 μm, and L4 ═ 22.6 μm, so (E1 ═ L1/D1+ E2 ═ L3/D3)/(E1 ═ L2/D2+ E2 ═ L4/D4) ═ 1.099.

In some examples, as shown in fig. 2, the connection 1220 of the pixel electrode 122 and the Drain1 is located on an area bisector of the pixel electrode 122 in the first direction. Therefore, the parasitic capacitance Cpd2 between the Drain electrode Drain1 and the Source electrode Source1 and the parasitic capacitance Cpd4 between the Drain electrode Drain1 and the signal line 142 are both connected to the middle of the pixel electrode 122 in the first direction, so that the influence on the parasitic capacitance of the pixel electrode 122 on both sides in the first direction is more balanced, thereby further effectively avoiding the poor gray scale V-Cross and improving the display quality. It should be noted that the area bisector mentioned above may be an area bisector of an orthographic projection of the pixel electrode on the substrate.

In some examples, as shown in fig. 2, a side length L1 of the pixel electrode 122 near the data line 141 is equal to a side length L2 of the pixel electrode 122 near the signal line 142, and the first distance D1 is equal to the second distance D2. Therefore, the parasitic capacitance Cpd 1-E1-L1/D1 between the pixel electrode 122 and the data line 141 and the parasitic capacitance Cpd 3-E1-L2/D2 between the pixel electrode 122 and the signal line 142 are equal, so that the parasitic capacitances generated by the data line 141 and the signal line 142 on both sides of the pixel electrode 122 and the pixel electrode 122 can be ensured to be equal.

In some examples, as shown in fig. 2, a dimension L3 of the Source1 in the second direction Y is equal to a dimension L4 of the Drain1 in the second direction Y, and the third distance D3 is equal to the fourth distance D4. Therefore, the parasitic capacitances Cpd 2-E2-L3/D3 between the Drain1 and the Source1 and the parasitic capacitances Cpd 4-E2-L4/D4 between the Drain1 and the signal line 142 are equal, so that the parasitic capacitances generated by the Source1 and the signal line 142 on the left and right sides of the Drain1 and the Drain Drain1 are equal.

In the array substrate provided in the above example, by respectively setting the parasitic capacitances Cpd1 ═ E1 ═ L1/D1 between the pixel electrode 122 and the data line 141 and Cpd3 ═ E1 ═ L2/D2 between the pixel electrode 122 and the signal line 142 to be equal, and setting the parasitic capacitances Cpd2 between the Drain 2 and the Source 2 to be equal to E2 ═ L2/D2 and the parasitic capacitances Cpd2 between the Drain Drain 2 and the signal line 142 to be equal to E2 ═ L2/D2, it is possible to better ensure that E2 × L2/D2+ E2L 2/D2 ═ E2/D2 to be equal, and further possible to avoid the Crosstalk (cross talk) effectively.

In some examples, as shown in fig. 2, each sub-pixel unit 120 includes a first region 120A and a second region 120B sequentially arranged in the second direction Y, the pixel electrode 122 is located in the first region 120A, and the driving transistor T1 is located in the second region 120B. At this time, the first region 120A may be a light emitting region or a color filter region, and the second region 120B may be a driving region or a TFT region.

In some examples, as shown in fig. 2, in the second region 120B, the Source1 and the data line 141 or the signal line 142 connected to the Source1 are oppositely disposed at an interval. At this time, the array substrate 100 further includes a conductive connection block 151, and the Source1 is connected to the data line 141 or the signal line 142 connected to the Source1 through the conductive connection block 151; the distance between the Source1 and the data line 141 or the signal line 142 connected to the Source1 is a fifth distance D5, and the fifth distance D5 is equal to the fourth distance D4. That is, the third distance D3, the fourth distance D4, and the fifth distance D5 are all equal. Thus, the driving transistor T1 is located on the area bisector of the pixel electrode 122 in the first direction as a whole, so that the symmetry of the driving transistor T1 is improved, and the symmetry of the sub-pixel unit 120 is improved.

As shown in fig. 2, fig. 2 shows 4 sub-pixel units 120, including a first sub-pixel unit 1201, a second sub-pixel unit 1202, a third sub-pixel unit 1203, and a fourth sub-pixel unit 1204; the first sub-pixel unit 1201, the second sub-pixel unit 1202, the third sub-pixel unit 1203 and the fourth sub-pixel unit 1204 are sequentially arranged along a first direction X; in the first sub-pixel unit 1201 and the second sub-pixel unit 1202, the Source1 is connected to the data line 141; in the third sub-pixel unit 1203 and the fourth sub-pixel unit 1204, a Source1 is connected to the signal line 142. Thus, with the 4 sub-pixel units 120 as a whole, the symmetry of the 4 sub-pixel units 120 in the first direction is improved.

In some examples, as shown in fig. 2, an orthographic projection of the pixel electrode 122 on the substrate 110 is axisymmetric with respect to an area bisector of the pixel electrode 122 in the first direction, so that the symmetry of the pixel electrode 122 may be improved.

In some examples, as shown in fig. 2, the pixel electrode 122 includes a first domain 161, a second domain 162, a third domain 163, and a fourth domain 164; the first domain 161 and the second domain 162 are axisymmetric with respect to a bisector of an area of the pixel electrode 122 in the first direction X, and the third domain 163 and the fourth domain 164 are axisymmetric with respect to a bisector of an area of the pixel electrode 122 in the first direction X; the first domain 161 and the third domain 163 are sequentially disposed along the second direction Y, and the second domain 162 and the fourth domain 163 are sequentially disposed along the Y second direction. Thus, by arranging the pixel electrode 122 as the first domain 161, the second domain 162, the third domain 163 and the fourth domain 164, the array substrate may reduce the color shift phenomenon and improve the display effect.

In addition, since the first domain 161 and the second domain 162 are axisymmetric with respect to a bisector of an area of the pixel electrode 122 in the first direction X, and the third domain 163 and the fourth domain 164 are axisymmetric with respect to a bisector of an area of the pixel electrode 122 in the first direction X, the pixel electrode 122 has high symmetry.

In some examples, as shown in fig. 2, the pixel electrode 122 further includes an intermediate portion 1225, the intermediate portion 1225 extending in the second direction Y and being located between the first domain 161 and the second domain 162, and between the third domain 163 and the fourth domain 164; the Drain1 is connected to the middle portion 1225 of the pixel electrode 122. Therefore, the parasitic capacitance Cpd2 between the Drain electrode Drain1 and the Source electrode Source1 and the parasitic capacitance Cpd4 between the Drain electrode Drain1 and the signal line 142 are both connected to the middle of the pixel electrode 122 in the first direction, so that the influence on the parasitic capacitance of the pixel electrode 122 on both sides in the first direction is more balanced, thereby further effectively avoiding the poor gray scale V-Cross and improving the display quality.

In some examples, as shown in fig. 2, the pixel electrode 122 includes a plurality of first slits 1224A disposed at intervals, located in the first domain 161; a plurality of second slits 1224B arranged at intervals, located in the second domain 162; a plurality of third slits 1224C provided at intervals and located in the third domain 163; and a plurality of fourth slits 1224D arranged at intervals, located in the fourth domain 164.

Fig. 3 is an enlarged schematic view of a driving transistor in an array substrate according to an embodiment of the disclosure. As shown in fig. 3, the sub-pixel unit 120 has a width Wpixel in the first direction X, the driving transistor T1 includes an active layer a1, a length of a channel region of the active layer a1 in the first direction X is L, and a length of a channel region of the active layer a in the second direction Y is W; the Source1 has a width Wsource in the first direction X, the Drain1 has a width wdain in the first direction X, and the data line 141 or the signal line 142 has a width Wdata in the first direction X. At this time, the length L of the channel region of the active layer a1 in the first direction X satisfies the following formula:

Wsource+Wdrain＜L＜(Wpixel-2Wdata-Wsource-Wdrain)/3。

in bookThe disclosed embodiment provides an array substrate in which the turn-on current I of the driving transistor T1_onThe calculation formula of (a) is as follows:

wherein W, L are the width and length, μ, of the channel region of the active layer A1 of the driving transistor T1, respectively_nFor equivalent electron mobility, C_SiNxTo drive the capacitance of transistor T1, V_THTo drive the threshold voltage, V, of the transistor T1_GAnd V_DIs the voltage of the gate G1 and Drain1 of the drive transistor T1 relative to the Source 1.

It can be seen from the above formula that the turn-on current I of the driving transistor T1 is influenced_onMainly the ratio W/L of the width to the length of the channel region, the electron mobility, etc. In order to obtain a large on-current I_onThe value of the ratio W/L of the width to the length of the channel region needs to be set large. Therefore, the following formula is satisfied by making the length of the channel region of the active layer a1 in the first direction X L: wsource + Wdrain < L < (Wpixel-2Wdata-Wsource-Wdrain)/3, the length of the channel region of the active layer A1 in the first direction X can be reduced to L, and therefore the ratio W/L of the width and the length of the channel of the driving transistor T1 can be increased, and the turn-on current can be increased.

In some examples, a length L of a channel region of the active layer a1 in the first direction X satisfies the following formula: wsource + Wdrain < L < (Wpixel-2 Wdata-Wsource-Wdrain)/4. Thus, by making the length L of the channel region of the active layer a1 in the first direction X, the following formula is satisfied: wsource + Wdrain < L < (Wpixel-2Wdata-Wsource-Wdrain)/4, the length of the channel region of the active layer A1 in the first direction X can be further reduced to L, and therefore the ratio W/L of the width to the length of the channel of the driving transistor T1 can be increased, and the turn-on current can be increased.

Fig. 4 is a schematic plan view of another array substrate according to an embodiment of the present disclosure. As shown in fig. 4, the Source1 is a part of the data line 141 or the signal line 142 connected to the Source 1. Thus, the array substrate 100 does not need to be provided with the above-mentioned conductive connection block, and the data line 141 or the signal line 142 connected to the Source1 directly overlaps the active layer a1 of the driving transistor T1.

As shown in fig. 4, the distance between the pixel electrode 122 and the data line 141 is a first distance D1, the distance between the pixel electrode 122 and the signal line 142 is a second distance D2, the side length of the pixel electrode 122 close to the data line 141 is L1, and the side length of the pixel electrode 122 close to the signal line 142 is L2; the distance between the Drain1 and the Source1 in the first direction is a third distance D3, the distance between the Drain1 and the signal line 142 is a fourth distance D4, the size of the Drain1 in the second direction is L3, the size of the Source1 in the second direction is L4, and the above-mentioned L1, L2, L3, L4, D1, D2, D3, and D4 also satisfy the following formulas:

E1*L1/D1+E2*L3/D3＝E1*L2/D2+E2*L4/D4，

wherein, E1 is the dielectric constant of the film between the pixel electrode 122 and the data line 141 or the signal line 142, and E2 is the dielectric constant of the film between the signal line 142 and the Source1 or the Drain 1.

In the array substrate, the pixel electrode 122 is provided with a data line 141 on a first side (for example, a left side in fig. 4) in the first direction X, and a signal line 142 on a second side (for example, a right side in fig. 4) in the first direction X. On the first side of the pixel electrode 122, the parasitic capacitance Cpd1 between the pixel electrode 122 and the data line 141, E1L 1/D1, and the parasitic capacitance Cpd2 between the Drain1 and the Source1, which are connected to the pixel electrode 122, E2L 3/D3; at this time, the parasitic capacitance C1 between the pixel electrode 122 and the first side conductive structure of the pixel electrode 122 is E1 × L1/D1+ E2 × L3/D3. On the second side of the pixel electrode 122, the parasitic capacitance Cpd3 ═ E1 ═ L2/D2 between the pixel electrode 122 and the signal line 142, and the parasitic capacitance Cpd4 ═ E2 ═ L4/D4 between the Drain1 connected to the pixel electrode 122 and the signal line 142; at this time, the parasitic capacitance C2 between the pixel electrode 122 and the conductive structure on the second side of the pixel electrode 122 is E1 × L2/D2+ E2 × L4/D4. Since the ratio of (E1 × L1/D1+ E2 × L3/D3) to (E1 × L2/D2+ E2 × L4/D4) is in the range of 0.9-1.1, parasitic capacitances generated by the pixel electrode in each sub-pixel unit and other conductive structures on the first side and the second side (e.g., the left side and the right side in fig. 4) of the pixel electrode in the first direction are approximately equal, so that the defect of gray scale V-Crosstalk can be effectively avoided, and the display quality can be improved. The first side and the second side of the pixel electrode are divided by an area bisector of the pixel electrode in the first direction.

Fig. 5 is an enlarged schematic view of a driving transistor in another array substrate according to an embodiment of the disclosure. As shown in fig. 5, the width of the sub-pixel unit 120 in the first direction X is Wpixel, the driving transistor T1 includes an active layer a1, the length of the channel region of the active layer a1 in the first direction X is L, the length of the channel region of the active layer a1 in the second direction Y is W, the width of the Source1 in the first direction is Wsource, the width of the Drain1 in the first direction is Wdrain, the widths of the data line 141 and the signal line 142 in the first direction are Wdata, and the length of the channel region of the active layer in the first direction L satisfies the following formula:

Wsource+Wdrain＜L＜(Wpixel-2Wdata-Wdrain)/2。

in the array substrate, the following formula is satisfied by making the length of the channel region of the active layer a1 in the first direction X be L: wsource + Wdrain < L < (Wpixel-2Wdata-Wdrain)/2, the length of the channel region of the active layer A1 in the first direction X can be reduced to L, and the ratio W/L of the width and the length of the channel of the driving transistor T1 can be increased, thereby increasing the turn-on current.

For example, the width Wpixel of the sub-pixel element 120 in the first direction X is in the range of 60-64 microns, such as 62 microns; the length L of the channel region of the active layer a1 in the first direction X may range from 5-7 microns, such as 5.79 microns, the length W of the channel region of the active layer a1 in the second direction Y may range from 9-12.5 microns, such as 11.24 microns, the width Wsource of the Source1 in the first direction may range from 2-4 microns, such as 2.57 microns, the width Wdrain of the Drain1 in the first direction may range from 2-4 microns, such as 2.57 microns, and the width Wdata of the data line 141 and the signal line 142 in the first direction may range from 4-6 microns, such as 5.4 microns. At this time, the current I is turned on_onThe calculation formula of (2):

can be simplified into

Where k may range from 1.05 to 1.20, e.g., k 1.11.

Fig. 6A is a schematic plan view of another array substrate according to an embodiment of the present disclosure; fig. 6B is a schematic plan view of another array substrate according to an embodiment of the disclosure. As shown in fig. 6A, the plurality of sub-pixel units 120 form n sub-pixel rows 210 arranged in the second direction Y, and the array substrate 100 includes n gate lines 130, which are arranged in one-to-one correspondence with the n sub-pixel rows 210; the kth gate line 130 and the (k +1) th gate line 130 form a (k +1)/2 th gate line group 1300. At this time, the array substrate 100 further includes a first vertical gate line 131 and a second vertical gate line 132 respectively located at two sides of the plurality of sub-pixel units 120 in the first direction, and in the (k +1)/2 th gate line group 1300, the kth gate line 130 and the (k +1) th gate line 130 are connected through the first vertical gate line 131 and the second vertical gate line 132, k may be an odd number greater than or equal to 1, and n is a positive integer greater than k. Therefore, one gate line group 1300 can have an annular structure, so that signal delay on the gate lines can be reduced, and the display quality of the array substrate is improved.

In some examples, as shown in fig. 6A and 6B, the first and second

vertical gate lines

131 and 132 are disposed at the same layer as the data line 141.

In some examples, as shown in fig. 6A and 6B, the first vertical gate line 131 is connected to the kth gate line 130 through a first via connection structure H1, the first vertical gate line 131 is connected to the (k +1) th gate line 130 through a second via connection structure H2, the second vertical gate line 132 is connected to the kth gate line 130 through a third via connection structure H3, and the second vertical gate line 132 is connected to the (k +1) th gate line 130 through a fourth via connection structure H4. It should be noted that the above-mentioned via connection structure generally includes a via hole in an insulating layer between two conductive film layers and a conductive structure located in the via hole, so that the two conductive film layers can be electrically connected.

In some examples, as shown in fig. 6B, the array substrate 100 further includes at least one middle vertical gate line 135 between two adjacent sub-pixel columns 220; in the (k +1)/2 gate line group 1300, the k gate line 130 and the k +1 gate line 130 are connected by the middle vertical gate line 135. Therefore, the middle vertical grid line can be used for connecting two grid lines positioned in the same grid line group, so that when the first vertical grid line or the second vertical grid line is short-circuited, the electric connection of the two grid lines of the same grid line group can be ensured, and the signal delay of the sub-pixel unit positioned in the middle of the array substrate can be reduced.

In some examples, as shown in fig. 6B, the middle vertical gate line 135 is disposed on the same layer as the gate line 130, so that an additional via connection structure is not required, and the middle vertical gate line can be formed using the same metal film layer using the same patterning process.

In some examples, as shown in fig. 6A and 6B, the data line 141 and the signal line 142 are both configured to transmit data signals, the Source1 of a portion of the sub-pixel cells 120 in the sub-pixel column 220 is connected to the data line 141, and the Source1 of another portion of the sub-pixel cells 120 in the sub-pixel column 220 is connected to the signal line 142.

Fig. 7A is a schematic view of another array substrate according to an embodiment of the present disclosure; fig. 7B is a schematic view of another array substrate according to an embodiment of the disclosure. As shown in fig. 7A, the array substrate 100 further includes a first common electrode line 171 and a second common electrode line 172; the first common electrode lines 171 extend in the first direction X, and the second common electrode lines 172 extend in the second direction Y; each sub-pixel unit 120 includes a first region 120A and a second region 120B sequentially arranged in the second direction Y, the pixel electrode 122 is located in the first region 120A, and the driving transistor T1 is located in the second region 120B; the first common electrode line 171 is located between two sub-pixels 120 adjacent in the second direction Y, and between the first region 120A and the second region 120B of the same sub-pixel 120; the second common electrode line 172 is positioned between two adjacent sub-pixel columns 220, so that mutual influence between data signals of the adjacent sub-pixel units 120 can be shielded.

In some examples, as shown in fig. 7A, each sub-pixel unit 120 includes a first region 120A and a second region 120B sequentially arranged in the second direction Y, the pixel electrode 122 is located in the first region 120A, and the driving transistor T1 is located in the second region 120B; the width of the portion of the second common electrode line 172 located in the first area 120A is greater than the width of the portion of the second common electrode line 172 located in the second area 120B, that is, the width of the orthogonal projection of the portion of the second common electrode line located in the first area on the substrate is greater than the width of the orthogonal projection of the portion of the second common electrode line located in the second area on the substrate. Therefore, when the array substrate adopts a coa (color filter on array) structure, the color filter can be disposed in the first region 120A, and at this time, by setting the width of the second common electrode line 172 to be larger, the array substrate 100 can use the second common electrode line 172 as a black matrix to achieve a light shielding effect.

In some examples, as shown in fig. 7A and 7B, the second common electrode lines 172 include gate layer common electrode lines 1721 and data line layer common electrode lines 1722; the gate layer common electrode line 1721 is disposed on the same layer as the gate line 130 and connected to the data line layer common electrode line 1722 through a via hole, so that the resistance of the second common electrode line 172 can be reduced.

In some examples, as shown in fig. 7A and 7B, the first common electrode line 171 is disposed on the same layer as the gate line 130, the first common electrode line 171 includes at least one first notch 1710 and first sub-common electrode lines 1712 located at both sides of the first notch 1710, and the middle vertical gate line 135 passes through the first notch 1710 and is disposed to be spaced apart from the first sub-common electrode lines 1712 in an insulating manner, respectively. Thus, by providing the first notch 1710 on the first common electrode line 171, the above-described intermediate vertical gate line 135 may be conveniently provided.

In some examples, as shown in fig. 7A and 7B, two first common electrode lines 171 are disposed between the kth gate line 130 and the kth +1 gate line 130 within the (k +1)/2 th gate line group 1300 and respectively include first gaps 1710, and the middle vertical gate line 135 passes through the two first gaps 1710 of the two first common electrode lines 171 to connect the kth gate line 130 and the kth +1 th gate line 130.

In some examples, as shown in fig. 7A and 7B, in the case where the middle vertical gate line 135 described above is provided, since the middle vertical gate line 135 is provided at the same layer as the gate line 130; at this time, the second common electrode line 172 at the position of the middle vertical gate line 135 may not include the gate layer common electrode line 1721. In some examples, as shown in fig. 7A and 7B, the second common electrode line 172 is located between the l-th sub-pixel column 220 and the l + 1-th sub-pixel column 220, a distance between the second common electrode line 172 and the signal line 142 corresponding to the l-th sub-pixel column 220 is equal to a distance between the second common electrode line 172 and the data line 141 corresponding to the l + 1-th sub-pixel column 220, or a distance between the second common electrode line 172 and the data line 141 corresponding to the l-th sub-pixel column 220 is equal to a distance between the second common electrode line 172 and the signal line 142 corresponding to the l + 1-th sub-pixel column 220, and l is a positive integer greater than or equal to 1.

Fig. 8A is a schematic cross-sectional view of an array substrate along line AB in fig. 7A according to an embodiment of the present disclosure. As shown in fig. 8A, the second common electrode lines 172 include gate layer common electrode lines 1721 and data line layer common electrode lines 1722; the gate layer common electrode line 1721 is disposed on the same layer as the gate line 130 and connected to the data line layer common electrode line 1722 through the fifth via connection structure H5, so that the resistance of the second common electrode line 172 can be reduced.

In some examples, as shown in fig. 8A, the array substrate 100 further includes a first color filter 191 and a second color filter 192, and orthogonal projections of the first color filter 191 and the second color filter 192 on the substrate 110 overlap with an orthogonal projection of the second common electrode line 172 on the substrate 110. At this time, by setting the width of the second common electrode line 172 to be larger, the array substrate 100 can use the second common electrode line 172 as a black matrix to achieve a light shielding effect.

For example, the width of the portion of the second common electrode line 172 located in the first region 120A may be 12.3 micrometers, and the width of the portion of the second common electrode line 172 located in the second region 120B may be 5.5 micrometers.

For example, as shown in fig. 8A, the array substrate 100 further includes a shielding electrode 195 on the substrate 110 and disposed at the same layer as the gate line 130. The shield electrode 195 serves to prevent signal crosstalk between the data line 141 or the signal line 142 and the second common electrode line 172, thereby improving display quality.

For example, as shown in fig. 8A, the shielding electrode 195 may be disposed between the data line 141 and the signal line 142 of the same sub-pixel unit 120, so that signal crosstalk between the data line 141 and the signal line 142 of the same sub-pixel unit 120 may also be prevented.

For example, shield electrode 195 can be fabricated using a transparent conductive oxide material, such as ITO (indium tin oxide). The width of the shield electrode 195 in the first direction X is in the range of 3-5 microns, for example 4 microns; the thickness of shield electrode 195 in the range perpendicular to substrate base plate 110 is

For example

In some examples, as shown in fig. 8A, the orthographic projection of the shielding electrode 195 on the substrate base plate 110 is located between the orthographic projection of the second common electrode line 172 on the substrate base plate 110 and the orthographic projection of the data line 141 on the substrate base plate 110, and between the orthographic projection of the second common electrode line 172 on the substrate base plate 110 and the orthographic projection of the signal line 142 on the substrate base plate 110.

Fig. 8B is a schematic cross-sectional view of an array substrate along the CD line in fig. 7A according to an embodiment of the disclosure; as shown in fig. 8B, the orthographic projection of the shield electrode 195 on the substrate base 110 is also located between the orthographic projection of the data line 141 on the substrate base 110 and the orthographic projection of the signal line 142 on the substrate base 110.

Fig. 9 is a schematic plan view of another array substrate according to an embodiment of the present disclosure. As shown in fig. 9, each sub-pixel unit 120 includes a first region 120A and a second region 120B sequentially arranged in the second direction Y, the pixel electrode 122 is located in the first region 120A, and the driving transistor T1 is located in the second region 120B; the distance in the first direction between the portion of the data line 141 in the first region 120A and the portion of the signal line 142 in the first region 120A is smaller than the distance in the first direction between the portion of the data line 141 in the second region 120B and the portion of the signal line 142 in the second region 120B; the data line 141 includes a first inclined connection 1415 to connect a portion of the data line 141 in the first region 120A and a portion of the data line 141 in the second region 120B, and the signal line 142 includes a second inclined connection 1425 to connect a portion of the signal line 142 in the first region 120A and a portion of the signal line 142 in the second region 120B.

In some examples, as shown in fig. 9, an orthogonal projection of the first inclined connection part 1415 on the base substrate 110 overlaps an orthogonal projection of the first common electrode lines 171 on the base substrate 110, and an orthogonal projection of the second inclined connection part 1425 on the base substrate 110 overlaps an orthogonal projection of the first common electrode lines 171 on the base substrate 110.

In some examples, as shown in fig. 9, an orthographic projection of the via hole H7 of the pixel electrode 122 connected to the Drain1 of the driving transistor T1 on the substrate base plate 110 is located between the first and second

inclined connection portions

1415 and 1425.

Fig. 10 is a schematic plan view of another array substrate according to an embodiment of the present disclosure. As shown in fig. 10, the array substrate 100 further includes: a plurality of gate lead-out lines 180, each gate lead-out line 180 being located between two adjacent sub-pixel columns 220; each gate lead-out line 180 includes: a first gate lead line 181 disposed at the same layer as the data line 141 and configured to connect a gate signal; and a second gate lead-out line 182 disposed at the same layer as the gate line 130 and configured to be connected to the corresponding gate line 130, the first gate lead-out line 181 and the second gate lead-out line 182 being connected through a sixth via connection structure H6.

In some examples, as shown in fig. 10, the gate lead line 180 is configured to be electrically connected to the (m +1)/2 th gate line group 1300, the second gate lead line 182 is directly connected to the mth gate line 130, and m is an odd number greater than or equal to 1; the (m-1) th gate line 130 comprises a second notch 1302, the three first common electrode lines 171 are arranged between the (m-2) th gate line 130 and the (m-1) th gate line 130 and respectively comprise a first notch 1710, and the second gate outgoing line 182 passes through the second notch 1302 of the (m-1) th gate line 130 and the three first notches 1710 of the three first common electrode lines 171 and extends to the position of the sixth via connection structure H6; the sixth via connection structure H6 is located between the m-2 th gate line 130 and the first common electrode line 171, and the first gate outgoing line 181 is connected to the second gate outgoing line 182 through the sixth via connection structure H6.

At least one embodiment of the present disclosure also provides a display device. Fig. 11 is a schematic diagram of a display device according to an embodiment of the disclosure. As shown in fig. 11, the display device 400 includes the array substrate 100 of any one of the above. In the array substrate, parasitic capacitances generated by other conductive structures on two sides of the pixel electrode in each sub-pixel unit and the pixel electrode in the first direction are approximately equal, so that poor gray scale V-Crosstalk (Crosstalk) can be effectively avoided, and the display quality is improved. Therefore, the display device can also effectively avoid poor gray scale V-Crosstalk and improve the display quality.

Fig. 12 is a schematic cross-sectional view of a display device according to an embodiment of the disclosure. As shown in fig. 12, the display device 400 further includes a counter substrate 300 and a liquid crystal layer 350, the counter substrate 300 is disposed opposite to the array substrate 100 with a gap therebetween, and the liquid crystal layer 350 is disposed between the counter substrate 300 and the array substrate 100; the opposite substrate 300 includes a common electrode 310; the common electrode 310 is disposed opposite to and spaced apart from the pixel electrode 122 on the array substrate 100, and is configured to form an electric field to drive the liquid crystal molecules in the liquid crystal layer 350 to be deflected. It can be seen that the display device shown in fig. 12 employs a VA mode, but of course, the embodiments of the present disclosure include but are not limited thereto, and the display device may also employ an ADS mode or an IPS mode, i.e., the common electrode 310 is also disposed on the array substrate 100.

In some examples, the display device may be any product or component having a display function, such as a liquid crystal display, a smart phone, a tablet computer, a television, a display, a smart watch, a notebook computer, a digital photo frame, and a navigator.

The following points need to be explained:

(1) in the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are referred to, and other structures may refer to general designs.

(2) Features of the same embodiment of the disclosure and of different embodiments may be combined with each other without conflict.

The above are merely exemplary embodiments of the present disclosure and are not intended to limit the scope of the present disclosure, which is defined by the appended claims.

Claims

1. An array substrate, comprising:

a substrate base plate;

a plurality of sub-pixel units on the substrate and arranged in an array along a first direction and a second direction to form sub-pixel rows extending in the first direction and sub-pixel columns extending in the second direction;

a gate line on the substrate, extending in the first direction, and configured to provide a gate signal to the subpixel row;

the data line is positioned on the substrate base plate and extends along the second direction; and

a signal line on the substrate base plate and extending in the second direction;

wherein the data line and the signal line are respectively located on both sides of the sub-pixel column in the first direction,

each sub-pixel unit comprises a pixel electrode, the distance between the pixel electrode and the data line is a first distance D1, the distance between the pixel electrode and the signal line is a second distance D2, the side length of the pixel electrode close to the data line is L1, the side length of the pixel electrode close to the signal line is L2,

each of the sub-pixel units further includes a driving transistor including a source electrode connected to one of the data line and the signal line and a drain electrode connected to the pixel electrode,

a distance between the drain and the source in the first direction is a third distance D3, a distance between the drain and the other of the data line and the signal line is a fourth distance D4, a size of the source in the second direction is L3, a size of the drain in the second direction is L4,

wherein a ratio of (E1 × L1/D1+ E2 × L3/D3) to (E1 × L2/D2+ E2 × L4/D4) is in a range of 0.9 to 1.1, E1 is a dielectric constant of a film layer between the pixel electrode and the data line or the signal line, and E2 is a dielectric constant of a film layer between the signal line and the source electrode or the drain electrode.

2. The array substrate of claim 1, wherein the ratio of (E1 x L1/D1+ E2 x L3/D3) to (E1 x L2/D2+ E2 x L4/D4) is in the range of 0.95-1.05.

3. The array substrate of claim 2, wherein (E1 × L1/D1+ E2 × L3/D3) ═ E1 × L2/D2+ E2 × L4/D4).

4. The array substrate of claim 1, wherein the data line and the signal line are configured to transmit data signals, the sources of some of the sub-pixel units in the sub-pixel column are connected to the data line, and the sources of other some of the sub-pixel units in the sub-pixel column are connected to the signal line.

5. The array substrate of claim 1, wherein the data line on one side of the jth sub-pixel column in the first direction is configured to provide a data signal to the jth sub-pixel column, and the signal line on the other side of the jth sub-pixel column in the first direction is configured to provide a data signal to the j +1 th sub-pixel column, where j is a positive integer greater than or equal to 1.

6. The array substrate of claim 5, wherein the signal line on one side of the jth sub-pixel column in the first direction and the data line on one side of the (j +1) th sub-pixel column in the first direction are configured to be connected to a same signal terminal.

7. The array substrate of claim 1, wherein the signal lines are configured to transmit a common electrode signal.

8. The array substrate of any one of claims 1-7, wherein the connection of the pixel electrode and the drain electrode is located on a bisector of an area of the pixel electrode in the first direction.

9. The array substrate of any one of claims 1-7, wherein a side length L1 of the pixel electrode near the data line is equal to a side length L2 of the pixel electrode near the signal line,

the first distance D1 is equal to the second distance D2.

10. The array substrate of any one of claims 1-7, wherein a dimension L3 of the source electrode in the second direction and a dimension L4 of the drain electrode in the second direction are equal, and the third distance D3 and the fourth distance D4 are equal.

11. The array substrate of any one of claims 1-7, wherein each of the sub-pixel units comprises a first region and a second region sequentially arranged along the second direction, the pixel electrode is located in the first region, and the driving transistor is located in the second region.

12. The array substrate of claim 11, wherein the source electrode and the data line or the signal line connected to the source electrode are oppositely spaced,

the array substrate further comprises a conductive connection block, the source electrode is connected with the data line or the signal line connected with the source electrode through the conductive connection block,

the distance between the source electrode and the data line or the signal line connected to the source electrode is a fifth distance D5, and the fifth distance D5 is equal to the fourth distance D4.

13. The array substrate of claim 12, wherein the width of the sub-pixel unit in the first direction is Wpixel, wherein the driving transistor comprises an active layer, wherein the length of a channel region of the active layer in the first direction is L, the length of a channel region of the active layer in the second direction is W, the width of the source electrode in the first direction is Wsource, the width of the drain electrode in the first direction is Wdrain, and the width of the data line and the signal line in the first direction is Wdata,

the length of the channel region of the active layer in the first direction is L, and the following formula is satisfied:

Wsource+Wdrain＜L＜(Wpixel-2Wdata-Wsource-Wdrain)/3。

14. the array substrate of claim 13, wherein a length L of the channel region of the active layer in the first direction satisfies the following formula:

Wsource+Wdrain＜L＜(Wpixel-2Wdata-Wsource-Wdrain)/4。

15. the array substrate of claim 11, wherein the source electrode is a portion of the data line or the signal line connected to the source electrode.

16. The array substrate of claim 15, wherein the width of the sub-pixel unit in the first direction is Wpixel, wherein the driving transistor comprises an active layer, wherein the length of a channel region of the active layer in the first direction is L, the length of a channel region of the active layer in the second direction is W, the width of the source electrode in the first direction is Wsource, the width of the drain electrode in the first direction is Wdrain, and the width of the data line and the signal line in the first direction is Wdata,

Wsource+Wdrain＜L＜(Wpixel-2Wdata-Wdrain)/2。

17. the array substrate of any one of claims 1-7, wherein an orthographic projection of the pixel electrode on the substrate is axisymmetric with respect to a bisector of an area of the pixel electrode in the first direction.

18. The array substrate of claim 17, wherein the pixel electrode comprises a first domain, a second domain, a third domain, and a fourth domain,

the first domain and the second domain are axisymmetric with respect to a bisector of an area of the pixel electrode in the first direction, the third domain and the fourth domain are axisymmetric with respect to a bisector of an area of the pixel electrode in the first direction,

the first domain and the third domain are sequentially arranged along the second direction, and the second domain and the fourth domain are sequentially arranged along the second direction.

19. The array substrate of claim 18, wherein the pixel electrode comprises a middle portion extending in the second direction and located between the first domain and the second domain, between the third domain and the fourth domain,

the drain electrode is connected to the middle portion of the pixel electrode.

20. The array substrate of claim 19, wherein the pixel electrode comprises:

a plurality of first slits arranged at intervals and positioned in the first domain;

a plurality of second slits arranged at intervals and positioned in the second domain;

a plurality of third slits arranged at intervals and positioned in the third domain; and

and a plurality of fourth slits arranged at intervals are positioned in the fourth domain.

21. The array substrate of any one of claims 1-7, wherein the plurality of sub-pixel units form n sub-pixel rows arranged in the second direction, the array substrate comprises n gate lines arranged in a one-to-one correspondence with the n sub-pixel rows,

the kth gate line and the (k +1) th gate line form a (k +1)/2 gate line group,

the array substrate further comprises a first vertical grid line and a second vertical grid line which are respectively positioned at two sides of the plurality of sub-pixel units in the first direction, and in the (k +1)/2 th grid line group, the kth grid line and the (k +1) th grid line are connected through the first vertical grid line and the second vertical grid line,

wherein k can be an odd number greater than or equal to 1, and n is a positive integer greater than k.

22. The array substrate of claim 21, wherein the first vertical gate line and the second vertical gate line are disposed on the same layer as the data line.

23. The array substrate of claim 22, wherein the first vertical gate line is connected to the kth gate line through a first via connection structure, the first vertical gate line is connected to the (k +1) th gate line through a second via connection structure,

the second vertical grid line is connected with the kth grid line through a third via hole connecting structure, and the second vertical grid line is connected with the (k +1) th grid line through a fourth via hole connecting structure.

24. The array substrate of claim 21, further comprising at least one intermediate vertical gate line between two adjacent sub-pixel columns,

in the (k +1)/2 gate line group, the k gate line and the k +1 gate line are connected through the middle vertical gate line.

25. The array substrate of claim 24, wherein the middle vertical gate line is disposed on the same layer as the gate line.

26. The array substrate of claim 24, further comprising:

a first common electrode line extending in the first direction; and

a second common electrode line extending in the second direction,

wherein each of the sub-pixel units includes a first region and a second region sequentially arranged along the second direction, the pixel electrode is located in the first region, the driving transistor is located in the second region, the first common electrode line is located between two adjacent sub-pixel units in the second direction and between the first region and the second region of the same sub-pixel unit,

the second common electrode line is located between two adjacent sub-pixel columns.

27. The array substrate of claim 26, wherein the first common electrode line is disposed on the same layer as the gate line, the first common electrode line comprises at least one first notch and first sub-common electrode lines disposed at two sides of the first notch,

the middle vertical grid line penetrates through the first notch and is respectively arranged at intervals and in an insulating mode with the first sub-common electrode line.

28. The array substrate of claim 26, wherein the second common electrode lines comprise gate layer common electrode lines and data line layer common electrode lines, the gate layer common electrode lines are disposed on the same layer as the gate lines, the data line layer common electrode lines are disposed on the same layer as the data lines, and the gate layer common electrode lines are connected to the data line layer common electrode lines through a fifth via connection structure.

29. The array substrate of claim 27, wherein two first common electrode lines are disposed between a kth gate line and a k +1 th gate line in the (k +1)/2 th gate line group and respectively include the first notch, and the middle vertical gate line passes through the two first notches of the two first common electrode lines to connect the kth gate line and the k +1 th gate line.

30. The array substrate of claim 26,

the width of the part of the second common electrode line in the first area is larger than that of the part of the second common electrode line in the second area.

31. The array substrate of claim 26, wherein the second common electrode line is located between the l-th sub-pixel column and the l + 1-th sub-pixel column, a distance between the second common electrode line and the signal line corresponding to the l-th sub-pixel column is equal to a distance between the second common electrode line and the data line corresponding to the l + 1-th sub-pixel column, or a distance between the second common electrode line and the data line corresponding to the l-th sub-pixel column is equal to a distance between the second common electrode line and the signal line corresponding to the l + 1-th sub-pixel column, and l is a positive integer greater than or equal to 1.

32. The array substrate of any one of claims 1-7,

each sub-pixel unit comprises a first area and a second area which are sequentially arranged along the second direction, the pixel electrode is positioned in the first area, the driving transistor is positioned in the second area,

a distance in the first direction between a portion of the data line in the first region and a portion of the signal line in the first region is smaller than a distance in the first direction between a portion of the data line in the second region and a portion of the signal line in the second region,

the data line includes a first inclined connection portion connecting a portion of the data line in the first region and a portion of the data line in the second region, and the signal line includes a second inclined connection portion connecting a portion of the signal line in the first region and a portion of the signal line in the second region.

33. The array substrate of claim 26, further comprising:

a plurality of gate lead-out lines, each of the gate lead-out lines being located between two adjacent sub-pixel columns,

wherein each grid lead-out line includes:

a first gate lead-out line disposed on the same layer as the data line and configured to connect a gate signal;

a second gate lead-out line disposed at the same layer as the gate lines and configured to be connected to the corresponding gate line,

and the first grid outgoing line and the second grid outgoing line are connected through a sixth through hole structure.

34. The array substrate of claim 33, wherein the gate lead-out line is configured to be electrically connected to an (m +1)/2 gate line group, the second gate lead-out line is directly connected to the m-th gate line, m is an odd number greater than or equal to 1,

the m-1 th grid line comprises a second notch, three first common electrode lines are arranged between the m-2 th grid line and respectively comprise a first notch, the second grid outgoing line passes through the second notch of the m-1 th grid line and the three first notches of the three first common electrode lines and extends to the position of the sixth via hole connecting structure,

the sixth via hole connection structure is located between the m-2 th grid line and the first common electrode line, and the first grid outgoing line is connected with the second grid outgoing line through the sixth via hole connection structure.

35. The array substrate of claim 26, further comprising:

and the shielding electrode is positioned on the substrate and arranged on the same layer with the grid line.

36. The array substrate of claim 35, wherein an orthogonal projection of the shielding electrode on the substrate is located between an orthogonal projection of the second common electrode line on the substrate and an orthogonal projection of the data line on the substrate, and between an orthogonal projection of the second common electrode line on the substrate and an orthogonal projection of the signal line on the substrate.

37. The array substrate of claim 36, wherein the orthographic projection of the shielding electrode on the substrate is further located between the orthographic projection of the data line on the substrate and the orthographic projection of the signal line on the substrate.

38. A display device comprising the array substrate according to any one of claims 1 to 37.