CN216313058U

CN216313058U - Multi-path digital adjustable attenuator device

Info

Publication number: CN216313058U
Application number: CN202122752234.XU
Authority: CN
Inventors: 丁哲壮; 唐海波; 马英兴
Original assignee: Taicang T&W Electronics Co Ltd
Current assignee: Taicang T&W Electronics Co Ltd
Priority date: 2021-11-11
Filing date: 2021-11-11
Publication date: 2022-04-15
Anticipated expiration: 2031-11-11

Abstract

The utility model discloses a multipath digital adjustable attenuator device, which comprises a multipath digital attenuation circuit and an FPGA (field programmable gate array) for controlling the attenuation value of the digital attenuation circuit, wherein the output end of the FPGA is respectively connected with the input end of the multipath digital attenuation circuit and provides a digital control signal of the attenuation value for the digital attenuation circuit. The utility model utilizes the FPGA and the digital attenuation chip to form the multi-path digital adjustable attenuator, is convenient for debugging and use, can control the actual attenuation value by using a command, does not need to replace a fixed attenuator and does not need to adjust a circuit. Compared with the debugging of a multi-path fixed attenuator, the loss of the device is greatly reduced, the use cost is further reduced, and the test efficiency is greatly improved.

Description

Multi-path digital adjustable attenuator device

Technical Field

The utility model belongs to the technical field of digital communication testing, and particularly relates to a multi-path digital adjustable attenuator device.

Background

Attenuators are common devices for signal attenuation in the field of communications. Currently, the conventional attenuator is mainly a fixed attenuator. The attenuation gain of the attenuator is fixed, such as 3dB, 20dB, 30dB and the like.

In mobile communication tests, particularly 5G mobile communication tests, in order to accurately detect the accuracy of signal output power adjustment of mobile communication equipment, the attenuator needs to be adjusted every 1dB, that is, attenuation values of 15dB, 14dB, 13dB, 12dB and the like may be required.

In transmission, the fixed value attenuators of 1dB, 2dB, 3dB, 5dB and the like are required to be gradually accumulated so as to achieve the purpose of presetting attenuation. And this adjustment requires a lot of time for the connection work. Moreover, only one channel can be adjusted in each adjustment. For testing multiple channels of multiple devices, multiple channels need to be adjusted simultaneously, which consumes a lot of time.

SUMMERY OF THE UTILITY MODEL

The technical problem to be solved by the utility model is to provide a multi-path digital adjustable attenuator device. The digital adjustable attenuation of any natural value in the range of 1-90dB can be realized, the multi-channel can be provided for testing at the same time, the equipment is assembled and connected at one time, the adjustment of the subsequent attenuation value is not needed to adjust hardware equipment, only the regulation and control value needs to be changed, the use is convenient, the testing efficiency is high, and the cost is low.

In order to solve the problems, the technical scheme adopted by the utility model is as follows:

the output end of the FPGA is respectively connected with the input end of the multi-path digital attenuation circuit, and provides a digital control signal of the attenuation value for the digital attenuation circuit.

Furthermore, each digital attenuation circuit comprises a plurality of digital attenuation chips, a coupling capacitor and a radio frequency base, wherein the input radio frequency base is connected with the radio frequency input end of the first digital attenuation chip, the radio frequency output end of the first digital attenuation chip is connected with the radio frequency input end of the second digital attenuation chip through the capacitor, and so on, and the radio frequency output end of the Nth digital attenuation chip is connected with the output radio frequency base.

Preferably, each digital attenuation circuit comprises three digital attenuation chips, and the maximum attenuation value of each digital attenuation chip is more than 30 dB.

Furthermore, at least one of the three digital attenuation chips has an attenuation step gain of 0.25 dB.

Preferably, the three digital attenuation chips are respectively of two HMCs 1122L and one HMC 1119.

Furthermore, the FPGA is an FPGA supporting Ethernet communication, and the FPGA is connected with a three-wire serial interface of the digital attenuation chip.

Preferably, the FPGA is of the EP3C5E1 family with a more available interface.

Furthermore, the system also comprises a control device, and the FPGA is connected with the control device through a network cable.

Furthermore, the system also comprises a switch, and the control equipment is connected with the FPGA through the switch.

Preferably, the control device is a computer or a human-computer terminal with a network interface.

Adopt the produced beneficial effect of above-mentioned technical scheme to lie in:

the utility model utilizes the FPGA and the digital attenuation chip to form the multi-path digital adjustable attenuator, is convenient for debugging and use, can control the actual attenuation value by using a command, does not need to replace a fixed attenuator and does not need to adjust a circuit. Compared with the debugging of a multi-path fixed attenuator, the loss of the device is greatly reduced, the use cost is further reduced, and the test efficiency is greatly improved.

Drawings

FIG. 1 is a functional block diagram of the present invention;

FIG. 2 is a block diagram of a digital attenuator circuit according to the present invention;

FIG. 3 is a schematic diagram of a digital attenuator circuit according to the present invention;

fig. 4 is a flow chart of the attenuation control method of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the specific embodiments of the present invention and the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the utility model, and not restrictive of the full scope of the utility model. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The utility model relates to a multi-path digital adjustable attenuator device, which constructs a multi-path digital adjustable attenuator by utilizing the characteristic that an FPGA has a plurality of output pins, and can construct 16 or 32 paths of attenuation test channels by adopting an EP3C5E1 series FPGA. The utility model adopts two digital attenuation chips of HMC1119 and HMC1122L, the HMC1119 is a broadband, high-precision, 7-bit digital attenuator, the working frequency range is 0.1GHz to 6.0GHz, and an attenuation control range of 31.5dB is provided by 0.25dB step size. The HMC1122 is a 6-bit digital attenuator with an operating frequency range of 0.1GHz to 6GHz providing 31.5dB attenuation control range in 0.5dB steps. A plurality of digital attenuation chips are cascaded (connected in series) to form an attenuation circuit with any attenuation value, and the utility model adopts 1 HMC1119 and 2 HMC1122L to be cascaded to form a 90dB digital attenuation circuit. By using two digital attenuation chips with different attenuation step values, the attenuation value with the step value of 0.25db can be obtained, so that the control precision of the attenuation is higher. More application occasions are met, and the cost is saved.

As shown in fig. 1, the present invention includes a multi-path digital attenuation circuit and an FPGA for controlling attenuation values of the digital attenuation circuit, wherein output terminals of the FPGA are respectively connected to input terminals of the multi-path digital attenuation circuit, and provide digital control signals of the attenuation values for the digital attenuation circuit.

As a preferred embodiment of the present invention, the FPGA according to the present invention is an FPGA supporting ethernet communication. The utility model also comprises a control device, wherein the FPGA is connected with the control device through a network cable. Of course, if one control device is realized, the digital adjustable attenuation circuit formed by a plurality of FPGAs is controlled, and a switch is also needed, the control device is connected with the FPGAs through the switch, so that more controls can be realized. In a further preferred embodiment, the control device is a computer or a human-machine terminal with a network interface.

As shown in fig. 2, each digital attenuation circuit of the present invention includes a plurality of digital attenuation chips, a coupling capacitor and a radio frequency base, wherein the input radio frequency base is connected to the radio frequency input terminal of the first digital attenuation chip, the radio frequency output terminal of the first digital attenuation chip is connected to the radio frequency input terminal of the second digital attenuation chip through the capacitor, and so on, the radio frequency output terminal of the nth digital attenuation chip is connected to the output radio frequency base.

As shown in fig. 3, as a preferred embodiment of the present invention, each digital attenuation circuit includes 1 digital attenuation chip HMC1119,2 digital attenuation chips HMC1122L, and 3 digital attenuation chips are sequentially connected in series through coupling capacitors to form a 90dB digital attenuation circuit, since the HMC1119 attenuation step is 0.25dB, the adjustment accuracy of each digital attenuation circuit can reach 0.25dB, the HMC1119 is connected to the FPGA through a 3-wire serial interface (18 pin SERIN, 17 pin CLK, 16 pin LE), instead of using a GPIO (data 0-6) port, the HMC1122L is connected to the FPGA through a 3-wire serial interface (3 pin SERIN, 2 pin CLK, 4 pin LE), instead of using a GPIO (0-data 5) port, so that a large number of pins of the FPGA can be saved, and multiple groups of attenuation circuit channels can be built. And the control is simpler by using the 3-wire serial interface, and the circuit structure is simpler.

In order to enable an FPGA to build more attenuation circuit paths, the FPGA selects the EP3C5E1 family with more available interfaces.

For the utility model, the attenuation control method based on the digital adjustable attenuator device comprises the following steps:

s1, the FPGA acquires attenuation control information;

s2, the FPGA sets an attenuation channel n according to the attenuation control information;

and S3, the FPGA sets an attenuation value m according to the attenuation control information, converts the attenuation value m into a digital control signal and outputs the digital control signal to the digital attenuation circuit to complete attenuation control.

The control flow chart of the present invention is shown in fig. 4, and as a preferred embodiment of the present invention: the FPGA in the step S1 supports ethernet communication, and monitors attenuation control information issued by the control device through the network; the digital attenuation circuit in step S3 is composed of two HMCs 1122L and one HMC1119 digital attenuation chip, and step S3 specifically includes the following steps:

s31, the FPGA compares the attenuation value m with a preset threshold range according to the attenuation control information;

s32, when the attenuation value m is less than or equal to 31dB, setting 0dB attenuation values for the two HMCs 1122L, and setting m attenuation values for the HMC 1119;

s33, when the attenuation value m is larger than 31dB and smaller than or equal to 60dB, setting 0dB attenuation value for one HMC1122L, setting 30dB attenuation value for one HMC1122L and setting m-30 attenuation value for HMC 1119;

s34, when the attenuation value m is more than 60dB and less than or equal to 90dB, the two HMCs 1122L are both set with 30dB attenuation values, and the HMC1119 is set with m-60 attenuation values.

The steps are the flow of setting one path of digital attenuation circuit, and the setting method and steps of other paths are the same as the path. In practice, the same hardware circuit is used for the multiple digital attenuation circuits, and different addresses are defined for each chip in each digital attenuation circuit in program control, so that the program can distribute attenuation values to different digital attenuation chips.

Claims

1. A multi-path digital adjustable attenuator device is characterized in that: the digital attenuation circuit comprises a multi-path digital attenuation circuit and an FPGA for controlling the attenuation value of the digital attenuation circuit, wherein the output end of the FPGA is respectively connected with the input end of the multi-path digital attenuation circuit and provides a digital control signal of the attenuation value for the digital attenuation circuit.

2. The multi-path digitally adjustable attenuator device of claim 1, wherein: each digital attenuation circuit comprises a plurality of digital attenuation chips, a coupling capacitor and a radio frequency seat, wherein the input radio frequency seat is connected with the radio frequency input end of the first digital attenuation chip, the radio frequency output end of the first digital attenuation chip is connected with the radio frequency input end of the second digital attenuation chip through the capacitor, and so on, and the radio frequency output end of the Nth digital attenuation chip is connected with the output radio frequency seat.

3. A multi-path digitally adjustable attenuator device according to claim 2, wherein: each digital attenuation circuit comprises three digital attenuation chips, and the maximum attenuation value of each digital attenuation chip is more than 30 dB.

4. A multi-path digitally adjustable attenuator device according to claim 3, wherein: at least one of the three digital attenuation chips has an attenuation step gain of 0.25 dB.

5. The multi-path digitally adjustable attenuator device of claim 4, wherein: the three digital attenuation chips are respectively of two HMCs 1122L and one HMC 1119.

6. A multi-path digitally adjustable attenuator device according to any one of claims 2 to 5, wherein: the FPGA is an FPGA supporting Ethernet communication and is connected with a three-wire serial interface of the digital attenuation chip.

7. The multi-path digitally adjustable attenuator device of claim 6, wherein: the FPGA is of the EP3C5E1 family with more available interfaces.

8. The multi-path digitally adjustable attenuator device of claim 1, wherein: the FPGA is connected with the control equipment through a network cable.

9. The multi-path digitally adjustable attenuator device of claim 8, wherein: still include the switch, controlgear passes through the switch and is connected with FPGA.

10. The multi-path digitally adjustable attenuator device of claim 8, wherein: the control equipment is a computer or a man-machine terminal with a network interface.