CN216084877U - Three-dimensional packaging structure and semiconductor device - Google Patents

Abstract

The utility model discloses a three-dimensional packaging structure and a semiconductor device, wherein the three-dimensional packaging structure comprises: the method comprises the following steps: the front surface of the first chip is provided with a first bonding pad and a chip connection area formed beside the first bonding pad; a second chip having a back surface disposed on the chip attach region and a front surface provided with a second pad; the rewiring structure is arranged in the front direction of the second chip and is electrically connected with the second bonding pad; and the electric connecting piece is arranged between the rewiring structure and the first bonding pad and is electrically connected with the rewiring structure and the first bonding pad. The embodiment of the utility model adopts the electric connecting piece to connect the bonding pad of the stacked chip and the rewiring structure, the electric connecting piece can be directly formed on the bonding pad by adopting a ball planting process, compared with the technical scheme of adopting a metal bump formed by electroplating in the prior art, the process is simpler, and the cost can be better saved by avoiding the use of a large amount of photoresist in the electroplating process.

Description

Three-dimensional packaging structure and semiconductor device

Technical Field

The utility model relates to the technical field of chip packaging, in particular to a three-dimensional packaging structure and a semiconductor device.

Background

Three-dimensional (3D) packaging is widely used in the IC manufacturing industry as an advanced packaging technology, and breaks through the concept of conventional planar packaging, so that a plurality of chips can be stacked in a single package, thereby doubling the storage capacity and increasing the assembly efficiency to more than 200%. Meanwhile, the chips are directly interconnected by the three-dimensional packaging, the length of an interconnecting wire is obviously shortened, the signal transmission is quicker, the interference is smaller, and a single packaging body realizes more functions, so that a new idea of packaging the system chips is formed.

When a plurality of stacked chips are connected, wires need to be re-wired above the chips, and in order to realize the electrical connection between a re-wiring structure and a bonding pad of the chip, a metal copper column needs to be manufactured on the bonding pad of the chip; in the prior art, the metal copper column is generally formed by electroplating through an electroplating process.

Since the stacking of the chips results in a relatively large distance from the rewiring structure with respect to the chips stacked on the lower side, typically a distance exceeding 80 μm, this requires a relatively large height of the copper metal pillar formed on the pad. In the prior art, if a metal copper column with a higher size is to be formed, a relatively thicker photoresist layer needs to be covered in the electroplating process, which not only increases the cost and prolongs the electroplating time, but also causes the process complexity, and meanwhile, rework is not good if defects exist after the metal copper column is electroplated.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a three-dimensional packaging structure, which can solve the defects in the prior art, simplify the process, reduce the use of photoresist and reduce the production cost.

The utility model provides a three-dimensional packaging structure, which comprises:

the front surface of the first chip is provided with a first bonding pad and a chip connection area formed beside the first bonding pad;

a second chip having a back surface disposed on the chip attach region and a front surface provided with a second pad;

the rewiring structure is arranged in the front direction of the second chip and is electrically connected with the second bonding pad;

and the electric connecting piece is arranged between the rewiring structure and the first bonding pad and is electrically connected with the rewiring structure and the first bonding pad.

Further, the electrical connector comprises a core and a solder body arranged outside the core, the electrical connector is welded on the pad through the solder body, and the rewiring structure is electrically connected with the core.

Further, the solder body covers the outer side of the core, and the top of the core is exposed towards the direction of the rewiring structure so as to be butted with the rewiring structure.

Furthermore, the top of the inner core and the top of the solder body are planar and located on the same plane, the solder body has an annular structure in the plane, and the shape of the inner core in the plane is matched with the inner ring of the annular structure.

Further, a passivation layer is arranged between the top surface of the solder body and the rewiring structure, and the solder body is connected with the passivation layer through an IMC layer formed on the top of the solder body.

Further, the minimum distance between any point on the top surface of the solder body and the inner core is not more than 10 μm.

Further, in any cross section of the electrical connector parallel to the top surface of the solder body and through the core, the minimum distance of the solder body from the core at any point on the cross section is not more than 10 μm.

Further, the inner core is a metal ball with a partially cut top.

Further, the melting point of the inner core is higher than that of the welding flux body; the inner core is made of one of gold, copper, aluminum and silver, and the solder body is made of tin or tin alloy.

Further, the solder body is a solder layer disposed between the core and the pad, and the solder layer has a height not less than 1/3 of the height of the core and not more than 1/2 of the height of the core.

Further, the distance between the first pad and the rewiring structure is greater than 80 μm.

Furthermore, the rewiring structure is electrically connected with the second bonding pad through an electric connection structure, and the electric connection structure is a copper column or the electric connection piece.

Further, the three-dimensional package structure further includes:

the encapsulation layer covers the front surface of the chip, and encapsulation gaps are formed at positions of the encapsulation layer corresponding to the electric connecting pieces and the electric connecting structures;

a passivation layer covering the encapsulation layer, wherein passivation layer openings are formed at positions of the passivation layer corresponding to the electric connecting pieces and the electric connecting structure;

the rewiring structure is arranged on the upper side of the electric connecting piece, the upper side of the electric connecting structure and part of the upper side of the passivation layer, and the rewiring structure penetrates through the packaging gap and the passivation layer opening to be connected with the electric connecting piece and the electric connecting structure.

The utility model also discloses a semiconductor device, which comprises the three-dimensional packaging structure and a circuit substrate with a substrate bonding pad, wherein a plurality of metal bumps are arranged on one side of the rewiring structure, which is far away from the chip, and the metal bumps are welded on the substrate bonding pad.

Compared with the prior art, the utility model adopts the pre-manufactured electric connecting piece to connect the bonding pad of the stacked chip with the rewiring structure, the electric connecting piece can be directly welded on the bonding pad by adopting a ball planting process, compared with the scheme of adopting the metal bump to be electroplated and formed in the prior art, the process of the embodiment is simpler, the cost can be better saved by avoiding using a large amount of photoresist materials in the electroplating process, meanwhile, the electric connecting piece is pre-manufactured, before the electric connecting piece is welded on the bonding pad, the appearance inspection can be carried out on the electric connecting piece, and the bad electric connecting piece can be found in time to replace the rework in time.

Drawings

Fig. 1-6 are schematic packaging flow diagrams of a three-dimensional packaging structure according to a first embodiment of the disclosure;

FIG. 7 is a structural diagram of a three-dimensional package structure according to a second embodiment of the disclosure;

FIG. 8 is a schematic structural view showing the core exposed to the outside after the encapsulant layer and the solder body are abraded in the first embodiment of the present disclosure;

FIG. 9 is a schematic structural diagram of a passivation layer covering an encapsulation layer according to a first embodiment of the disclosure;

description of reference numerals: 1-chip, 11-first chip, 111-first pad, 112-die attach region, 12-second chip, 121-second pad, 2-rewiring structure, 3-electrical connection, 31-core, 32-body of solder, 4-electrical connection, 5-encapsulation, 6-passivation, 60-passivation opening, 7-metal bump.

Detailed Description

The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the utility model.

The embodiment of the utility model comprises the following steps: as shown in fig. 6 and 7, a three-dimensional package structure is disclosed, which specifically includes: the chip comprises at least two chips 1, a rewiring structure 2 and an electric connecting piece 3 which are sequentially stacked, wherein bonding pads of the chips 1 face to the same side; the rewiring structure 2 is arranged in the front direction of the uppermost chip 1 and is electrically connected with the two chips stacked up and down; the electrical connection member 3 electrically connects the rewiring structure 2 and a pad of the chip on the lower side, wherein the electrical connection member 3 is pre-fabricated, and the pre-fabricated electrical connection member 3 is soldered to the pad. It should be noted that the pad of the chip on the lower side is the chip on the lower side relative to the two stacked chips, and when stacking a plurality of chips, the chip on the lower side is the lowest chip relative to the chip on the uppermost side; of course, in another embodiment, the chip on the lower side may be a chip with three chips stacked and then located in the middle.

Adopt electric connector 3 to connect the pad and the rewiring structure 2 of the chip that piles up in this embodiment, electric connector 3 makes in advance, then can adopt the ball technology of planting direct welding shaping on the pad, compares in the prior art that the scheme technology that adopts electroplating shaping metal lug is simpler to avoid the cost-effective that can be better of using in a large number of photoresist in the electroplating process.

As shown above, the three-dimensional package structure disclosed in the present application may stack two chips or more chips, and in the present embodiment, the stacking of two chips, i.e., the first chip 11 and the second chip 12, is taken as an example for description.

The three-dimensional packaging structure comprises:

a first chip 11 having a front surface provided with a first pad 111 and a die attach region 112 formed beside the first pad 111;

a second chip 12 having a back surface disposed on the die attach region 112 and a front surface provided with a second pad 121; the size of the first chip 11 is larger than that of the second chip 12, so that the second chip 12 is stacked on the first chip 11; the back of the second chip 12 can be directly attached to the first chip 11;

a rewiring structure 2 disposed in a front direction of the second chip 12 and electrically connected to the second pad 121;

and an electrical connection member 3 disposed between the rewiring structure 2 and the first pad 111 and electrically connecting the rewiring structure 3 and the first pad 111.

After the chips are stacked, the first chip 11 is a chip relatively positioned at the lower side, the second chip 12 is a chip relatively positioned at the upper side, and the rewiring structure 2 is positioned above the front surface of the second chip 12, so that the rewiring structure 2 is relatively far away from the first bonding pad 111; in the embodiment, the first bonding pad 111 and the rewiring structure 2 are connected through the electric connector 3, so that the complexity of the process can be reduced, the use of a large amount of photoresist is avoided, and the cost is reduced.

In this embodiment, the redistribution structure 2 and the second pad 121 are electrically connected through an electrical connection structure 4, wherein the electrical connection structure 4 may be a copper pillar, and is formed by electroplating through an electroplating process; of course, the electrical connection structure 4 may also be the electrical connector, which is manufactured in advance and then soldered on the pad by the ball-mounting process.

It is understood that the three-dimensional encapsulation structure further comprises an encapsulation layer 5 and a passivation layer 6;

wherein, the encapsulation layer 5 covers the front side of the chip; the encapsulating layer 5 covers all the stacked chips at the same time for packaging and fixing the stacked chips; an encapsulating gap is formed on the encapsulating layer 5 at a position corresponding to the electric connecting piece 3 and the electric connecting structure 4, and the electric connecting piece 3 and the electric connecting structure 4 are exposed from the encapsulating gap to the outer side of the encapsulating layer 5;

the encapsulation gap is in fact the escape of the encapsulation layer 5 from the electrical connection structure 4 and the electrical connection 3, thus being embodied at the top of the encapsulation layer 5;

generally, the upper surface of the encapsulating layer 5 after the initial molding is not lower than the front surface of the chip in the vertical direction to completely embed the chip therein. However, in order to conveniently realize the connection between the rewiring structure and the electrical connection structure 4 and the electrical connection member 3, after the encapsulation layer 5 is formed, a part of the encapsulation layer 5 needs to be etched to form the encapsulation gap; the encapsulating layer 5 is made of epoxy resin, phenolic resin, organic silicon resin and unsaturated polyester resin, which are commonly used at present, and fillers such as silicon oxide and aluminum oxide are added into the encapsulating layer to improve the strength, electrical property, viscosity and other properties of the encapsulating layer 5 and improve the thermo-mechanical reliability of the packaging structure. The encapsulating layer 5 can play the roles of water resistance, moisture resistance, shock resistance, dust resistance, heat dissipation, insulation and the like after being cured.

A passivation layer 6 is covered on the encapsulating layer 5, a passivation layer opening 60 is formed on the passivation layer 6 at a position opposite to the electric connecting member 3 and the electric connecting structure 4, and the electric connecting member 3 and the electric connecting structure 4 are exposed from the passivation layer opening 60 to the outside of the passivation layer 6; the passivation layer opening 60 is located opposite the encapsulation gap; the passivation layer 6 is made of silicon oxide, silicon nitride or resin dielectric material;

the rewiring structure 2 is arranged on the upper side of the electrical connection element 3, on the upper side of the electrical connection structure 4 and on a part of the passivation layer 6, and the rewiring structure 2 is connected to the electrical connection element and the electrical connection structure through the encapsulation recess and the passivation layer opening 60.

The material of the rewiring structure 2 includes, but is not limited to, copper, the rewiring structure 2 has an opening 60 passing through the passivation layer and an opening for encapsulating to connect with the electrical connector 3 or the electrical connection structure 4, and the rewiring structure 2 may be a single layer or multiple layers, depending on the actual requirement.

In the embodiment, the rewiring structure 2 is formed by an electroplating process, and in order to better realize the arrangement of the rewiring structure 2, seed layers are formed between the rewiring structure 2 and the electric connecting members 3, between the rewiring structure 2 and the electric connecting structures 4 and between the rewiring structure 2 and the passivation layer 6, and the rewiring structure 2 is formed on the seed layers in a growth mode.

In the present embodiment, the electrical connector 3 includes a core 31 and a solder body 32 disposed outside the core 31, the electrical connector 3 is soldered on the first pad 111 by the solder body 32, and the rewiring structure 2 is electrically connected to the core 31.

The melting point of the inner core 31 is higher than that of the solder body 32; the inner core 31 is made of one of gold, copper, aluminum, silver and the like, and the solder body 32 is made of tin or tin alloy.

In order to avoid the influence of the higher temperature on the stability of the electrical connector 3 when the rewiring structure 2 is formed, the core 31 is made of metal with a relatively high melting point, and in order to facilitate the connection between the core 31 and the pad, the electrical connector 3 is further provided with the solder body 32, and the solder body 32 is made of material with a relatively low melting point so as to facilitate the connection between the solder body 32 and the pad.

In a particular embodiment, the solder body 32 of the electrical connector 3 is molded directly on the outside of the core 31. The solder body 32 covers the outside of the core 31, and the top of the core 31 is exposed towards the rewiring structure 2 to be butted with the rewiring structure 2, that is, the solder body 32 only covers the side wall and the bottom wall of the core 31, and the top of the core 31 is not covered by the solder body 32.

Since electrical connector 3 is pre-formed during actual use, solder body 32 is often completely wrapped around inner core 31 to facilitate fabrication of electrical connector 3, and then portions of solder body 32 above electrical connector 3 are removed to expose outer core 31 during use. Specifically, after the electrical connector 3 is soldered to the pad, part of the solder body 32 is removed by physical abrasion to expose the core 31, and in the process, part of the core 31 is removed to increase the size of the core 31 exposed to the outside, so that the electrical connection with the rewiring structure 2 is more conveniently realized, and the connection stability is improved.

Specifically, after the electrical connector 3 is soldered to the pad and the encapsulating layer 5 is formed on the chip, a portion of the encapsulating layer 5 and a portion of the electrical connector 3 are abraded to expose the core 31 to the outside; as shown in fig. 8, after the abrasion, the top of the core 31 and the top of the solder body 32 are both planar and located in the same plane, and the solder body 32 has an annular structure in the plane, and the shape of the core in the plane is matched with the inner ring of the annular structure.

As shown in fig. 9, in order to secure the stability of the rewiring structure 2 and the electrical connection member 3, the rewiring structure 2 is provided to be connected only to the core 31. Therefore, forming the passivation layer 6 over the encapsulating layer 5 before molding the rewiring structure 2 needs to cover the upper side of the solder body 32 to block the rewiring structure 2 from contacting the solder body 32. The passivation layer opening 60 formed in the passivation layer 6 during this process needs to be located opposite the core 31 and the passivation layer opening 60 is no larger in size than the outwardly exposed size of the core 31. In the process of pre-forming the electric connector 3, the solder body 32 and the inner core 31 are two different metals, the contact part of the solder body 32 and the inner core 31 reacts with the inner core 31 to form an IMC layer, the IMC layer is formed because the tin atoms and the metal atoms of the inner core 31 are combined, penetrated, migrated and diffused during the welding forming, and a thin eutectic substance, namely the IMC layer, appears immediately after cooling and solidification. The IMC layer ages to a degree that the tin atoms and metal atoms infiltrate each other, and thus, the IMC layer is primarily located at the solder body 32 near the core 31.

After the passivation layer 6 has been applied to the solder body 32, delamination between the passivation layer 6 and the solder body 32 is easily formed when subjected to high temperatures, the presence of which delamination may affect the stability of the connection of the rewiring structure 2 to the electrical connection 3.

In order to avoid the delamination problem, the IMC layer is required to be completely formed when the solder body 32 is connected to the passivation layer through the IMC layer formed on top, that is, the portion where the top of the solder body 32 is connected to the passivation layer 6 is in the process of the interaction between the core 31 and the passivation layer, which requires that the outermost portion of the top of the solder body 32 also reacts to form the IMC layer, that is, when the top surface of the solder body 32 has a ring structure, the IMC layer is already formed at any point of the outer ring of the ring structure, thereby ensuring that the passivation layer 6 directly covers the completely formed IMC layer on top of the solder body 32.

If no IMC layer is formed on the portion of the ring structure of the top surface of the solder body 32 close to the outer ring, the portion is also made of the material of the solder body itself, i.e., the material of tin and tin alloy, so that the reflow shrinkage of the edge position of the top surface of the solder body 32 is inevitably caused after the high-temperature melting in the later period, and the bonding with the passivation layer 6 is unstable, thereby forming a delamination between the passivation layer 6 and the top surface of the solder body 32. In this embodiment, the IMC layer is formed on the top surface of the solder body 32, and the above-mentioned delamination problem can be avoided by connecting the IMC layer to the passivation layer 6.

In order to ensure that an IMC layer is formed on top of the solder body 32, the minimum distance between any point on the solder body 32 and the inner core 31 in the plane of the top of the solder body 32 is no more than 10 μm. The arrangement described above, in which the top surface of the solder body 32 has a ring-shaped configuration, requires that the minimum distance from any point in the outer ring of the solder body 32 of the ring-shaped configuration to the inner ring of the ring-shaped configuration should not exceed 10 μm.

The above arrangement ensures that the top of the solder body 32 reacts to fully form the IMC layer. If there is a location on the solder body 32 in the plane of the top of the solder body 32 where the minimum distance from the core 31 exceeds 10 μm, this location can easily lead to an incomplete reflection of the solder body 32 from the core 31 during the formation of the electrical connector 3, i.e. to the formation of pure tin at the edge of the solder body 32, the presence of which can easily cause shrinkage during high temperature reflow and delamination between the solder body and the passivation layer 6.

Furthermore, in any cross-section of the electrical connector 3 parallel to the plane (i.e., the top surface of the solder body 32, i.e., the top surface of the core 31) and passing through the core 31, the minimum distance of the solder body from the core at any point on the cross-section is not more than 10 μm. The arrangement of the structure can enable the positions corresponding to the positions of the cores 31 on the whole welding body 32 to be completely reacted and enable the welding body to integrally form the IMC layer, so that the problem of layering between the welding body 32 and the passivation layer 6 can be avoided no matter how much the cores 31 are exposed outwards no matter how many positions the electric connecting piece 3 is put in use, the stability of the contact part between the welding body 32 and the passivation layer 6 is ensured, and the applicability of the electric connecting piece 3 is improved.

Preferably, the whole electric connecting piece 3 is integrally formed into a sphere with a two-layer structure after being manufactured in advance, so that the structure can be used for more conveniently adopting a ball planting process to directly weld the electric connecting piece 3 on the bonding pad, and the connecting use of the electric connecting piece 3 is conveniently realized.

The core 31 is a metal ball of a spherical structure in the electrical connector 3 after the fabrication in advance, and the core 31 is a metal ball of which the top is partially cut after the electrical connector 3 connects the pad and the re-wiring structure 2, and the top of the spherical core 31 is cut in the process of removing a part of the solder body 32. Of course, in another embodiment, the inner core 31 may also be a cylinder in the pre-manufactured electrical connector 3.

In the above embodiment, the solder body 32 covers the core 31, and in another embodiment, the solder body 32 is disposed on the lower side of the core 31, and the solder body 32 can be directly fixed on the core 31 to form the complete electrical connector 3, or the solder body 32 and the core 31 can be separately disposed. In the present embodiment, the solder body 32 and the core 31 are separately illustrated.

Specifically, the solder body 32 is a solder layer disposed between the core 31 and the pad, the solder layer is disposed on the pad and then the solder body 32 is soldered on the solder layer, and the height of the solder layer is set to be not lower than 1/3 and not higher than 1/2 of the height of the core in order to ensure the stability of the whole structure.

In the present embodiment, the distance between the first pad 111 and the redistribution structure 2 is greater than 80 μm, and the distance between the first pad 111 and the redistribution structure 2 is not greater than 750 μm. In the process of forming the metal bump by using the electroplating process in the prior art, if the distance between the pad 111 and the rewiring structure 2 exceeds 80 μm, the electroplating time is increased, and the height of the formed photoresist layer is large, which causes the waste of the photoresist. By adopting the scheme of the embodiment, the waste of the photoresist caused by the electroplating process can be effectively avoided.

The utility model also discloses a semiconductor device, which comprises the three-dimensional packaging structure and a circuit substrate with a substrate bonding pad, wherein a plurality of metal bumps 7 are arranged on one side of the rewiring structure, which is far away from the chip, and the metal bumps 7 are welded on the substrate bonding pad.

The utility model also discloses a packaging method of the three-dimensional packaging structure, which comprises the following steps:

as shown in fig. 1, a first chip 11 and a prefabricated electrical connector are provided, and the electrical connector is electrically connected to the first bonding pad 111 on the front surface of the first chip 11;

providing a second chip 12, and forming an electrical connection structure 4 on a second bonding pad 121 of the second chip 12;

as shown in fig. 2, the second chip 12 is fixed to the front surface of the first chip 12;

as shown in fig. 3, an encapsulating layer 5 is formed on the front surface of the first chip 11 and the front surface of the second chip 12;

as shown in fig. 4, removing a portion of the encapsulating layer 5 to simultaneously expose the electrical connection structure 4 and the electrical connection member 3 to the outside;

as shown in fig. 5, the redistribution structure 2 is formed over the encapsulation layer 6, and the redistribution structure 2 and the electrical connection structure 4 are electrically connected to the electrical connector 3.

In a specific wafer factory packaging process, in order to conveniently realize the molding of the electrical connectors 3, the first chips 11 are collectively operated on a wafer before being cut by a plurality of first chips 11 when the electrical connectors 3 are formed; similarly, when forming the electrical connection structures 4 on the second chips 12, a plurality of second chips 11 are collectively processed on a wafer before dicing, and after forming the electrical connection structures 4 on the second chips 12, the wafer carrying the second chips 12 is diced to form individual second chips 12.

In view of the above, another embodiment of the present invention further discloses a packaging method of a three-dimensional packaging structure, including the following steps:

s100: providing a first wafer, wherein the first wafer comprises a plurality of first chips 11, and a plurality of first bonding pads 111 are arranged on the front surfaces of the first chips 11;

providing a prefabricated electrical connector, electrically connecting the electrical connector to the first pad 111; specifically, the electrical connector 3 may be soldered on the first pad 111 by a ball-mounting process;

s200: providing a second wafer, wherein the second wafer comprises a plurality of second chips 12, a plurality of second bonding pads 121 are arranged on the front surfaces of the second chips 12, and the electrical connection structures 4 are formed on the second bonding pads 121;

the electric connection structure 4 can be a copper pillar formed on the second bonding pad 121 by electroplating or an electric connection piece 3 welded on the second bonding pad by adopting a ball-planting process;

s300: cutting the second wafer to cut out the single second chip 12, and stacking the single second chip 12 on the front surface of the first chip 11, wherein the front surface of the single second chip 12 is aligned with the front surface of the first chip 11;

the back of the second wafer is required to be thinned before the second wafer is cut, and specifically, the back of the second wafer can be thinned in a physical grinding mode, so that the thickness of the stacked chip packages can be reduced due to the structural arrangement;

the back surface of the single second chip 12 is directly attached to the front surface of the first chip 11, a chip connection area is formed at the front surface of the first chip 11, and the single second chips 12 and the single first chips 11 are in one-to-one correspondence and attached to the chip connection area;

s400: forming an encapsulating layer 5 on the front surface of the first chip 11 and the front surface of the second chip 12; the encapsulating layer 5 is formed by injection molding or film attaching through an injection molding process;

filling a plastic packaging material in a corresponding mold through an injection molding process, coating the first chip 11 and the second chip 12, and heating and curing to form the packaging body 5;

s500: removing part of the encapsulating layer 5 to simultaneously expose the electrical connection structure 4 and the electrical connection member 3 to the outside; specifically, the upper encapsulation layer 5 is removed by using a thinning process and a physical grinding method, it is understood that a part of the electrical connection structure 4 and the electrical connection member 3 is also removed during this step in order to expose the electrical connection structure 4 and the electrical connection member 3;

in a specific embodiment, if the electrical connector 3 has a core 31 and a solder body 32 covering the core 31, when part of the encapsulating layer 5 is removed to simultaneously expose the electrical connection structure 4 and the electrical connector 3, part of the solder body 32 is removed to simultaneously expose the core 31 and the solder body 32;

s600: and forming a rewiring structure above the encapsulating layer 6, and electrically connecting the rewiring structure and the electric connecting structure with the electric connecting piece.

Specifically, S600: forming a rewiring structure 2 above the encapsulating layer and electrically connecting the rewiring structure 2 and the electric connecting structure 4 with the electric connecting piece 3; the method specifically comprises the following steps:

s601: forming a passivation layer on the upper surface of the encapsulation layer, and removing a portion of the passivation layer to form a passivation layer opening 60, wherein the electrical connection structure 4 and the electrical connection member are exposed from the passivation layer opening 60; the detailed prior art of how to remove a portion of the passivation layer to form the passivation layer opening 60 by exposure and development is not described herein again;

in the present exemplary embodiment, the passivation layer opening 60 is located opposite the outwardly exposed core 31 and the size of the passivation layer opening 60 is not greater than the size of the outwardly exposed core 31, the passivation layer 6 covering the upper side of the outwardly exposed solder body 32;

s602: covering a seed layer on the passivation layer, the electric connection structure 4 and the electric connection member 3;

s603: covering a photoresistive layer on the seed layer, and removing partial photoresistive layer at the target position to form a photoresistive layer opening at the target position, wherein the electric connecting piece 3 and the electric connecting structure 4 are exposed outwards from the photoresistive layer opening; specifically, the removal of the photoresist layer also uses the prior art, and is not described again;

s604: electroplating and molding the rewiring structure 2 in the photoresist layer opening;

s605: the specific process for removing the photoresist layer and the seed layer outside the coverage of the rewiring structure 2 is not described again by using the prior art.

The above embodiment shows a structure in which the electrical connector 3 is formed by coating the inner core 31 with the solder body 32 and is soldered to the first land 111 by a ball-planting process, and in another embodiment, the electrical connector includes a metal connector and a solder layer disposed between the metal connector and the first land 111; the step of providing the electrical connection 3 on the first pads 111 on the front side of the first chip 11 specifically comprises the following steps:

the solder layer is patterned on the first pads 111,

and welding the metal connecting piece on the solder layer.

After the rewiring structure is formed on the encapsulating layer 6, the packaging method of the three-dimensional packaging structure further comprises the following steps:

s700: forming a metal bump on the rewiring structure 2, wherein the metal bump is used for being electrically connected with an external circuit substrate; the metal bump is arranged on one side, away from the chip, of the rewiring structure;

s800: and thinning the back surface of the first wafer, and cutting the thinned first wafer to form a single chip.

The construction, features and functions of the present invention are described in detail in the embodiments illustrated in the drawings, which are only preferred embodiments of the present invention, but the present invention is not limited by the drawings, and all equivalent embodiments modified or changed according to the idea of the present invention should fall within the protection scope of the present invention without departing from the spirit of the present invention covered by the description and the drawings.

Claims (14)

1. A three-dimensional package structure, comprising:

the front surface of the first chip is provided with a first bonding pad and a chip connection area formed beside the first bonding pad;

a second chip having a back surface disposed on the chip attach region and a front surface provided with a second pad;

the rewiring structure is arranged in the front direction of the second chip and is electrically connected with the second bonding pad;

and the electric connecting piece is arranged between the rewiring structure and the first bonding pad and is electrically connected with the rewiring structure and the first bonding pad.

2. The three-dimensional package structure of claim 1, wherein the electrical connector comprises a core and a solder body disposed outside the core, the electrical connector is soldered on the pad by the solder body, and the rewiring structure is electrically connected to the core.

3. The three-dimensional package structure according to claim 2, wherein the solder body covers an outside of the core and exposes a top portion of the core toward the rewiring structure for interfacing with the rewiring structure.

4. The three-dimensional package structure according to claim 3, wherein the top of the core and the top of the solder body are planar and located in the same plane, and the solder body has a ring structure in the plane, and the shape of the core in the plane is adapted to the inner ring of the ring structure.

5. The three-dimensional package structure according to claim 4, wherein a passivation layer is disposed between the top surface of the solder body and the rewiring structure, and the solder body is connected to the passivation layer through an IMC layer formed on top of the solder body.

6. The three-dimensional package structure according to claim 5, wherein a minimum distance between any point of the top surface of the solder body and the core is no more than 10 μm.

7. The three-dimensional package structure according to claim 5, wherein in any cross-section of the electrical connection parallel to the top surface of the solder body and through the core, the minimum distance of the solder body from the core at any point on the cross-section is no more than 10 μm.

8. The three-dimensional package structure of claim 2, wherein the core is a partially cut-top metal ball.

9. The three-dimensional package structure according to claim 2, wherein the core has a higher melting point than the solder body; the inner core is made of one of gold, copper, aluminum and silver, and the solder body is made of tin or tin alloy.

10. The three-dimensional package structure of claim 2, wherein the solder body is a solder layer disposed between the core and the pad, and the solder layer has a height not less than 1/3 of the core height and not greater than 1/2 of the core height.

11. The three-dimensional package structure according to claim 1, wherein a distance between the first pad and the rewiring structure is greater than 80 μm.

12. The three-dimensional package structure according to claim 1, wherein the redistribution structure is electrically connected to the second pad through an electrical connection structure, the electrical connection structure being a copper pillar or the electrical connector.

13. The three-dimensional package structure according to claim 12, further comprising:

the encapsulation layer covers the front surface of the chip, and encapsulation gaps are formed at positions of the encapsulation layer corresponding to the electric connecting pieces and the electric connecting structures;

a passivation layer covering the encapsulation layer, wherein passivation layer openings are formed at positions of the passivation layer corresponding to the electric connecting pieces and the electric connecting structure;

the rewiring structure is arranged on the upper side of the electric connecting piece, the upper side of the electric connecting structure and part of the upper side of the passivation layer, and the rewiring structure penetrates through the packaging gap and the passivation layer opening to be connected with the electric connecting piece and the electric connecting structure.

14. A semiconductor device, comprising the three-dimensional package structure according to any one of claims 1 to 13 and a circuit substrate having a substrate pad, wherein a side of the rewiring structure facing away from the chip is provided with a plurality of metal bumps, and the metal bumps are soldered on the substrate pad.

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