CN216054759U - Miniature LED chip, display device and light-emitting device - Google Patents
Miniature LED chip, display device and light-emitting device Download PDFInfo
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- CN216054759U CN216054759U CN202122158321.2U CN202122158321U CN216054759U CN 216054759 U CN216054759 U CN 216054759U CN 202122158321 U CN202122158321 U CN 202122158321U CN 216054759 U CN216054759 U CN 216054759U
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Abstract
The application provides a miniature LED chip, a display device and a light-emitting device. The miniature LED chip comprises a substrate, a first semiconductor layer and a miniature LED unit array, wherein the miniature LED unit array is arranged above the first semiconductor layer, a metal grid line is arranged between the miniature LED units, each miniature LED unit comprises a second electrode, first electrodes are arranged at the edges of the periphery of the miniature LED chip, and the metal grid line is electrically connected with the first electrodes. The Micro LED chip provided by the application can utilize the area of the epitaxial wafer to the maximum extent, so that a high-quality Micro-LED device is prepared, and a high PPI and high-resolution Micro display screen is realized.
Description
Technical Field
The application relates to the field of display, in particular to a micro LED chip, a display device and a light-emitting device.
Background
Micro-LEDs (Micro-LEDs) are an emerging semiconductor technology in recent years, and are expected to become the main technology of AR/VR display in the future due to their characteristics such as high brightness, high stability, and fast refresh rate. To fit AR/VR applications, it becomes crucial to develop micro-LED microdisplays with ultra-high brightness and ultra-high PPI (Pixels Per Inch of pixel count).
However, in the prior art, the P electrode and the N electrode are respectively disposed and electrically connected to the P-type semiconductor and the N-type semiconductor, and the P electrode and the N electrode occupy a larger area of the epitaxial wafer, so that the area of the LED unit on the epitaxial wafer is smaller and the PPI is lower.
SUMMERY OF THE UTILITY MODEL
In order to solve the technical problem, the application provides a micro LED chip, a display device and a light emitting device. The Micro LED chip provided by the application can utilize the area of the epitaxial wafer to the maximum extent, so that a high-quality Micro-LED device is prepared, and a high PPI and high-resolution Micro display screen is realized.
In order to realize the above-mentioned purpose, this application provides a miniature LED chip, including substrate, first semiconductor layer, miniature LED unit array set up in first semiconductor layer top is adjacent be equipped with metal grid line, every between the miniature LED unit includes the second electrode, miniature LED chip edge all around is equipped with first electrode, metal grid line with first electrode electricity is connected.
Optionally, the width of the metal grid line is smaller than the interval between adjacent micro LED units and smaller than the width of the micro LED unit. This application is through interlude metal gridline between miniature LED unit to be connected with miniature LED chip edge's first electrode electricity all around, thereby greatly improved the utilization ratio of epitaxial wafer, increased the electric current homogeneity.
Optionally, the micro LED unit further includes a second semiconductor layer and a multiple quantum well structure, and the second semiconductor layer is disposed above the multiple quantum well structure.
Optionally, the micro LED unit further includes a current diffusion layer disposed between the second semiconductor layer and the second electrode, and the second electrode is electrically connected to the second semiconductor layer through the current diffusion layer.
Optionally, the current diffusion layer is a single metal layer or a multi-layer metal layer structure.
Optionally, the current diffusion layer includes any one of nickel-gold metal, aluminum-based metal, and indium tin oxide, and is preferably a nickel/gold double-layer metal layer structure, wherein a thickness ratio of the nickel metal layer to the gold metal layer is 1: 1.
Optionally, a passivation layer is disposed around the micro LED unit to isolate the micro LED unit and avoid short circuit.
Optionally, a passivation layer is disposed above the metal grid lines to protect the metal grid lines and prevent the metal grid lines from being electrically connected to the second electrode.
Optionally, the material of the passivation layer may be one or more of silicon dioxide, silicon nitride, and aluminum oxide.
Optionally, contact pads are arranged on the first electrode and the second electrode, the contact pads are electrically connected with the first electrode and the second electrode respectively, and the contact pads are used for realizing the electrical connection between the micro LED chip and an external circuit.
Optionally, the contact pad comprises one or more of indium, titanium, aluminum, nickel, gold, chromium, platinum.
Optionally, the first electrode, the second electrode, and the metal grid line adopt a multi-layer metal layer structure.
Optionally, the first electrode, the second electrode, and the metal grid lines comprise one or more of titanium, aluminum, gold, chromium, nickel, and platinum.
Optionally, the first electrode, the second electrode, and the metal grid line adopt a titanium/aluminum/titanium/gold multilayer metal layer structure, wherein a thickness ratio of the titanium/aluminum/titanium/gold four-layer metal layer is 3:12:1: 5.
The application also provides a display device, wherein the display device comprises the micro LED chip.
The present application also provides a light emitting device, wherein the light emitting device includes the micro LED chip.
The application provides a miniature LED chip is through the interval of reasonable control miniature LED unit to set up the metal grid line on the first semiconductor layer between adjacent miniature LED unit, collect and conduct current to first electrode through the metal grid line, not only effectively increased epitaxial wafer area utilization ratio, improved the electric current homogeneity moreover, have advantages such as high quality, high PPI, high resolution.
Drawings
The above and other objects, features and advantages of exemplary embodiments of the present application will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the present application are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar or corresponding parts and in which:
fig. 1 shows a schematic cross-sectional structure of a micro LED chip according to an embodiment of the present application;
fig. 2 illustrates a schematic cross-sectional structure of a micro LED chip according to another embodiment of the present application;
FIG. 3 shows a flow chart of a method of fabricating a micro LED chip according to one embodiment of the present application;
FIG. 4 shows a flow chart of a method of fabricating a micro LED chip according to a preferred embodiment of the present application;
FIGS. 5a-5f illustrate a schematic flow chart of a process for manufacturing a micro LED chip according to a preferred embodiment of the present application;
fig. 6 shows a flow chart of a method of manufacturing a micro LED chip according to another preferred embodiment of the present application.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
Spatially relative terms, such as "over", "above", "on", "in. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above" may include both an orientation of "above" and "below". The device may also be oriented 90 degrees or at other orientations and the spatially relative descriptors used herein interpreted accordingly.
Exemplary embodiments according to the present application will now be described in more detail with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and the same devices are denoted by the same reference numerals, and thus the description thereof will be omitted.
One embodiment of the present application provides a micro LED chip, as shown in fig. 1, a micro LED chip 200 includes a substrate 104, a first semiconductor layer 103, and a micro LED unit array, wherein the micro LED unit array includes a plurality of micro LED units disposed above the first semiconductor layer 103; each micro LED unit comprises a multi-quantum well structure 102, a second semiconductor layer 101, a current diffusion layer 105 and a second electrode 106 which are sequentially stacked from bottom to top; a metal grid line 1072 is arranged above the first semiconductor layer 103 between the adjacent micro LED units, a first electrode 1071 is arranged above the first semiconductor layer 103 at the peripheral edge of the micro LED chip, and the metal grid line 1072 is electrically connected with the first electrode 1071; the first electrode 1071, the second electrode 106, and the metal grid lines 1072 form an electrode structure of the micro LED chip 200.
It will be understood by those skilled in the art that the size of each micro LED unit and/or the number of micro LED units can be set according to actual needs, and is not limited herein.
As a preferred embodiment, the spacing between adjacent micro LED units is smaller than the width of the micro LED units; the width of the metal grid lines 1072 is less than the spacing between adjacent micro LED units; the size of the second electrode 106 is smaller than the size of the micro LED unit.
As a preferred embodiment, a passivation layer 108 is disposed over the first electrode 1071, the second electrode 106, and the metal gridlines 1072 to protect the electrodes and prevent direct contact between the first electrode and the metal gridlines and the second electrode; wherein the passivation layer 108 over the first electrode 1071 and the second electrode 106 is provided with an electrode contact hole to expose a portion of the first electrode and the second electrode; contact pads 110 are provided in the electrode contact holes to electrically connect the first electrode 1071 and the second electrode 106 to an external circuit.
As a preferred embodiment, the first semiconductor layer 103 is an N-type semiconductor layer, preferably N-GaN; the second semiconductor layer 101 is a P-type semiconductor layer, preferably P-GaN; the current diffusion layer 105 may be a single-layer metal layer structure, a multi-layer metal layer structure, or an ITO layer, and may be, for example, any one of nickel-gold metal, aluminum-based metal, and indium tin oxide, and preferably a nickel/gold double-layer metal layer structure, where the thickness ratio of the nickel metal layer to the gold metal layer is 1: 1; the passivation layer 108 may be made of silicon dioxide, silicon nitride, aluminum oxide, or the like, preferably silicon dioxide; the N-electrode 107 includes a first electrode 1071 and metal gridlines 1072, wherein,the metal grid lines 1072 are used for collecting and conducting the N-electrode current of the micro LED unit to the first electrode 1071, and the P-electrode 106, i.e. the second electrode 106, is used for conducting the P-electrode current of the micro LED unit; the materials and/or structures of the first electrode 1071, the second electrode 106 and the metal grid lines 1072 may be the same or different, and may adopt a single-layer structure or a multi-layer structure, and may include one or more of titanium, aluminum, gold, chromium, nickel and platinum, and preferably adopt the same titanium/aluminum/titanium/gold multi-layer metal layer structure, wherein the thickness ratio of the titanium/aluminum/titanium/gold four-layer metal layer is 3:12:1:5, and preferably the thicknesses thereof are sequentially in sequence
The metal grid lines 1072 are preferably the same material and structure as the first electrode 1071.
The application provides a miniature LED chip is through alternating metal grid line between miniature LED unit to be connected with miniature LED chip edge's first electrode electricity all around, thereby greatly improved the utilization ratio of epitaxial wafer, increased the electric current homogeneity, have advantages such as high quality, high PPI, high resolution. In addition, according to the micro LED chip of the embodiment, the contact area between the current diffusion layer and the metal layer is large, and the current uniformity is further improved.
Another embodiment of the present application provides a micro LED chip, as shown in fig. 2, the micro LED chip 300 includes a substrate 104, a first semiconductor layer 103, and a micro LED unit array, wherein the micro LED unit array includes a plurality of micro LED units, and is disposed above the first semiconductor layer 103; each micro LED unit comprises a multi-quantum well structure 102, a second semiconductor layer 101, a current diffusion layer 105 and a second electrode 106' which are sequentially stacked from bottom to top; a metal grid line 1072 'is arranged above the first semiconductor layer 103 between the adjacent micro LED units, a first electrode 1071' is arranged above the first semiconductor layer 103 at the peripheral edge of the micro LED chip, and the metal grid line 1072 'is electrically connected with the first electrode 1071'; the first electrode 1071 ', the second electrode 106 ', and the metal grid lines 1072 ' constitute an electrode structure of the micro LED chip 300.
It will be understood by those skilled in the art that the size of each micro LED unit and/or the number of micro LED units can be set according to actual needs, and is not limited herein.
The passivation layer 108 'is arranged on the periphery of each micro LED unit, and the passivation layer 108' is etched to form a preset pattern so as to expose part of the current diffusion layer 105 and part of the first semiconductor layer 103; the first electrode 1071 ', the second electrode 106', and the metal grid line 1072 'are respectively disposed at corresponding positions of a predetermined pattern of the passivation layer 108' to form the above-mentioned electrode structure, so as to achieve electrical connection between the micro LED units and current conduction of the micro LED units.
As a preferred embodiment, the first electrode 1071 'and the second electrode 106' are provided with contact pads for a flip-chip process to electrically connect the micro LED chip with an external circuit. The position, size, shape, number, etc. of the contact pads may be set according to actual needs, and are not particularly limited herein.
As a preferred embodiment, the first semiconductor layer 103 is an N-type semiconductor layer, preferably N-GaN; the second semiconductor layer 101 is a P-type semiconductor layer, preferably P-GaN; the current diffusion layer 105 may be a single-layer metal layer structure, a multi-layer metal layer structure, or an ITO layer, and may be, for example, any one of nickel-gold metal, aluminum-based metal, and indium tin oxide, and preferably a nickel/gold double-layer metal layer structure, where the thickness ratio of the nickel metal layer to the gold metal layer is 1: 1; the passivation layer 108' may be made of silicon dioxide, silicon nitride, aluminum oxide, etc., preferably, silicon dioxide; the N electrode 107 ' includes a first electrode 1071 ' and a metal grid line 1072 ', wherein the metal grid line 1072 ' is used for collecting and conducting an N electrode current of the micro LED unit to the first electrode 1071 ', and the P electrode 106 ', i.e. the second electrode 106 ', is used for conducting a P electrode current of the micro LED unit; the first electrode 1071 ', the second electrode 106 ', and the metal grid lines 1072 ' may be the same or different in material and/or structure, may have a single-layer structure or a multi-layer structure, and may include titanium, aluminum, and goldOne or more of chromium, nickel and platinum preferably adopt the same titanium/aluminum/titanium/gold multilayer metal layer structure, wherein the thickness ratio of the titanium/aluminum/titanium/gold four-layer metal layer is 3:12:1:5, and the thicknesses of the four-layer metal layer are preferably sequentially
The material and structure of the metal grid lines 1072 ' are preferably the same as the first electrode 1071 ', and the width of the metal grid lines 1072 ' is preferably smaller than the width of the micro LED unit.
The application provides a miniature LED chip is through alternating metal grid line between miniature LED unit to be connected with miniature LED chip edge's first electrode electricity all around, thereby greatly improved the utilization ratio of epitaxial wafer, increased the electric current homogeneity, have advantages such as high quality, high PPI, high resolution. In addition, according to the micro LED chip provided by the embodiment, the first electrode, the second electrode and the metal grid line are disposed at corresponding positions of the passivation layer preset pattern, so that short circuit of the electrodes is effectively avoided, and the yield of the micro LED chip is improved.
Another embodiment of the present application also provides a display device including the micro LED chip of the present application.
As a preferred embodiment, the display device further comprises an IC chip, a shift register, and a data selector, wherein the micro LED chip is flip-chip bonded to the IC chip to electrically connect the micro LED chip to the IC chip; the IC chip is electrically connected with the shift register and the data selector respectively.
The display device provided by the embodiment of the application can realize high PPI (polymer PPI) and has good device quality, and the display device can be applied to a display screen of electronic equipment. The electronic device may include: any device with a display screen, such as a smart phone, a smart watch, a laptop, a tablet computer, a vehicle data recorder, a navigator, a Virtual Reality (VR)/Augmented Reality (AR) display, etc.
Another embodiment of the present application also provides a light emitting device. The light-emitting device comprises the micro LED chip. The light emitting means may be, for example, a lighting means and an indicating means. The lighting device may be, for example, various lamps for illumination. The indicating means may be, for example, various indicator lights for indicating action.
One embodiment of the present application provides a method for manufacturing a micro LED chip. Referring to fig. 3, the method for manufacturing the micro LED chip includes the following steps S301 to S303:
step S301: etching the LED wafer to expose part of the first semiconductor layer and obtain a plurality of table tops;
step S302: a current diffusion layer is arranged on the table top;
step S303: arranging a metal layer on the current diffusion layer and the first semiconductor layer to form an electrode structure comprising a first electrode, a second electrode and metal grid lines; the first electrode is arranged on the first semiconductor layer at the peripheral edge of the wafer; the second electrode is arranged on the current diffusion layer; the metal grid lines are arranged on the first semiconductor layer between the adjacent table tops.
In step S301, the LED wafer is etched to expose a portion of the first semiconductor layer and obtain a plurality of mesas.
According to an embodiment of the application, the photoresist is used as a mask, and an inductively coupled plasma etching method is adopted to remove part of the second semiconductor layer and the multiple quantum well structure on the LED wafer to expose the first semiconductor layer; removing the residual photoresist to obtain a plurality of mesas; the width of the first semiconductor layer exposed between the adjacent mesas is smaller than that of the mesas.
In step S302, a current diffusion layer is provided on the mesa.
According to one embodiment of the present application, a mask pattern may be formed on the etched wafer using a photoresist, and the current diffusion layer may be deposited thereon; and then removing the current diffusion layer on the first semiconductor layer by adopting a stripping method, and only remaining the current diffusion layer on the mesa.
In step S303, a metal layer is disposed on the current diffusion layer and the first semiconductor layer to form an electrode structure including a first electrode, a second electrode, and metal grid lines; the first electrode is arranged on the first semiconductor layer at the peripheral edge of the wafer; the second electrode is arranged on the current diffusion layer; the metal grid lines are arranged on the first semiconductor layer between the adjacent table tops.
According to an embodiment of the present application, a metal layer may be directly deposited on the current diffusion layer and the first semiconductor layer to form an electrode structure including a first electrode, a second electrode, and metal grid lines.
According to another embodiment of the present application, a passivation layer may be deposited on the current spreading layer and the first semiconductor layer; etching the passivation layer to expose part of the current diffusion layer and the first semiconductor layer; and depositing a metal layer on the exposed part of the current diffusion layer and the first semiconductor layer to form an electrode structure comprising a first electrode, a second electrode and metal grid lines.
As a preferred embodiment, after disposing the metal layer on the current diffusion layer and the first semiconductor layer, the method further includes: contact pads are disposed on the first and second electrodes.
According to an embodiment of the present application, a passivation layer may be deposited on the metal layer, and the passivation layers of the first electrode and the second electrode may be etched to etch an electrode contact hole; depositing the contact pad at the electrode contact hole.
According to another embodiment of the present application, contact pads may be directly deposited on the first electrode and the second electrode, wherein the position, size, shape, number, etc. of the contact pads may be set according to actual needs, and are not particularly limited herein.
The method for manufacturing the micro LED chip of the present application is described in detail below by two preferred embodiments.
As a preferred embodiment, referring to fig. 4 and fig. 5a to 5f, the method for manufacturing a micro LED chip provided by the preferred embodiment includes the following steps S401 to S405 for manufacturing the micro LED chip according to the aforementioned first embodiment of the present application.
Step S401: etching the LED wafer to expose part of the first semiconductor layer and obtain a plurality of mesas (Mesa);
as shown in fig. 5a and 5b, an LED epitaxial wafer, preferably an LED epitaxial wafer with a standard multiple quantum well structure, is adopted as the LED wafer 100, and includes a substrate 104, a first semiconductor layer 103, a multiple quantum well structure 102, and a second semiconductor layer 101, which are sequentially stacked from bottom to top; the LED epitaxial wafer can be purchased directly or prepared by adopting the prior art, and is not described again; etching the LED wafer by using the photoresist as a mask and adopting an Inductively Coupled Plasma (ICP) etching method, removing a part of the second semiconductor layer 101 and the multi-quantum well structure 102 on the LED wafer, and exposing the first semiconductor layer 103; removing the residual photoresist by adopting an ICP dry method or a photoresist removing liquid wet method, and cleaning by using a strong acid strong oxidizing solution to obtain a plurality of mesas (Mesa); each Mesa comprises a multi-quantum well structure 102 and a second semiconductor layer 101 which are stacked from bottom to top, the number of mesas can be set according to actual needs, the size of each Mesa and the distance between adjacent mesas can also be set according to actual needs, and the distance between adjacent mesas is preferably smaller than the size of a single Mesa;
as a specific example, the first semiconductor layer 103 is an N-type semiconductor layer, preferably N-GaN; the second semiconductor layer 101 is a P-type semiconductor layer, preferably P-GaN; the photoresist adopts one or more of silicon dioxide, silicon nitride and aluminum oxide; the etching process gas may be Ar and BI3Wherein Ar and BI3The gas flow rates of (a) and (b) may all be set to 10sccm, the etch gas pressure may be set to 8mTorr, the radio frequency power (Source RF) may be set to 100W, the radio frequency Bias (Bias RF) may be set to 20W, and the etch time may be set to 10 min; etching and removing the residual photoresist to obtain a P-type semiconductor Mesa array;
step S402: depositing a current spreading layer on the mesa;
as shown in fig. 5c, a mask pattern is formed on the wafer obtained in step S401 by using a photoresist, and a current diffusion layer is deposited thereon by using electron beam evaporation, plasma sputtering, or thermal evaporation; immersing the obtained wafer deposited with the current diffusion layer into an acetone solution for ultrasonic treatment for 5 minutes, then immersing the wafer into an isopropanol solution for ultrasonic treatment for 5 minutes, and finally cleaning the wafer by using deionized water to remove the current diffusion layer on the first semiconductor layer and only keep the current diffusion layer 105 on the Mesa; the current diffusion layer 105 may be a single-layer metal layer, a multi-layer metal layer, or an ITO layer, and the current diffusion layer 105 is preferably any one of nickel-gold metal, metal mainly containing aluminum, and ITO;
in one specific embodiment, the current diffusion layer 105 is a nickel/gold double-layer metal layer, wherein the thicknesses of the nickel metal layer and the gold metal layer are set to be equal
The nickel/gold double-layer metal layer is deposited by adopting an electron beam evaporation mode, and the gas flow rate can be set as follows: ar of 300sccm, O23 sccm; the radio frequency power can be set to 50W;
as a preferred embodiment, after the current diffusion layer is prepared, the current diffusion layer is subjected to an annealing treatment. Specifically, in the case where the current diffusion layer is nickel-gold metal, the wafer provided with the current diffusion layer was placed on N at a temperature of 570 ℃2Treating in gas atmosphere for 5min, and placing in N2And O2Treating in mixed gas environment for 5min, wherein N2And O2At a volume ratio of 4:1, and finally carrying out rapid cooling; in the case where the current diffusion layer is a metal based on aluminum, the wafer provided with the current diffusion layer is placed in N at a temperature of 850 deg.C2Treating in gas environment for 5 min; in the case where the current diffusion layer is ITO, the wafer provided with the current diffusion layer is placed in O at a temperature of 600 deg.C2Treating in a gas atmosphere for 300s to oxidize the ITO, and then placing in N at a temperature of 750 DEG C2Treating in a gas environment for 30s, so as to obtain the ITO alloy;
step S403: depositing a metal layer on the current diffusion layer and the first semiconductor layer to form an electrode structure comprising a first electrode, a second electrode and metal grid lines;
as shown in fig. 5d, the metal layer includes a first metal layer 107 and a second metal layer 106, and the first metal layer 107 and the second metal layer 106 may be the same or different and may have a single-layer structure or a multi-layer structure; the first metal layer 107 is electrically connected to the first semiconductor layer 103, and includes a metal grid line deposited on the first semiconductor layer 103 exposed between adjacent mesas and a first electrode deposited on the first semiconductor layer 103 exposed at the peripheral edge of the wafer, and the metal grid line is electrically connected to the first electrode; the second metal layer 106 is electrically connected to the second semiconductor layer 101 through the current diffusion layer 105 as a second electrode; the metal layer can be deposited by adopting an electron beam evaporation method, a plasma sputtering method or a thermal evaporation method, and different first metal layer 107 and second metal layer 106 can be obtained by adopting a photoetching stripping method twice; the photoetching stripping method and the preparation method of the current diffusion layer are not described again; the material of the metal layer can be one or more of titanium, aluminum, gold, chromium, nickel and platinum;
as a specific embodiment, the first metal layer 107 and the second metal layer 106 are the same, and both adopt a titanium/aluminum/titanium/gold multilayer metal layer structure, and the thicknesses of the titanium/aluminum/titanium/gold four metal layers are sequentially
Step S404: depositing a passivation layer on the metal layer, and etching the passivation layer on the first electrode and the passivation layer on the second electrode to etch an electrode contact hole;
as shown in fig. 5e, the passivation layer 108 may be deposited using Plasma Enhanced Chemical Vapor Deposition (PECVD); the electrode contact holes 109 may be obtained by dry etching and/or wet etching; the passivation layer 108 may be made of silicon dioxide, silicon nitride, aluminum oxide, or the like;
as a specific example, a PECVD process is used to deposit a silicon dioxide passivation layer 108, wherein SiH4The flow rate of the deposition solution is increased from 10sccm to 20sccm, the deposition temperature is 160 ℃, the deposition time is 12min, and the deposition thickness is 600 nm; after the deposition is finished, the wafer is put inBaking in an oven at 120 deg.C for 30 min to evaporate water vapor on the wafer; then, a tackifier hexamethyldioxane is coated, and the passivation layers on the first electrode and the second electrode are etched by using a photoetching mode to etch the electrode contact hole 109 to expose part of the first metal layer 107 and the second metal layer 106, wherein the embodiment preferably adopts a mode of 'dry etching and wet etching', wherein in the process of dry etching, the etching pressure can be set to be 8mTorr, and Ar and SF can be adopted as process gas6Mixed gas of (2), argon and SF6The gas flow rates of (A) and (B) can be set to 60sccm and 20sccm respectively, the radio frequency power (Source RF) can be set to 100W, the radio frequency Bias (Bias RF) can be set to 20W, and the etching time can be set to 280 s; in the wet etching process, BOE or 777 solution can be used as the etching solution, and the wet etching time depends on the thickness of the passivation layer left after dry etching; if the process requirement is not high, the electrode contact hole can be obtained by independently adopting a dry etching or wet etching mode; the position, size, shape, number and the like of the electrode contact holes can be set according to actual needs;
step S405: depositing a contact pad at the electrode contact hole;
as shown in fig. 5f, the contact pad 110 is deposited using a photolithographic lift-off process; the contact pad 110 may be made of one or more metals such as indium, titanium, aluminum, nickel, gold, chromium, platinum, etc.;
as a specific example, a mask pattern is made of photoresist, and indium metal is deposited as the contact pad 110 by electron beam evaporation, plasma sputtering, or thermal evaporation; and removing the indium metal outside the electrode contact hole by adopting a stripping method, so that the indium metal is electrically connected with the first electrode and the second electrode through the electrode contact hole.
According to the preparation method of the micro LED chip provided by the preferred embodiment of the application, the first electrode is arranged at the periphery of the micro LED chip, the metal grid lines are arranged on the first semiconductor layer between the adjacent Mesa structures, and the current is collected and conducted to the first electrode through the metal grid lines, so that the area utilization rate of the epitaxial wafer is effectively increased, and the current uniformity is improved. In addition, according to the preparation method of the preferred embodiment, the metal layer is directly deposited on the current diffusion layer and the first semiconductor layer, so that the contact area of the electrode and the current diffusion layer and the first semiconductor layer is effectively increased, and the current uniformity is improved.
As another preferred embodiment, as shown in fig. 6, the method for manufacturing a micro LED chip provided by this preferred embodiment includes the following steps S601-S605 to manufacture the micro LED chip according to the aforementioned second embodiment of the present application.
Step S601: etching the LED wafer to expose part of the first semiconductor layer and obtain a plurality of mesas (Mesa);
specifically, the photoresist is used as a mask, an Inductively Coupled Plasma (ICP) etching method is adopted to etch the LED wafer, a part of the second semiconductor layer and the multi-quantum well structure on the LED wafer is removed, and the first semiconductor layer is exposed; removing the residual photoresist by adopting an ICP dry method or a photoresist removing liquid wet method, and cleaning by using a strong acid strong oxidizing solution to obtain a plurality of mesas (Mesa); each Mesa comprises a multi-quantum well structure and a second semiconductor layer which are stacked from bottom to top, the number of the Mesas can be set according to actual needs, the size of each Mesa and the distance between every two adjacent Mesas can also be set according to actual needs, and the distance between every two adjacent Mesas is preferably smaller than the size of a single Mesa;
as a specific example, the first semiconductor layer is an N-type semiconductor layer, preferably N-GaN; the second semiconductor layer is a P-type semiconductor layer, preferably P-GaN; the photoresist adopts one or more of silicon dioxide, silicon nitride and aluminum oxide; the etching process gas may be Ar and BI3Wherein Ar and BI3The gas flow rates of (a) and (b) may all be set to 10sccm, the etch gas pressure may be set to 8mTorr, the radio frequency power (Source RF) may be set to 100W, the radio frequency Bias (Bias RF) may be set to 20W, and the etch time may be set to 10 min; etching and removing the residual photoresist to obtain a P-type semiconductor Mesa array;
step S602: depositing a current spreading layer on the mesa;
specifically, a mask pattern is manufactured on the wafer obtained in step S601 by using a photoresist, and a current diffusion layer is deposited thereon by using electron beam evaporation, plasma sputtering, or thermal evaporation; immersing the obtained wafer deposited with the current diffusion layer into an acetone solution for ultrasonic treatment for 5 minutes, then immersing the wafer into an isopropanol solution for ultrasonic treatment for 5 minutes, and finally cleaning the wafer by using deionized water to remove the current diffusion layer on the first semiconductor layer and only keep the current diffusion layer on the Mesa; the current diffusion layer 105 may be a single-layer metal layer, a multi-layer metal layer, or an ITO layer, and is preferably any one of nickel-gold metal, metal mainly containing aluminum, and ITO;
as a specific example, the current diffusion layer adopts a nickel/gold double-layer metal layer, wherein the thicknesses of the nickel metal layer and the gold metal layer are set to be
The nickel/gold double-layer metal layer is deposited by adopting an electron beam evaporation mode, and the gas flow rate can be set as follows: ar of 300sccm, O23 sccm; the radio frequency power can be set to 50W;
as a preferred embodiment, after the current diffusion layer is prepared, the current diffusion layer is subjected to an annealing treatment. Specifically, in the case where the current diffusion layer is nickel-gold metal, the wafer provided with the current diffusion layer was placed on N at a temperature of 570 ℃2Treating in gas atmosphere for 5min, and placing in N2And O2Treating in mixed gas environment for 5min, wherein N2And O2At a volume ratio of 4:1, and finally carrying out rapid cooling; in the case where the current diffusion layer is a metal based on aluminum, the wafer provided with the current diffusion layer is placed in N at a temperature of 850 deg.C2Treating in gas environment for 5 min; in the case where the current diffusion layer is ITO, the wafer provided with the current diffusion layer is placed in O at a temperature of 600 deg.C2Treating in a gas atmosphere for 300s to oxidize the ITO, and then placing in N at a temperature of 750 DEG C2Treating in a gas environment for 30s, so as to obtain the ITO alloy;
step S603: depositing a passivation layer on the current spreading layer and the first semiconductor layer;
specifically, the passivation layer may be deposited using Plasma Enhanced Chemical Vapor Deposition (PECVD), and may be deposited using a Plasma Enhanced Chemical Vapor Deposition (PECVD)Is silicon dioxide, silicon nitride, or aluminum oxide; wherein is SiH4The flow rate of the deposition solution is increased from 10sccm to 20sccm, the deposition temperature is 160 ℃, the deposition time is 12min, and the deposition thickness is 600 nm; after deposition, the wafer is put into an oven with the temperature of 120 ℃ to be baked for 30 minutes so as to evaporate water vapor on the wafer;
step S604: etching the passivation layer to expose part of the current diffusion layer and the first semiconductor layer;
specifically, a tackifier hexamethyl dioxane is coated, and the current diffusion layer and the passivation layer on the first semiconductor layer are etched in a photoetching mode to expose part of the current diffusion layer and the first semiconductor layer; the first semiconductor layer exposed among the Mesa is in a grid shape, the first semiconductor layer exposed at the peripheral edge of the wafer is in a strip shape, and the current diffusion layer exposed on the Mesa is in a circular or square shape;
the passivation layer can be etched by adopting a dry etching and/or wet etching mode, and the dry etching and wet etching mode is preferred in the embodiment, wherein in the dry etching process, the etching pressure can be set to be 8mTorr, and Ar and SF can be adopted as process gas6Mixed gas of (2), argon and SF6The gas flow rates of (A) and (B) can be set to 60sccm and 20sccm respectively, the radio frequency power (Source RF) can be set to 100W, the radio frequency Bias (Bias RF) can be set to 20W, and the etching time can be set to 280 s; in the wet etching process, BOE or 777 solution can be used as the etching solution, and the wet etching time depends on the thickness of the passivation layer left after dry etching; if the process requirement is not high, the passivation layer can be etched in a dry etching or wet etching mode independently;
step S605: depositing a metal layer on the exposed part of the current diffusion layer and the first semiconductor layer to form an electrode structure comprising a first electrode, a second electrode and metal grid lines;
specifically, a first metal layer is deposited on a first semiconductor layer exposed between mesas and in a grid shape and a first semiconductor layer exposed at the peripheral edge of a wafer and in a strip shape, so as to obtain a metal grid line and a first electrode respectively, wherein the metal grid line is electrically connected with the first semiconductor layer and is used for collecting and conducting a first current of the micro LED unit, and the first electrode is electrically connected with the metal grid line and the first semiconductor layer and is used for collecting and conducting the first current (for example, an N-pole current); depositing a second metal layer on the circular or square current diffusion layer exposed on the Mesa to obtain a second electrode, wherein the second electrode is electrically connected with the second semiconductor through the current diffusion layer for conducting a second current (for example, a P-pole current);
the first metal layer and the second metal layer may be the same or different, and may have a single-layer structure or a multi-layer structure; the metal layer can be deposited by adopting an electron beam evaporation method, a plasma sputtering method or a thermal evaporation method, and different first metal layers and second metal layers can be obtained by adopting a photoetching stripping method twice; the photoetching stripping method and the preparation method of the current diffusion layer are not described again; the material of the metal layer can be one or more of titanium, aluminum, gold, chromium, nickel and platinum;
as a specific embodiment, the first electrode, the second electrode and the metal grid lines have the same structure, and all adopt a titanium/aluminum/titanium/gold multilayer metal layer structure, and the thicknesses of the titanium/aluminum/titanium/gold four metal layers are sequentially
As a preferred embodiment, the method for manufacturing a micro LED chip further includes: and depositing a metal layer on the exposed part of the current diffusion layer and the first semiconductor layer, forming an electrode structure comprising a first electrode, a second electrode and metal grid lines, and then depositing a contact pad on the first electrode and the second electrode.
Specifically, a contact pad is deposited by a photolithographic lift-off method; one or more of indium, titanium, aluminum, nickel, gold, chromium, platinum, etc. metals may be used for the contact pads. For example, a mask pattern is made by using a photoresist, indium metal is deposited on the first electrode and the second electrode by using an electron beam evaporation method, a plasma sputtering method or a thermal evaporation method, and then an indium metal contact pad is obtained by using a stripping method; the indium metal contact pad is electrically connected to the first electrode or the second electrode. The position, size, shape, number, etc. of the contact pads may be set according to actual needs, and are not particularly limited herein.
According to the preparation method of the micro LED chip provided by the preferred embodiment of the application, the first electrode is arranged at the periphery of the micro LED chip, the metal grid lines are arranged on the first semiconductor layer between the adjacent Mesa structures, and the current is collected and conducted to the first electrode through the metal grid lines, so that the area utilization rate of the epitaxial wafer is effectively increased, and the current uniformity is improved. In addition, according to the preparation method of the preferred embodiment, the passivation layer is deposited firstly, and then the hole is formed in the passivation layer to deposit the electrode, so that the short circuit of the electrode is effectively avoided, and the yield of the micro LED chip is improved.
As a preferred embodiment, before etching the LED wafer, the method further comprises the steps of: preprocessing the LED wafer;
specifically, the pretreatment comprises: immersing the LED wafer in aqua regia (hydrochloric acid: nitric acid ═ 3:1) or sulfuric acid hydrogen peroxide for at least thirty minutes to clean the metal particles on the LED wafer; then, the LED wafer after being cleaned with the metal particles is immersed in a degumming solution (such as MS-2001 solution) tank at 70 ℃ for five minutes to clean the organic particles attached on the LED wafer; then, the LED wafer after being cleaned with the metal particles and the organic particles is put into deionized water for further cleaning; and finally, drying the cleaned LED wafer for later use.
The rest steps are the same as the two aforementioned preferred embodiments for preparing the micro LED chip, and are not described herein again.
In the preferred embodiment, the LED wafer is pretreated to remove the metal particles and the organic particles on the LED wafer, so that the phenomenon of electric leakage or uneven coating of the prepared micro LED chip is avoided, and the influence on the performance of the micro LED chip is avoided.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (13)
1. The utility model provides a miniature LED chip, wherein, miniature LED chip includes substrate, first semiconductor layer, miniature LED unit array set up in first semiconductor layer top is adjacent be equipped with metal gridlines between the miniature LED unit, every the miniature LED unit includes the second electrode, miniature LED chip edge all around is equipped with first electrode, metal gridlines with first electrode electricity is connected.
2. The micro LED chip of claim 1, wherein a width of the metal grid lines is less than a width of the micro LED units.
3. The micro LED chip of claim 1, wherein said micro LED cell further comprises a second semiconductor layer and a multiple quantum well structure, said second semiconductor layer being disposed over said multiple quantum well structure.
4. The micro LED chip of claim 3, wherein the micro LED cell further comprises a current spreading layer disposed between the second semiconductor layer and the second electrode, the second electrode being electrically connected to the second semiconductor layer through the current spreading layer.
5. The micro LED chip of claim 4, wherein said current spreading layer is a single metal layer or a multi-layer metal layer structure.
6. The micro LED chip of claim 4, wherein said current spreading layer comprises any one of nickel gold metal, aluminum-based metal, indium tin oxide.
7. The micro LED chip of claim 6, wherein said current spreading layer is a nickel/gold bi-layer metal layer structure, and the thickness ratio of nickel metal layer to gold metal layer is 1: 1.
8. The micro LED chip of claim 1, wherein a passivation layer is disposed around the micro LED unit or/and over the metal grid lines.
9. The micro LED chip of claim 1, wherein contact pads are provided on said first and second electrodes, said contact pads being electrically connected to said first and second electrodes, respectively.
10. The micro LED chip of claim 1, wherein said first electrode, said second electrode, said metal grid line are in a multi-layer metal layer structure.
11. The micro LED chip of claim 10, wherein said first electrode, said second electrode, said metal grid lines are a titanium/aluminum/titanium/gold multilayer metal layer structure.
12. A display device, wherein the display device comprises the micro LED chip of any one of claims 1 to 11.
13. A light emitting device, wherein the light emitting device comprises the micro LED chip of any one of claims 1 to 11.
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| CN115799233A (en) * | 2022-11-30 | 2023-03-14 | 深圳市思坦科技有限公司 | Light-emitting chip array structure, preparation method and display structure |
| CN115799233B (en) * | 2022-11-30 | 2023-11-28 | 深圳市思坦科技有限公司 | Light-emitting chip array structure, preparation method and display structure |
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