CN216054722U - P-type channel gallium nitride device - Google Patents
P-type channel gallium nitride device Download PDFInfo
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- CN216054722U CN216054722U CN202121975584.6U CN202121975584U CN216054722U CN 216054722 U CN216054722 U CN 216054722U CN 202121975584 U CN202121975584 U CN 202121975584U CN 216054722 U CN216054722 U CN 216054722U
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Abstract
The embodiment of the utility model provides a P-type channel gallium nitride device. The P-channel gallium nitride device includes: a gallium nitride substrate; the gallium nitride aluminum buffer layer is positioned on the surface of the gallium nitride substrate; the P-type gallium nitride layer is positioned on the surface of the gallium nitride aluminum buffer layer away from the gallium nitride substrate; the high-resistance doped region is positioned on the surface of the P-type gallium nitride layer far away from the gallium nitride aluminum buffer layer, wherein the resistivity of the high-resistance doped region is greater than that of the non-doped region of the P-type gallium nitride layer, and the doping depth of the high-resistance doped region is less than the thickness of the P-type gallium nitride layer; the grid electrode is positioned on the surface, far away from the surface of the gallium nitride aluminum buffer layer, of the P-type gallium nitride layer of the high-resistance doped region, and the projection of the high-resistance doped region on the gallium nitride substrate is positioned in the projection of the grid electrode on the gallium nitride substrate; and the source electrode and the drain electrode are positioned on the surface of the P-type gallium nitride layer of the non-doped region, which is far away from the gallium aluminum nitride buffer layer. The technical scheme provided by the embodiment of the utility model realizes an enhanced P-type channel gallium nitride device.
Description
Technical Field
The embodiment of the utility model relates to the technical field of semiconductors, in particular to a P-type channel gallium nitride device.
Background
With the development of semiconductor devices, gallium nitride (GaN) -based semiconductor devices have been widely used in the field of power electronic devices due to their characteristics of wide bandgap, high electron drift saturation velocity, small dielectric constant, good conductivity, etc.
The P-type channel gallium nitride device has the characteristics of low cost and excellent performance, and can replace a silicon-based device in a monolithic integrated CMOS device. Since the P-channel GaN device in the gate region is electrically conductive using the P-type GaN body material, the P-channel GaN device is in an on state without applying a gate voltage. There is a need for an enhanced P-channel gan device.
SUMMERY OF THE UTILITY MODEL
In view of the above, embodiments of the present invention provide a P-channel gan device to realize an enhanced P-channel gan device.
The embodiment of the utility model provides a P-type channel gallium nitride device, which is characterized by comprising the following components:
a gallium nitride substrate;
the gallium nitride aluminum buffer layer is positioned on the surface of the gallium nitride substrate;
the P-type gallium nitride layer is positioned on the surface of the gallium nitride aluminum buffer layer away from the gallium nitride substrate;
the high-resistance doped region is positioned on the surface, far away from the gallium nitride aluminum buffer layer, of the P-type gallium nitride layer, wherein the resistivity of the high-resistance doped region is greater than that of the non-doped region of the P-type gallium nitride layer, and the doping depth of the high-resistance doped region is smaller than the thickness of the P-type gallium nitride layer;
the grid is positioned on the surface, far away from the surface of the gallium nitride aluminum buffer layer, of the P-type gallium nitride layer of the high-resistance doped region, and the projection of the high-resistance doped region on the gallium nitride substrate is positioned in the projection of the grid on the gallium nitride substrate;
and the source electrode and the drain electrode are positioned on the surface of the P-type gallium nitride layer of the non-doped region, which is far away from the gallium nitride aluminum buffer layer.
Optionally, the high-resistance doped region includes a hydrogen high-resistance doped region and/or an oxygen high-resistance doped region.
Optionally, a groove is formed in the surface of the P-type gallium nitride layer away from the gallium nitride aluminum buffer layer, and the depth of the groove is smaller than the thickness of the P-type gallium nitride layer; the high-resistance doped region is positioned on the bottom surface of the groove, wherein the doping depth of the high-resistance doped region is smaller than the vertical distance between the bottom surface of the groove and the surface of the P-type gallium nitride layer adjacent to the gallium nitride aluminum buffer layer.
Optionally, the device further comprises a dielectric layer, the dielectric layer is located on one side of the P-type gallium nitride layer, which is far away from the gallium nitride substrate, a projection of the dielectric layer on the gallium nitride substrate is not overlapped with a projection of the source electrode and the drain electrode on the gallium nitride substrate, and the gate is located on the surface of one side of the dielectric layer, which is far away from the P-type gallium nitride layer.
Optionally, the source electrode includes a first ohmic contact metal layer and a first conductive layer;
the first ohmic contact metal layer is positioned on one side of the P-type gallium nitride layer far away from the gallium nitride substrate;
the first conducting layer is positioned on the surface of one side, away from the P-type gallium nitride layer, of the first ohmic contact metal layer;
and/or the drain electrode comprises a second ohmic contact metal layer and a second conductive layer;
the second ohmic contact metal layer is positioned on one side of the P-type gallium nitride layer far away from the gallium nitride substrate;
the second conducting layer is located on the surface of the second ohmic contact metal layer, far away from one side of the P-type gallium nitride layer.
In the technical scheme provided by the embodiment of the utility model, the P-type gallium nitride layer of the grid electrode positioned in the high-resistance doping area is far away from the surface of the gallium nitride aluminum buffer layer, the projection of the high-resistance doped region on the gallium nitride substrate is positioned in the projection of the grid electrode on the gallium nitride substrate, the resistivity of the high-resistance doped region is greater than that of the non-doped region of the P-type gallium nitride layer, namely, the concentration of the holes in the high-resistance doped region is less than that of the holes in the P-type gallium nitride layer of the non-doped region, compared with the P-type channel gallium nitride device without the high-resistance doped region, the P-type channel gallium nitride device provided by the embodiment of the utility model reduces the concentration of the holes of the grid electrode in the projection region of the gallium nitride substrate, when the grid is applied with positive bias, the non-doped region of the P-type gallium nitride layer between the high resistance doped region and the gallium aluminum nitride buffer layer is called as a P-type channel region, the P-type channel region has a large number of holes flowing through, and the P-type channel gallium nitride device is in an open state. Under the condition that no voltage is applied to the grid electrode, the P-type channel gallium nitride device is in a turn-off state, an enhanced P-type channel gallium nitride device is formed, negative voltage bias is not required to be additionally designed to turn off the device, the complexity of circuit design can be improved, and meanwhile, static power consumption and switching loss under the circuit turn-off state are reduced.
Drawings
Fig. 1 is a schematic structural diagram of a P-channel gan device according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of another P-channel GaN device according to an embodiment of the utility model;
FIG. 3 is a schematic structural diagram of another P-channel GaN device according to an embodiment of the utility model;
FIG. 4 is a schematic structural diagram of another P-channel GaN device according to an embodiment of the utility model;
fig. 5 is a schematic flow chart of a method for manufacturing a P-channel gan device according to an embodiment of the present invention;
fig. 6-9 are flow charts corresponding to steps of a method for fabricating a P-channel gan device according to an embodiment of the present invention;
FIGS. 10-12 are cross-sectional views corresponding to steps of another method for fabricating a P-channel GaN device according to an embodiment of the utility model;
fig. 13 is a schematic flow chart included in step 150 in fig. 5.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the utility model and are not limiting of the utility model. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
The embodiment of the utility model provides a P-type channel gallium nitride device, which can be applied to the field of power electronic devices, replaces a P-type channel silicon-based device in a CMOS (complementary metal oxide semiconductor) device, is an enhanced P-type channel gallium nitride device, does not need to additionally design negative voltage bias to turn off the device, can display and improve the complexity of circuit design, and simultaneously reduces the static power consumption and the switching loss of a circuit in an off state.
Fig. 1 is a schematic structural diagram of a P-channel gan device according to an embodiment of the present invention. Referring to fig. 1, the P-channel gan device includes: a gallium nitride substrate 10; a gallium aluminum nitride buffer layer 20 located on the surface of the gallium nitride substrate 10; the P-type gallium nitride layer 30 is positioned on the surface of the gallium nitride aluminum buffer layer 20 far away from the gallium nitride substrate 10; the high-resistance doped region 31 is positioned on the surface of the P-type gallium nitride layer 30, which is far away from the gallium nitride aluminum buffer layer 20, wherein the resistivity of the high-resistance doped region 31 is greater than that of the non-doped region 32 of the P-type gallium nitride layer 30, and the doping depth H1 of the high-resistance doped region 31 is less than the thickness H2 of the P-type gallium nitride layer 30; the gate 40 is positioned on the P-type gallium nitride layer 30 of the high-resistance doped region 31 and is far away from the surface of the gallium nitride aluminum buffer layer 20, and the projection of the high-resistance doped region 31 on the gallium nitride substrate 10 is positioned in the projection of the gate 40 on the gallium nitride substrate 10; and the source electrode 50 and the drain electrode 60 are positioned on the surface of the P-type gallium nitride layer 30 of the non-doped region 32 far away from the aluminum gallium nitride buffer layer 20.
It is known that enhancement mode (E-mode) devices (also commonly referred to as normally-off devices) require a positive gate voltage to generate channel carriers for the devices to operate normally, and no additional negative voltage bias is required to turn off the devices.
Note that the undoped region 32 of the P-type gallium nitride layer 30 between the high-resistance doped region 31 and the aluminum gallium nitride buffer layer 20 is referred to as a P-type channel region 32A, and a projection of the P-type channel region 32A on the gallium nitride substrate 10 coincides with a projection of the high-resistance doped region 31 on the gallium nitride substrate 10. When a positive bias is applied to the gate 40, a large number of holes flow through the P-channel region 32A, and the P-channel gan device is in an on state. In the case where no voltage is applied to the gate electrode 40, the hole concentration in the P-type channel region 32A is low, and the P-type channel gallium nitride device is in an off state.
In the technical solution provided by the embodiment of the present invention, the gate 40 is located on the surface of the P-type gallium nitride layer 30 of the high-resistance doped region 31 away from the surface of the gallium nitride aluminum buffer layer 20, the projection of the high-resistance doped region 31 on the gallium nitride substrate 10 is located in the projection of the gate 40 on the gallium nitride substrate 10, and the resistivity of the high-resistance doped region 31 is greater than the resistivity of the non-doped region 32 of the P-type gallium nitride layer 30, that is, the hole concentration in the high-resistance doped region 31 is less than the hole concentration of the P-type gallium nitride layer 30 of the non-doped region 32, compared with a P-type channel gallium nitride device without the high-resistance doped region 31, the P-type channel gallium nitride device provided by the embodiment of the present invention reduces the hole concentration of the gate 40 in the projection region of the gallium nitride substrate 10, when a positive bias is applied to the gate 40, the non-doped region 32 of the P-type gallium nitride layer 30 between the high-resistance doped region 31 and the gallium nitride aluminum buffer layer 20 is called a P-type channel region 32A, the P-channel region 32A has a large number of holes flowing through it, and the P-channel gan device is in an on state. Under the condition that no voltage is applied to the grid 40, the P-type channel gallium nitride device is in an off state, an enhanced P-type channel gallium nitride device is formed, negative voltage bias is not required to be additionally designed to turn off the device, the complexity of circuit design can be improved, and meanwhile, static power consumption and switching loss under the off state of the circuit are reduced.
Optionally, on the basis of the above technical solution, referring to fig. 1, the high-resistance doped region 31 includes a hydrogen-element high-resistance doped region and/or an oxygen-element high-resistance doped region.
It is known that the P-type gan layer 30 can be formed by doping the intrinsic gan material with P-type dopant to obtain the P-type gan layer 30. Illustratively, in the P-type gallium nitride layer 30 doped with magnesium element in the embodiment of the present invention, the more magnesium atoms are used to substitute for gallium atoms and form bonds with nitrogen atoms, the higher the hole concentration of the P-type gallium nitride layer 30 is, hydrogen is doped in the P-type gallium nitride layer 30 doped with magnesium element, magnesium-hydrogen bonds can be formed between hydrogen atoms and magnesium atoms, the number of magnesium atoms to substitute for gallium atoms and form bonds with nitrogen atoms is reduced, and further, the hole concentration of the P-type gallium nitride layer 30 doped with magnesium element is reduced, accordingly, the resistivity of a doped region formed by hydrogen is increased, and further, the high-resistance doped region 31 doped with hydrogen is formed. Oxygen is doped in the P-type gallium nitride layer 30 doped with magnesium, on the first hand, magnesium-hydrogen bonds can be formed between hydrogen atoms and magnesium atoms, so that the number of bonds formed by the magnesium atoms instead of gallium atoms and nitrogen atoms is reduced, and further, the hole concentration of the P-type gallium nitride layer 30 doped with magnesium is reduced; in the second aspect, the resistivity of the reactant formed by the reaction of the oxygen atoms and the gallium nitride is increased, and therefore the resistivity of the doped region formed by the oxygen element is increased, and the oxygen-doped high-resistance doped region 31 is formed. Therefore, compared with a P-type channel gallium nitride device without the high-resistance doping region 31, the P-type channel gallium nitride device provided by the embodiment of the utility model reduces the hole concentration of the gate 40 in the projection region of the gallium nitride substrate 10, and when a positive bias is applied to the gate 40, a large number of holes flow through the P-type channel region 32A, and the P-type channel gallium nitride device is in an open state. Under the condition that no voltage is applied to the grid 40, the P-type channel gallium nitride device is in an off state, an enhanced P-type channel gallium nitride device is formed, negative voltage bias is not required to be additionally designed to turn off the device, the complexity of circuit design can be improved, and meanwhile, static power consumption and switching loss under the off state of the circuit are reduced.
In order to increase the gate control capability of the gate 40, the embodiment of the present invention further provides the following technical solutions:
fig. 2 is a schematic structural diagram of another P-channel gan device according to an embodiment of the present invention. Referring to fig. 2, a groove 32B is formed in the surface of the P-type gallium nitride layer 30 away from the aluminum gallium nitride buffer layer 20, and a depth H3 of the groove 32B is smaller than a thickness H2 of the P-type gallium nitride layer 30; the high-resistance doped region 31 is located at the bottom surface of the groove, wherein the doping depth H1 of the high-resistance doped region 31 is smaller than the vertical distance H4 between the bottom surface of the groove 32B and the surface of the P-type gallium nitride layer 30 adjacent to the aluminum gallium nitride buffer layer 20.
Specifically, the arrangement of the groove 32B shortens the distance between the gate 40 and the P-type channel region 32A, and enhances the control capability of the gate 40 on the P-type channel gallium nitride device.
Fig. 3 is a schematic structural diagram of another P-channel gan device according to an embodiment of the present invention. Optionally, on the basis of the above technical solution, referring to fig. 3, the P-channel gan device further includes a dielectric layer 70, the dielectric layer 70 is located on one side of the P-type gan layer 30 away from the gan substrate 10, a projection of the dielectric layer 70 on the gan substrate 10 is not overlapped with a projection of the source 50 and the drain 60 on the gan substrate 10, and the gate 40 is located on a surface of one side of the dielectric layer 70 away from the P-type gan layer 30.
Specifically, the introduction of the dielectric layer 70 can protect the P-type gallium nitride layer 30 when the gate 40 is manufactured; on the other hand, the introduction of the dielectric layer 70 reduces the gate leakage of the P-channel gan device.
Fig. 4 is a schematic structural diagram of another P-channel gan device according to an embodiment of the present invention. Optionally, on the basis of the above technical solution, referring to fig. 4, the source electrode 50 includes a first ohmic contact metal layer 51 and a first conductive layer 52; the first ohmic contact metal layer 51 is positioned on one side of the P-type gallium nitride layer 30 far away from the gallium nitride substrate 10; the first conductive layer 52 is positioned on the surface of the first ohmic contact metal layer 51 on the side far away from the P-type gallium nitride layer 30; and/or, the drain electrode 60 includes a second ohmic contact metal layer 61 and a second conductive layer 62; the second ohmic contact metal layer 61 is positioned on one side of the P-type gallium nitride layer 30 far away from the gallium nitride substrate 10; the second conductive layer 62 is located on the surface of the second ohmic contact metal layer 61 on the side away from the P-type gallium nitride layer 30.
Specifically, the first ohmic contact metal layer 51 is provided so that a good ohmic contact is formed between the first conductive layer 52 and the P-type gallium nitride layer 30. The second ohmic contact metal layer 61 is provided to form a good ohmic contact between the second conductive layer 62 and the P-type gallium nitride layer 30. For example, the first ohmic contact metal layer 51 and the second ohmic contact metal layer 61 may be metal nickel, the metal nickel reacts with oxygen in the air to form nickel oxide, the nickel oxide is a P-type semiconductor, the hole concentration of the nickel oxide is higher than that of common P-type gallium nitride, a good ohmic contact is formed between the first conductive layer 52 and the P-type gallium nitride layer 30, and a good ohmic contact is formed between the second conductive layer 62 and the P-type gallium nitride layer 30. The first conductive layer 52 and the second conductive layer 62 may be made of gold, which has good conductivity and stable physical and chemical properties, so as to stably apply electrical signals to the source electrode 50 and the drain electrode 60.
The embodiment of the utility model also provides a preparation method of the P-type channel gallium nitride device. Fig. 5 is a schematic flow chart of a method for manufacturing a P-channel gan device according to an embodiment of the present invention.
Fig. 6-9 are flow charts corresponding to steps of a method for fabricating a P-channel gan device according to an embodiment of the present invention. Referring to fig. 5, the method for preparing the P-channel gallium nitride device comprises the following steps:
Referring to fig. 6, a gallium nitride substrate 10 is provided.
Referring to fig. 7, an aluminum gallium nitride buffer layer 20 is formed on the surface of the gallium nitride substrate 10.
And step 130, forming a P-type gallium nitride layer on the surface of the gallium nitride aluminum buffer layer far away from the gallium nitride substrate.
Referring to fig. 8, a P-type gallium nitride layer 30 is formed on the surface of the aluminum gallium nitride buffer layer 20 away from the gallium nitride substrate 10.
The gallium nitride-based semiconductor device has the characteristics of wide forbidden band, high electron drift saturation velocity, small dielectric constant, good conductivity and the like, so that the power electronic device has good electrical properties.
And 140, forming a high-resistance doped region on the surface of the P-type gallium nitride layer far away from the gallium nitride aluminum buffer layer, wherein the resistivity of the high-resistance doped region is greater than that of the non-doped region of the P-type gallium nitride layer, and the doping depth of the high-resistance doped region is less than the thickness of the P-type gallium nitride layer.
Referring to fig. 9, a high-resistance doped region 31 is formed on the surface of the P-type gallium nitride layer 30 away from the gan-al buffer layer 20, wherein the resistivity of the high-resistance doped region 31 is greater than the resistivity of the undoped region 32 of the P-type gallium nitride layer 30, and the doping depth H1 of the high-resistance doped region 31 is less than the thickness H2 of the P-type gallium nitride layer 30.
Note that the undoped region 32 of the P-type gallium nitride layer 30 between the high-resistance doped region 31 and the aluminum gallium nitride buffer layer 20 is referred to as a P-type channel region 32A, and a projection of the P-type channel region 32A on the gallium nitride substrate 10 coincides with a projection of the high-resistance doped region 31 on the gallium nitride substrate 10. When a positive bias is applied to the gate 40, a large number of holes flow through the P-channel region 32A, and the P-channel gan device is in an on state. In the case where no voltage is applied to the gate electrode 40, the hole concentration in the P-type channel region 32A is low, and the P-type channel gallium nitride device is in an off state.
And 150, forming a gate on the surface of the P-type gallium nitride layer of the high-resistance doped region, which is far away from the gallium nitride aluminum buffer layer, wherein the projection of the high-resistance doped region on the gallium nitride substrate is positioned in the projection of the gate on the gallium nitride substrate.
Taking fig. 1 as an example, a gate 40 is formed on the surface of the P-type gan layer 30 of the high-resistance doped region 31 away from the gan-al buffer layer 20, wherein the projection of the high-resistance doped region 31 on the gan substrate 10 is located within the projection of the gate 40 on the gan substrate 10. The arrangement of the high-resistance doped region 31 reduces the hole concentration of the gate 40 in the projection region of the gallium nitride substrate 10, when a positive bias is applied to the gate 40, the non-doped region 32 of the P-type gallium nitride layer 30 between the high-resistance doped region 31 and the gallium nitride aluminum buffer layer 20 is called a P-type channel region 32A, a large number of holes flow through the P-type channel region 32A, and the P-type channel gallium nitride device is in an open state.
Taking fig. 1 as an example, a source electrode 50 and a drain electrode 60 are formed on the surface of the P-type gallium nitride layer 30 of the undoped region 32 away from the aluminum gallium nitride buffer layer 20.
In the technical solution provided by the embodiment of the present invention, the gate 40 is located on the surface of the P-type gallium nitride layer 30 of the high-resistance doped region 31 away from the surface of the gallium nitride aluminum buffer layer 20, the projection of the high-resistance doped region 31 on the gallium nitride substrate 10 is located in the projection of the gate 40 on the gallium nitride substrate 10, and the resistivity of the high-resistance doped region 31 is greater than the resistivity of the non-doped region 32 of the P-type gallium nitride layer 30, that is, the hole concentration in the high-resistance doped region 31 is less than the hole concentration of the P-type gallium nitride layer 30 of the non-doped region 32, compared with a P-type channel gallium nitride device without the high-resistance doped region 31, the P-type channel gallium nitride device provided by the embodiment of the present invention reduces the hole concentration of the gate 40 in the projection region of the gallium nitride substrate 10, when a positive bias is applied to the gate 40, the non-doped region 32 of the P-type gallium nitride layer 30 between the high-resistance doped region 31 and the gallium nitride aluminum buffer layer 20 is called a P-type channel region 32A, the P-channel region 32A has a large number of holes flowing through it, and the P-channel gan device is in an on state. Under the condition that no voltage is applied to the grid 40, the P-type channel gallium nitride device is in an off state, an enhanced P-type channel gallium nitride device is formed, negative voltage bias is not required to be additionally designed to turn off the device, the complexity of circuit design can be improved, and meanwhile, static power consumption and switching loss under the off state of the circuit are reduced.
Optionally, on the basis of the foregoing technical solution, the step 140 of forming the high-resistance doped region on the surface of the P-type gallium nitride layer away from the gallium aluminum nitride buffer layer includes:
and forming a high-resistance doped region of hydrogen element and/or oxygen element on the surface of the P-type gallium nitride layer far away from the gallium aluminum nitride buffer layer, wherein the P-type gallium nitride layer comprises a P-type gallium nitride layer doped with magnesium element.
Referring to fig. 9, a highly resistive doped region 31 of hydrogen element and/or oxygen element is formed on the surface of the P-type gallium nitride layer 30 away from the aluminum gallium nitride buffer layer 20, wherein the P-type gallium nitride layer 30 includes a P-type gallium nitride layer 30 doped with magnesium element.
It is known that the P-type gan layer 30 can be formed by doping the intrinsic gan material with P-type dopant to obtain the P-type gan layer 30. Illustratively, in the P-type gallium nitride layer 30 doped with magnesium element in the embodiment of the present invention, the more magnesium atoms are used to substitute for gallium atoms and form bonds with nitrogen atoms, the higher the hole concentration of the P-type gallium nitride layer 30 is, hydrogen is doped in the P-type gallium nitride layer 30 doped with magnesium element, magnesium-hydrogen bonds can be formed between hydrogen atoms and magnesium atoms, the number of magnesium atoms to substitute for gallium atoms and form bonds with nitrogen atoms is reduced, and further, the hole concentration of the P-type gallium nitride layer 30 doped with magnesium element is reduced, accordingly, the resistivity of a doped region formed by hydrogen is increased, and further, the high-resistance doped region 31 doped with hydrogen is formed. Oxygen is doped in the P-type gallium nitride layer 30 doped with magnesium, on the first hand, magnesium-hydrogen bonds can be formed between hydrogen atoms and magnesium atoms, so that the number of bonds formed by the magnesium atoms instead of gallium atoms and nitrogen atoms is reduced, and further, the hole concentration of the P-type gallium nitride layer 30 doped with magnesium is reduced; in the second aspect, the resistivity of the reactant formed by the reaction of the oxygen atoms and the gallium nitride is increased, and therefore the resistivity of the doped region formed by the oxygen element is increased, and the oxygen-doped high-resistance doped region 31 is formed. Therefore, compared with a P-type channel gallium nitride device without the high-resistance doping region 31, the P-type channel gallium nitride device provided by the embodiment of the utility model reduces the hole concentration of the gate 40 in the projection region of the gallium nitride substrate 10, and when a positive bias is applied to the gate 40, a large number of holes flow through the P-type channel region 32A, and the P-type channel gallium nitride device is in an open state. Under the condition that no voltage is applied to the grid 40, the P-type channel gallium nitride device is in an off state, an enhanced P-type channel gallium nitride device is formed, negative voltage bias is not required to be additionally designed to turn off the device, the complexity of circuit design can be improved, and meanwhile, static power consumption and switching loss under the off state of the circuit are reduced.
Optionally, on the basis of the foregoing technical solution, the step 140 of forming the high-resistance doped region on the surface of the P-type gallium nitride layer away from the gallium aluminum nitride buffer layer includes:
and forming a high-resistance doped region on the surface of the P-type gallium nitride layer far away from the gallium nitride aluminum buffer layer by a plasma doping process.
Referring to fig. 9, through the plasma doping process, the high-resistance doped region 31 is formed on the surface of the P-type gallium nitride layer 30 away from the gallium aluminum nitride buffer layer 20, the doping efficiency of the plasma doping process is high, the doping uniformity of the formed high-resistance doped region 31 is high, and the yield of the formed P-type channel gallium nitride device is high.
Fig. 10-12 are cross-sectional views corresponding to steps of another method for fabricating a P-channel gan device according to an embodiment of the utility model. Optionally, on the basis of the foregoing technical solution, step 140 includes, before forming the high-resistance doped region on the surface of the P-type gallium nitride layer away from the gallium aluminum nitride buffer layer:
and forming a groove on the surface of the P-type gallium nitride layer far away from the gallium nitride aluminum buffer layer, wherein the depth of the groove is less than the thickness of the P-type gallium nitride layer.
Referring to fig. 10, a groove 32B is formed on the surface of the P-type gallium nitride layer 30 away from the aluminum gallium nitride buffer layer 20, and the depth H3 of the groove 32B is smaller than the thickness H2 of the P-type gallium nitride layer 30.
Correspondingly, the step 140 of forming the high-resistance doped region on the surface of the P-type gan layer away from the gan-al buffer layer includes:
and forming a high-resistance doped region on the bottom surface of the groove, wherein the doping depth of the high-resistance doped region is smaller than the vertical distance between the bottom surface of the groove and the surface of the P-type gallium nitride layer adjacent to the gallium nitride aluminum buffer layer.
Referring to fig. 11, a high-resistance doped region 31 is formed at the bottom surface of the groove 32B, wherein the doping depth H1 of the high-resistance doped region 31 is smaller than the vertical distance H4 between the bottom surface of the groove 32B and the surface of the P-type gallium nitride layer 30 adjacent to the aluminum gallium nitride buffer layer 20.
Specifically, the arrangement of the groove 32B shortens the distance between the gate 40 and the P-type channel region 32A, and enhances the control capability of the gate 40 on the P-type channel gallium nitride device.
Fig. 13 is a schematic flow chart included in step 150 in fig. 5. Optionally, on the basis of the foregoing technical solution, the step 150 of forming a gate on the surface of the P-type gallium nitride layer of the high resistance doped region, which is far away from the gallium aluminum nitride buffer layer, includes:
Referring to fig. 12, a dielectric layer 70 is formed on the side of the P-type gallium nitride layer 30 away from the gallium nitride substrate 10, and the projection of the dielectric layer 70 on the gallium nitride substrate 10 has no overlap with the projection of the source 50 and the drain 60 on the gallium nitride substrate 10. Illustratively, the material of the dielectric layer 70 may be selected from silicon oxide, silicon nitride, or a stack of silicon oxide and silicon nitride.
And 1502, forming a grid on the surface of one side of the dielectric layer far away from the P-type gallium nitride layer.
Taking fig. 3 as an example, the gate 40 is formed on the surface of the dielectric layer 70 on the side away from the P-type gallium nitride layer 30.
Specifically, the introduction of the dielectric layer 70 can protect the P-type gallium nitride layer 30 when the gate 40 is manufactured; on the other hand, the introduction of the dielectric layer 70 reduces the gate leakage of the P-channel gan device.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the utility model. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (5)
1. A P-channel gan device, comprising:
a gallium nitride substrate;
the gallium nitride aluminum buffer layer is positioned on the surface of the gallium nitride substrate;
the P-type gallium nitride layer is positioned on the surface of the gallium nitride aluminum buffer layer away from the gallium nitride substrate;
the high-resistance doped region is positioned on the surface, far away from the gallium nitride aluminum buffer layer, of the P-type gallium nitride layer, wherein the resistivity of the high-resistance doped region is greater than that of the non-doped region of the P-type gallium nitride layer, and the doping depth of the high-resistance doped region is smaller than the thickness of the P-type gallium nitride layer;
the grid is positioned on the surface, far away from the surface of the gallium nitride aluminum buffer layer, of the P-type gallium nitride layer of the high-resistance doped region, and the projection of the high-resistance doped region on the gallium nitride substrate is positioned in the projection of the grid on the gallium nitride substrate;
and the source electrode and the drain electrode are positioned on the surface of the P-type gallium nitride layer of the non-doped region, which is far away from the gallium nitride aluminum buffer layer.
2. The P-channel gan device of claim 1 wherein the highly resistive doped region comprises a highly resistive doped region of hydrogen and/or a highly resistive doped region of oxygen.
3. The P-channel gan device of claim 1 wherein the surface of the P-type gan layer away from the gan buffer layer is provided with a groove, the depth of the groove being less than the thickness of the P-type gan layer; the high-resistance doped region is positioned on the bottom surface of the groove, wherein the doping depth of the high-resistance doped region is smaller than the vertical distance between the bottom surface of the groove and the surface of the P-type gallium nitride layer adjacent to the gallium nitride aluminum buffer layer.
4. The P-channel gan device of claim 1 further comprising a dielectric layer on a side of the P-type gan layer away from the gan substrate, wherein a projection of the dielectric layer on the gan substrate does not overlap with a projection of the source and the drain on the gan substrate, and the gate is on a surface of the dielectric layer on a side away from the P-type gan layer.
5. The P-channel gan device of claim 1 wherein the source comprises a first ohmic contact metal layer and a first conductive layer;
the first ohmic contact metal layer is positioned on one side of the P-type gallium nitride layer far away from the gallium nitride substrate;
the first conducting layer is positioned on the surface of one side, away from the P-type gallium nitride layer, of the first ohmic contact metal layer;
and/or the drain electrode comprises a second ohmic contact metal layer and a second conductive layer;
the second ohmic contact metal layer is positioned on one side of the P-type gallium nitride layer far away from the gallium nitride substrate;
the second conducting layer is located on the surface of the second ohmic contact metal layer, far away from one side of the P-type gallium nitride layer.
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