CN216013727U - Planar optical waveguide chip - Google Patents

Abstract

The utility model provides a planar optical waveguide chip, comprising: the silicon substrate, the lower cladding, the core layer, the upper cladding and the groove; the lower cladding layer is coupled to the upper surface of the silicon substrate; the upper cladding layer is coupled to an upper surface of the lower cladding layer; the core layer is positioned in the upper cladding layer and is coupled to the upper surface of the lower cladding layer; the trench penetrates the upper cladding layer, the core layer, and into the lower cladding layer from an upper surface of the upper cladding layer. According to the planar optical waveguide chip provided by the utility model, the grooves are generated on the existing chip structure by adopting a semiconductor process, and the generated grooves play roles of isolating heat propagation, blocking scattered light and the like between waveguides, so that the chip does not need an additional semiconductor refrigerator for temperature control, the heat dissipation power consumption of the chip is effectively reduced, and a chip-level heat-insensitive packaging mode is provided.

Description

Planar optical waveguide chip

Technical Field

The utility model relates to the technical field of optical fiber communication, in particular to a planar optical waveguide chip.

Background

The Planar Lightwave Circuit (PLC) chip is used as a core device chip of a wavelength division multiplexing passive optical network, and an optical device chip for processing complex functional optical signals is realized by integrating optical elements together by using a semiconductor process, and has the advantages of small wavelength interval, large channel number, uniform channel loss, small size, easiness in integration, convenience in batch production and the like. At present, PLC chips have been widely used in Optical splitters (Splitter), Array Waveguide Gratings (AWG), Optical Switches (OSW), Variable Optical Attenuators (VOA), and passive and active device fusion, such as VMUX (AWG + VOA), MCS (Switch + VOA), WSS (Switch + AWG).

The high-quality optical waveguide chip requires stable chip structure, and needs to achieve good scattered light management to avoid optical index deterioration conditions such as poor crosstalk characteristics between optical device channels and large return loss caused by poor control of the thickness of an upper cladding layer in the chip process, or light transmission leakage caused by overlarge bending size of a waveguide in chip design, or problems such as optical field mode matching in a temperature-changing use environment.

In addition, the high-quality PLC chip controls the beam splitting and coupling of the waveguide light beam, and also fully considers the power consumption of the power supply so as to avoid the light field leakage of more modes generated by the transmission light caused by the heating of the waveguide. For 5G outdoor scene application, higher requirements are put forward on performance indexes of the PLC chip. To solve these problems, an additional semiconductor Cooler (TEC) is usually used to control and manage the temperature of the PLC chip.

The scheme of adopting the TEC for electric heating is inflexible in use except that an electric interface and a control interface are required to be reserved; and because the constant temperature of the PLC chip is generally set to be more than 55 ℃, the TEC is adopted, except that the power consumption is larger, and in the packaging process link, the requirements on material and glue selection and related reliability are higher.

SUMMERY OF THE UTILITY MODEL

Aiming at the problems in the prior art, the embodiment of the utility model provides a planar optical waveguide chip and a preparation method thereof.

In a first aspect, the present invention provides a planar optical waveguide chip, comprising: the silicon substrate, the lower cladding, the core layer, the upper cladding and the groove; the lower cladding layer is coupled to the upper surface of the silicon substrate; the upper cladding layer is coupled to an upper surface of the lower cladding layer; the core layer is positioned in the upper cladding layer and is coupled to the upper surface of the lower cladding layer; the trench penetrates the upper cladding layer, the core layer, and into the lower cladding layer from an upper surface of the upper cladding layer.

In one embodiment, the trench extends through the lower cladding layer and into the silicon substrate.

In one embodiment, the trench extends through the silicon substrate.

In one embodiment, the groove is filled with ultraviolet curing glue; the ultraviolet curing glue is used for absorbing stray light in the core layer and absorbing heat in the core layer.

In one embodiment, the cross-section of the trench through the core layer is at the rowland circle between the waveguides.

In one embodiment, the trench is angled from 85 ° to 90 ° from the upper surface of the upper cladding layer.

In one embodiment, the number of the grooves is multiple; all the grooves are arranged in parallel.

In one embodiment, the core layer is coated with planar optical waveguide circuits and variable optical attenuation circuits which are arranged at intervals; a first electrode and a second electrode are fused on the upper surface of the upper cladding; the first electrodes are arranged above the planar optical waveguide circuit at intervals; the second electrode is arranged above the variable light attenuation circuit at intervals.

In one embodiment, the thickness of the metal mask layer is 1-2 μm; accordingly, the thickness of the upper cladding layer is 10-20 μm.

In a second aspect, the present invention provides a method for preparing a planar optical waveguide chip, including: preparing a silicon substrate, a lower cladding, a core layer and an upper cladding in sequence; masking a metal material on the upper surface of the upper cladding to generate a metal mask layer; spin-coating a photoresist layer on the upper surface of the metal mask layer, wherein an opening pattern of a groove is arranged on the photoresist layer; taking the photoresist layer as a mask layer, and carrying out metal etching on the metal mask layer; taking the metal mask layer as a mask layer, and carrying out oxygen silicon deep etching to generate the trench; the trench penetrates the upper cladding layer, the core layer, and into the lower cladding layer from an upper surface of the upper cladding layer.

According to the planar optical waveguide chip provided by the utility model, the grooves are generated on the existing chip structure by adopting a semiconductor process, and the generated grooves play roles of isolating heat propagation, blocking scattered light and the like between waveguides, so that the chip does not need an additional semiconductor refrigerator for temperature control, the heat dissipation power consumption of the chip is effectively reduced, and a chip-level heat-insensitive packaging mode is provided.

Drawings

In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a conventional PLC chip;

FIG. 2 is a schematic structural diagram of a PLC chip provided by the present invention;

FIG. 3 is a second schematic structural diagram of a PLC chip provided by the present invention;

FIG. 4 is a third schematic structural diagram of a PLC chip provided by the present invention;

FIG. 5 is a fourth schematic structural diagram of a PLC chip provided by the present invention;

FIG. 6 is a fifth schematic structural diagram of a PLC chip provided by the present invention;

fig. 7 is a flow chart illustrating a method for manufacturing a PLC chip according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that in the description of the embodiments of the present invention, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, article, or apparatus that comprises the element. The terms "upper", "lower", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the referenced items or elements must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are intended to be inclusive and mean, for example, that they may be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

Fig. 1 is a schematic structural diagram of a conventional PLC chip, as shown in fig. 1, which mainly includes: a silicon substrate 1, a lower cladding layer 2 (buffer layer), a core layer 3, and an upper cladding layer 4 (cladding layer). In the corresponding chip packaging process, the PLC chip needs to be coupled and packaged with the signal transmitting and receiving component through an optical fiber or a lens. For example, the AWG is directly optically connected to a single-core fiber or a multi-core array fiber, or the AWG is optically connected to a laser, a detector, or the like through a lens. In the actual coupling process of the waveguide, signal light is emitted by a light source, coupled to the input end of the PLC chip through an optical fiber or a lens, output from the output end of the PLC chip and enter the corresponding receiving component.

It is clear that, in addition to the requirement of stable chip structure, a high-quality PLC chip also needs to have good scattered light management to avoid optical index deterioration conditions such as poor crosstalk characteristics between channels of an optical device and large return loss caused by poor control of the thickness of an upper cladding layer in the chip process, or leakage of optical transmission due to overlarge waveguide bending size in chip design, or due to problems such as matching between optical field modes in a use environment with temperature change.

The existing PLC chip usually needs to adopt an additional TEC to control and manage the temperature of the chip, but the TEC needs to reserve an electrical interface and a control interface, so that the use is not flexible, and in a packaging process link, higher requirements are provided for the selection of materials and glue and the related reliability.

In view of the above problems of the PLC chip used in the prior art, the present invention provides a new PLC chip, and the PLC chip provided in the embodiments of the present invention and the method for manufacturing the same will be described with reference to fig. 1 to 7.

Fig. 2 is a schematic structural diagram of a PLC chip provided by the present invention, as shown in fig. 2, including but not limited to a silicon substrate 1, a lower cladding layer 2, a core layer 3, an upper cladding layer 4, and a trench 5;

the lower cladding layer 2 is coupled to the upper surface of the silicon substrate 1; the upper cladding layer 4 is coupled to the upper surface of the lower cladding layer 2; the core layer 3 is positioned in the upper cladding layer 4 and is coupled to the upper surface of the lower cladding layer 2; the trench 5 penetrates the upper cladding layer 4, the core layer 3, and the lower cladding layer 2 from the upper surface of the upper cladding layer 4.

It should be noted that the PLC chip provided by the present invention is designed and manufactured by adding at least one trench 5 on the basis of the conventional PLC chip. Wherein the trench 5 penetrates the entire upper cladding layer 4, the core layer 3, and the lower cladding layer 2, and penetrates a part or all of the silicon substrate 1.

It should be noted that, the planar optical waveguide chip provided by the present invention, by adding the trench 5 (which does not obstruct normal operation of the waveguide), the trench 5 can play a role in isolating heat propagation and blocking scattered light between waveguides, so as to solve the technical problems of small process tolerance, large power consumption of a packaged device, and the like in the manufacturing technology of the PLC chip, and ensure that the PLC chip can reduce power consumption required by the heat dissipation chip while exerting the light transmission characteristic, so that the chip does not need an additional TEC for temperature control, thereby implementing a chip-level heat-insensitive packaging manner.

Optionally, the cross-section of the trench 5 through the upper cladding layer 4, the core layer 3 and the lower cladding layer 2 is smooth and has an angle with the upper cladding layer 4, the core layer 3 and the lower cladding layer 2 to ensure that the signal light that is scattered and propagated does not return to the waveguide for input.

According to the planar optical waveguide chip provided by the utility model, the grooves are generated on the existing chip structure by adopting a semiconductor process, and the generated grooves 5 play roles in isolating heat propagation, blocking scattered light and the like between waveguides, so that the chip does not need an additional semiconductor refrigerator for temperature control, the heat dissipation power consumption of the chip is effectively reduced, and a chip-level heat-insensitive packaging mode is provided.

Fig. 3 is a second schematic structural diagram of the PLC chip provided in the present invention, and as an alternative embodiment, as shown in fig. 3, the trench 5 penetrates through the lower cladding layer 2 and enters into the silicon substrate 1.

In the PLC chip according to the present invention, the added trench 5 is mainly used to isolate heat propagation between waveguides, and thus the depth of the trench is required to at least penetrate the core layer 3.

As an alternative embodiment, the depth of the trench 5 is set to: penetrates through the lower cladding layer 2 and partially enters the silicon substrate 1, so that the heat dissipation capability of the trench 5 can be further improved under the condition that the groove depth of the trench 5 is increased.

Fig. 4 is a third schematic structural diagram of the PLC chip provided in the present invention, and as shown in fig. 4, the trench 5 penetrates through the silicon substrate 1.

As another alternative, the trench 5 starts from the upper surface of the upper cladding layer 4, penetrates the upper cladding layer 4, the core layer 3, and enters the lower cladding layer 2, and finally penetrates the lower cladding layer 2 and the silicon substrate 1.

According to the PLC chip provided by the utility model, the groove depth of the groove is set to penetrate through the upper cladding layer, the core layer, the lower cladding layer and the silicon substrate 1, so that the heat dissipation capability of the PLC chip can be further improved.

Based on the content of the above embodiment, as an optional embodiment, the trench 5 is filled with an Ultraviolet (UV) curing adhesive; the UV curing glue is used to absorb stray light in the core layer 3 and to absorb heat in the core layer 3.

It should be noted that, since the trench 5 can be filled with the glue having a strong heat dissipation capability and a certain absorption effect on the signal light, the glue filled only needs to have a good filling characteristic after curing, so as to further improve the heat absorption and stray signal light blocking effects of the trench 5 in the whole structure. The utility model adopts UV curing glue to fill the groove 5, but is not limited to heat curing, glue composition and the like, and can fully meet the requirement.

Based on the above description of the embodiments, as an alternative embodiment, the cross section of the trench 5 when penetrating the core layer 3 is located at the Rowland circle (Rowland circle) between the waveguides.

The Rowland circle is a reflection grating formed by etching a series of parallel lines with equal intervals on a concave spherical surface reflection mirror surface, and has light splitting capacity and light gathering capacity. If the slit light source and the concave grating are placed on a circle whose diameter is equal to the radius of curvature of the concave grating and the circle is tangent to the grating midpoint G, the spectrum formed by the concave grating appears on this circle, which is called the rowland circle.

It should be noted that the added trench 5 in the PLC chip provided by the present invention is used to absorb the waveguide in the core layer to perform the functions of isolating heat propagation and blocking scattered light, etc., but on the other hand, it is also necessary to ensure that the added trench 5 cannot affect the normal propagation of the waveguide, and therefore, the cross section of the trench 5 penetrating through the core layer 3 is set to be the rowland circle between the waveguides, which can simultaneously satisfy the above two requirements.

The upper cladding layer 4, the core layer 3, the lower cladding layer 2 and the silicon substrate 1 sequentially form a sandwich structure, as an optional embodiment, an included angle between the trench 5 and the upper surface of the upper cladding layer 4 can be set to be any angle, but considering the difficulty of preparation, the fact that the trench 5 cannot influence the normal propagation of the waveguide and other factors, the included angle between the trench 5 and the upper surface of the upper cladding layer 4 is set to be 85-90 degrees.

Fig. 5 is a fourth schematic structural diagram of a PLC chip provided in the present invention, and as shown in fig. 5, the number of the grooves 5 is multiple; all the grooves 5 are arranged in parallel.

In the case where the number of the trenches 5 is plural (e.g., 6), the trench depth of each trench 5 may be the same or different, but each trench penetrates at least the upper cladding layer 4, the core layer 3, and the lower cladding layer 2.

Fig. 6 is a fifth schematic structural view of the PLC chip according to the present invention, and as shown in fig. 6, each trench 5 penetrates through the upper cladding layer 4, the core layer 3, the lower cladding layer 2, and the silicon substrate 1.

The utility model can further improve the capability of isolating heat propagation and blocking scattered light by arranging a plurality of channels (such as 4 channels).

As an alternative embodiment, as shown in fig. 4 and fig. 6, the core layer 3 is coated with planar optical waveguide circuits 31 and variable optical attenuation circuits 32 which are arranged at intervals; a first electrode 7 and a second electrode 8 are fused on the upper surface of the upper cladding layer 4; the first electrode 7 is arranged above the planar optical waveguide circuit 31 at intervals; the second electrode 8 is disposed above the variable optical attenuator circuit 32 at an interval.

The utility model provides a thermo-optical integrated PLC chip (also called thermo-optical integrated chip), which comprises a conventional silicon substrate 1, a lower cladding layer 2, a core layer 3 and an upper cladding layer 4, wherein a first electrode 7 and a second electrode 8 are deposited on the upper surface of the core layer 3 of an optical waveguide, and the two electrodes have the functions of conducting electricity or phase modulation and the like. Thus, in the packaging process of the corresponding thermo-optical integrated chip, voltage and current are applied to the two electrodes. For example, in a VOA chip, an optical waveguide adopts a related principle of a Mach-Zehnder interferometer structure (abbreviated as MZI), the electrode is heated, and the refractive index of the material is changed by using a thermo-optical effect, so that the length of an interference arm of the MZI is changed, different optical path differences are generated between the two arms, and the control of optical attenuation is realized.

Further, an anti-oxidation layer 6 may be further clad on the first electrode 7 and the second electrode 8, for example: and the SiNx and SiO2 layers are used for prolonging the service life of the whole PLC chip.

Fig. 7 is a schematic flow chart of a method for manufacturing a PLC chip according to the present invention, as shown in fig. 7, which mainly includes, but is not limited to, the following steps:

step S1: preparing a silicon substrate 1, a lower cladding layer 2, a core layer 3 and an upper cladding layer 4 in sequence;

step S2: masking a metal material on the upper surface of the upper cladding 4 to generate a metal mask layer;

step S3: spin-coating a photoresist layer on the upper surface of the metal mask layer, wherein an opening pattern of a groove is arranged on the photoresist layer;

step S4: taking the photoresist layer as a mask layer, and carrying out metal etching on the metal mask layer;

step S5: taking the metal mask layer as a mask layer, and carrying out oxygen silicon deep etching to generate the trench 5; the trench 5 penetrates the upper cladding layer 4, the core layer 3, and the lower cladding layer 2 from the upper surface of the upper cladding layer 4.

Optionally, the thickness of the metal mask layer is 1-2 μm; accordingly, the thickness of the upper cladding layer 4 is 10 to 20 μm.

As an alternative embodiment, the utility model provides a method for preparing a thermo-optical isolation structure of a PLC chip based on SiO2, comprising the following steps:

step 1: on the surface of the conventional PLC chip shown in fig. 1, a metal mask layer is formed by masking a material such as Al or Cr with a metal by sputtering, evaporation, or the like. Considering the requirement of deep oxygen silicon etching, the thickness of the metal mask layer can be controlled to be about 1-2 μm.

In addition, the thickness of the upper cladding layer 4 can be reduced to 10-20 μm, so as to reduce the overall thickness of the prepared PLC chip.

Alternatively, the trench 5 may be processed using a semiconductor process; the upper cladding layer 4, the core layer 3 and the lower cladding layer 2 can be generated by a dry etching process, and the silicon substrate 1 can be prepared by a wet etching process, which is not particularly limited in the utility model.

Step 2: PR-coating is adopted to coat photoresist, and the processes of photoetching, photoresist homogenizing, developing and the like are adopted to transfer the designed opening pattern of the groove 5 to the photoresist layer.

And step 3: and performing metal Etching by using the photoresist as a mask layer in the modes of Inductively Coupled Plasma (ICP), Reactive Ion Etching (RIE) and the like to form a hard metal layer, and removing the redundant photoresist to ensure the etched metal angle. In addition, the preparation process can also be carried out by adopting a wet process mode.

And 4, step 4: and performing oxygen silicon deep etching by using the metal mask layer as a mask layer by adopting an etching mode such as ICP/RIE (inductively coupled plasma etching/reactive ion etching) and the like to form a deeper groove 5, wherein the etching depth is generally more than 10 mu m so as to penetrate through the upper cladding layer 4, the core layer 3, the lower cladding layer 2 and part of the silicon substrate 1.

And 5: the silicon substrate 1 may be further etched and etched from the back side of the silicon wafer by wet etching, so that the trench 5 penetrates through the silicon substrate 1.

Step 6: cleaning the polymer residue on the side wall of the deep hole, and filling UV curing glue with the functions of light absorption and heat insulation.

It should be noted that, for the fabrication of the trench with a large opening size and a small requirement for the aspect ratio (e.g. less than 5:1), polysilicon may be used for masking, and PR-coating is used for coating photoresist and performing pattern transfer by photolithography, photoresist leveling, development and other processes. And finally, taking the polycrystalline silicon as a mask layer to etch the deep oxygen silicon.

Optionally, in the preparation process of the planar optical waveguide chip provided by the utility model, the deposition thickness of the upper cladding 4 can be reduced on the basis of the existing PLC, so as to reduce the overall difficulty of deep etching and reduce the birefringence stress influence caused by stress.

Alternatively, the grooves 5 of the PLC chip prepared by the present invention can be randomly distributed on the chip without obstructing the normal operation of the waveguide chip,

in addition, the grooves 5 in the PLC chip to be prepared are matched according to the actual use requirement. For example: for the requirement of signal light blocking, stray light needs to be blocked from returning to the input channel and entering the output channel so as to ensure the roughness of the side wall and the angle after etching; for the requirement of isolating heat propagation, the purpose of preventing heat diffusion and reducing power consumption is needed to ensure the etching of the through holes to achieve better effect.

Finally, the UV curing adhesive for filling the groove has good fluidity and filling, is easy to UV and heat curing, and has good heat insulation, light absorption and other properties after curing.

It should be noted that, in the specific implementation process of the method for manufacturing a planar optical waveguide chip according to the embodiment of the present invention, corresponding manufacturing steps may be appropriately adjusted according to differences of actual manufacturing objects to manufacture the planar optical waveguide chip described in any of the above embodiments, which is not described in detail in this embodiment.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (8)

1. A planar lightwave circuit chip comprising: the silicon substrate, the lower cladding, the core layer, the upper cladding and the groove;

the lower cladding layer is coupled to the upper surface of the silicon substrate; the upper cladding layer is coupled to an upper surface of the lower cladding layer; the core layer is positioned in the upper cladding layer and is coupled to the upper surface of the lower cladding layer;

the trench penetrates the upper cladding layer, the core layer, and into the lower cladding layer from an upper surface of the upper cladding layer.

2. The planar lightwave circuit chip of claim 1 wherein the trench extends through the lower cladding layer and into the silicon substrate.

3. The planar lightwave circuit chip of claim 2 wherein the trench extends through the silicon substrate.

4. The planar lightwave circuit chip of any of claims 1-3 wherein the trench is filled with an ultraviolet curable glue;

the ultraviolet curing glue is used for absorbing stray light in the core layer and absorbing heat in the core layer.

5. The planar lightwave circuit chip of any of claims 1-3 wherein the cross-section of the trench through the core is located at the rowland circle between the waveguides.

6. The planar lightwave circuit chip of any of claims 1-3 wherein the trench is angled from 85 ° to 90 ° from the upper surface of the upper cladding layer.

7. The planar lightwave circuit chip of any of claims 1-3 wherein the number of trenches is a plurality of channels; all the grooves are arranged in parallel.

8. The planar lightwave circuit chip of any of claims 1-3 wherein the core layer is clad with the planar lightwave circuit and the variable optical attenuation circuit disposed at intervals;

a first electrode and a second electrode are fused on the upper surface of the upper cladding;

the first electrodes are arranged above the planar optical waveguide circuit at intervals;

the second electrode is arranged above the variable light attenuation circuit at intervals.

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