CN215955280U - Semiconductor memory device with a plurality of memory cells - Google Patents

Abstract

The utility model discloses a semiconductor memory device, which includes a substrate and a first pattern. The first pattern is disposed on the substrate and extends along a first direction, the first pattern includes an extension portion and two end points, the two end points respectively include a first end pattern and a second end pattern, wherein the extension portion has a first width, the first end pattern includes an outer widening and an inner widening, a maximum width of the outer widening and a maximum width of the inner widening are different from each other and are both greater than the first width of the extension portion of the first pattern.

Description

Semiconductor memory device with a plurality of memory cells

Technical Field

The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor memory device formed by a multiple patterning (multiple patterning) process.

Background

In a semiconductor manufacturing process, a fine pattern with a precise dimension needs to be formed on an appropriate substrate or material layer, such as a semiconductor substrate/film layer, a dielectric material layer, or a metal material layer, by photolithography, etching, or other manufacturing processes. To achieve this, in the conventional semiconductor technology, a mask layer is formed over a target material layer so that a pattern is first formed in the mask layer to define these minute patterns, and then the pattern of the mask layer is transferred to the target material layer. Generally, the mask layer is, for example, a patterned photoresist layer formed by a photolithography process, and/or a patterned mask layer formed using the patterned photoresist layer.

As integrated circuits become more complex and the size of these micro patterns continues to decrease, the equipment and patterning methods used to generate the micro feature patterns must meet the stringent requirements of resolution and overlay accuracy (overlay accuracy), while the single patterning method cannot meet the resolution requirements or the requirements of the fabrication process for fabricating micro line width patterns. Therefore, how to improve the existing manufacturing process of these micro patterns is one of the important issues in the field today.

SUMMERY OF THE UTILITY MODEL

The utility model provides a semiconductor memory device, which forms material patterns which are parallel to each other and are alternately arranged by performing a patterning process of a material layer through a self-aligned multiple patterning (SAMP) process and different mask patterns, wherein two end points of each material pattern comprise asymmetric end patterns, and one end pattern of each material pattern comprises at least two widened parts, and the at least two widened parts are connected with extension parts of the material patterns, so that the reliability of the connection between the end patterns and the extension parts of the material patterns can be improved.

According to an embodiment of the present invention, a semiconductor memory device includes a substrate and a first pattern. The first pattern is disposed over a substrate and extends in a first direction, the first pattern including an extension portion and two end points including a first end pattern and a second end pattern, respectively, wherein the extension portion has a first width, the first end pattern includes an outer widening and an inner widening, and a maximum width of the outer widening and a maximum width of the inner widening are different from each other and are both greater than the first width of the extension portion of the first pattern.

According to an embodiment of the present invention, a method for forming a semiconductor device is provided, including providing a substrate; forming a material layer on the substrate, the material layer comprising opposing first and second sides, wherein the material layer comprises a plurality of protrusions on the first side; forming a plurality of strip-shaped masks on the material layer, wherein a partial region of one of the strip-shaped masks covers a partial region of one of the protrusions; forming a mask layer on the plurality of strip-shaped masks, wherein the mask layer comprises an opening, the edge of the opening, which is positioned on the first side, comprises a plurality of mask protruding parts, and each mask protruding part covers the partial area of the strip-shaped mask and the partial area of the protruding part; and etching the material layer by using the plurality of strip-shaped masks and the mask layer as etching masks.

The embodiments of the present invention can form the feature pattern with dense layout and relatively small size on the premise of simplifying the process, and can further improve the reliability of the electrical connection between the formed feature pattern, such as the conductive wire and the contact pad pattern.

Drawings

Fig. 1 to 6 are schematic plan views illustrating stages of a method for forming a semiconductor device according to an embodiment of the utility model.

Fig. 7 is a schematic plan view of a first pattern and a second pattern of a semiconductor memory device according to an embodiment of the present invention.

Fig. 8 is a partially enlarged schematic plan view of a first pattern according to another embodiment of the present invention.

Fig. 9 is a partially enlarged schematic plan view of a first pattern according to yet another embodiment of the present invention.

Wherein the reference numerals are as follows:

100 semiconductor device

100A first region

100B second region

101 substrate

103 material layer

103-1 main part

103-2 projection

103A first side

103B second side

105 first block pattern

107 second block pattern

111 bar mandrel

113 strip mask

114 ring mask

115 mask layer

115P mask projection

116 open mouth

116E edge

120 pattern

120A first side

120B second side

121 first pattern

121A extension part

121B outer widening

121C inner widening

121C-1 partial region

121C-2 partial region

121D connector

121V end face

121P-1 first end pattern

121P-2 second end pattern

122 second pattern

122A extension part

122B outer widening

122C inner widening

122P-1 third end pattern

122P-2 fourth end pattern

130 conductive plug

W1 first width

W2 second width

W3 third Width

W4 fourth Width

W5 fifth Width

Detailed Description

For a better understanding of the present invention, preferred embodiments will be described in detail below. Preferred embodiments of the present invention are illustrated by reference numerals in the figures. Furthermore, technical features in different embodiments described below may be replaced with, recombined with, or mixed with each other to constitute another embodiment without departing from the spirit of the present invention.

Referring to fig. 1 to 6, schematic plan views of stages of a method for forming a semiconductor device according to an embodiment of the utility model are shown. First, as shown in fig. 1, a substrate 101 is provided, and the substrate 101 is, for example, a silicon substrate, a silicon-on-insulator (SOI) substrate, or other semiconductor substrate. The substrate 101 may include a first region 100A and a second region 100B, the first region 100A is, for example, an element region for arranging memory cells, and the second region 100B is, for example, a peripheral region for arranging logic cells, but is not limited thereto. A material layer 103 is formed on the first region 100A of the substrate 101, the material layer 103 including a main portion 103-1 and a plurality of protrusions 103-2, wherein the main portion 103-1 includes first and second opposing edges, the plurality of protrusions 103-2 being disposed on the first and second edges of the main portion 103-1, in other words, the material layer 103 includes first and second opposing sides 103A and 103B, and the material layer 103 includes a plurality of protrusions 103B on the first and second sides 103A and 103B, wherein each of the plurality of protrusions 103-2 on the first side 103A and each of the plurality of protrusions 103-2 on the second side 103B do not coincide with each other in a first direction (e.g., the x direction shown in fig. 1).

In addition, a plurality of first block patterns 105 and second block patterns 107 are formed on the second region 100B of the substrate 101, wherein the first block patterns 105 and the second block patterns 107 are parallel to each other and extend along a first direction (e.g., the x direction shown in fig. 1), and the first block patterns 105 and the second block patterns 107 are alternately arranged and offset from each other in a second direction (e.g., the y direction shown in fig. 1), for example, the second direction is perpendicular to the first direction. In an embodiment, the material layer 103, the first block pattern 105 and the second block pattern 107 may be formed by a same photolithography process, and include the same material, for example, a conductive material, such as a low-resistance metal material, such as tungsten (W), aluminum (Al) or copper (Cu), or a dielectric material disposed below the conductive material, such as silicon oxide, silicon nitride (SiN), silicon oxynitride (SiON) or silicon carbonitride (SiCN), but not limited thereto. In addition, in an embodiment, the material layer 103, the first block pattern 105 and the second block pattern 107 may be directly formed on the substrate 101, but the specific arrangement of the semiconductor device of the present invention is not limited thereto, and in another embodiment, other layers or elements, such as a dielectric layer (not shown) may be additionally disposed between the material layer 103 and the substrate 101 according to the actual element requirement. In addition, in order to protect the top surfaces of the material layer 103, the first block pattern 105, and the second block pattern 107, a protection layer (not shown), such as silicon oxide, silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN), may be disposed on the top surfaces, respectively, but not limited thereto. The passivation layer may have the same profile as the corresponding underlying material layer 103, the first block pattern 105 and the second block pattern 107, and the passivation layer is removed at a suitable time. The above-mentioned protective layer is not shown here in order to make the present invention easy to understand.

Next, referring to fig. 2, a plurality of bar-shaped mandrels (mangrel) 111 are formed on the material layer 103, a partial region of one of the bar-shaped mandrels 111 covers a partial region of one of the protrusions 103-2, and the bar-shaped mandrels 111 also cover a main portion 103-1 of the material layer 103 in the first region 100A. In addition, the plurality of bar-shaped mandrels 111 may also extend along the first direction (e.g., the x direction shown in fig. 2) to the second region 100B. In one embodiment, the plurality of stripe-shaped mandrels 111 may be formed by photoresist, and a photoresist layer is coated on the material layer 103, and then the plurality of stripe-shaped mandrels 111 are formed by a photolithography process. In addition, the bar-shaped mandrels 111 may be formed by transferring a pattern in a photoresist layer to a layer below the photoresist layer.

Then, referring to fig. 3, spacers (spacers) 113 are formed on the sidewalls of the stripe mandrels 111, the material of the spacers 113 may be a mask material, such as silicon oxide, silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN), and the like, and the spacers 113 may be formed by depositing a mask material layer on the material layer 103, covering the stripe mandrels 111 and filling the gaps between the stripe mandrels 111, and then removing the mask material covering the top surfaces of the stripe mandrels 111 and removing a portion of the mask material between the stripe mandrels 111 by an etching process, leaving the spacers 113 on the sidewalls of the stripe mandrels 111, as shown in fig. 3, and the spacers 113 surround the stripe mandrels 111. According to an embodiment of the present invention, the width of the spacer 113 is smaller than the width of the bar-shaped mandrel 111, so that the dimension of the spacer 113 in one dimension may be the dimension of sub-lithography (sub-lithography).

Next, referring to fig. 4, each of the strip mandrels 111 is removed, leaving spacers 113 on the material layer 103, and in the following description, the spacers 113 may also be referred to as strip masks 113. In one embodiment, an etching process may be used to remove each strip mandrel 111. As shown in fig. 4, a partial region of one of the strip masks 113 covers a partial region of one of the protrusions 103-2, and each protrusion 103-2 is disposed corresponding to each strip mask 113, and two adjacent strip masks 113 form a part of the ring mask 114. In addition, a partial region of one of the two adjacent stripe masks 113 of the ring mask 114 covers a partial region of one of the protrusions 103-2 on the first side 103A, and a partial region of the other stripe mask 113 of the ring mask 114 covers a partial region of the other protrusion 103-2 on the second side 103B.

Then, referring to fig. 5, a mask layer 115 is formed on the plurality of stripe-shaped masks 113, and the mask layer 115 includes openings 116. As shown in FIG. 5, an edge 116E of the opening 116 is spaced apart from an edge of the main portion 103-1 of the material layer 103, i.e., the edge of the main portion 103-1 is separated from the edge 116E of the opening 116. According to an embodiment of the present invention, the mask layer 115 further includes a plurality of mask protrusions 115P disposed on the opening 116 at the edge 116E of the first side 103A and the edge 116E of the second side 103B, and each mask protrusion 115P on the first side 103A and each mask protrusion 115P on the second side 103B are not overlapped with each other in the first direction (e.g., the x direction shown in fig. 5). In addition, each mask protrusion 115P covers a portion of the stripe mask 113 and a portion of the protrusion 103-2. According to an embodiment of the present invention, the area of each protrusion 103-2 in a plan view is larger than the area of each mask protrusion 115P in a plan view. In one embodiment, the mask layer 115 may be formed of photoresist, and the mask layer 115 including the opening 116 and the plurality of mask protrusions 115P is formed using a photolithography process.

Thereafter, referring to fig. 5 and 6, the material layer 103 is etched using the plurality of stripe masks 113 and the mask layer 115 (including the openings 116 and the plurality of mask protrusions 115P) of fig. 5 as an etching mask, thereby forming a plurality of patterns 120 of the semiconductor device 100 shown in fig. 6. In an embodiment, the semiconductor device 100 is a semiconductor memory device, as shown in fig. 6, the semiconductor memory device includes a substrate 101, a plurality of patterns 120 includes a plurality of first patterns 121 and a plurality of second patterns 122 disposed on the substrate 101, the plurality of first patterns 121 and the plurality of second patterns 122 each extend along a first direction (e.g., an x direction shown in fig. 6), and the plurality of first patterns 121 and the plurality of second patterns 122 are alternately arranged along a second direction (e.g., a y direction shown in fig. 6), the second direction is non-parallel to the first direction, for example, the second direction may be perpendicular to the first direction. Each first pattern 121 has a first end pattern 121P-1 at the end of the first side 120A of the pattern 120, each second pattern 122 has a fourth end pattern 122P-2 at the end of the second side 120B of the pattern 120, and the first end patterns 121P-1 and the fourth end patterns 122P-2 are arranged in a left-right asymmetric manner, i.e., each first end pattern 121P-1 at the first side 120A and each fourth end pattern 122P-2 at the second side 120B are not overlapped with each other in a first direction (e.g., the x direction shown in FIG. 6). In the case that the first pattern 121, the second pattern 122, the first block pattern 105, and the second block pattern 107 have the protection layer (not shown) on the top surface thereof, the protection layer may be further removed, and then the conductive plugs (plugs) 130 electrically connected to the first pattern 121, the second pattern 122, the first block pattern 105, and the second block pattern 107 may be formed.

In one embodiment, each of the first pattern 121 and each of the second pattern 122 of the semiconductor memory device is a bit line (bitline) pattern having a conductive layer, and each of the conductive plugs 130 of the semiconductor memory device is disposed on each of the first end patterns 121P-1 and each of the fourth end patterns 122P-2. In addition, each conductive plug 130 is further disposed on each first block pattern 105 and each second block pattern 107 of the second region 100B.

Referring to fig. 7, a schematic plan view of the first pattern and the second pattern of the semiconductor memory device according to the embodiment of the utility model is shown. As shown in FIG. 7, the first pattern 121 includes an extension portion 121A and two end points, which respectively include a first end pattern 121P-1 and a second end pattern 121P-2. The first end pattern 121P-1 includes an outer widening 121B and an inner widening 121C, and the first end pattern 121P-1 includes an end surface 121V perpendicular to a first direction (e.g., the x-direction shown in FIG. 7), the end surface 121V is located between the outer widening 121B and the inner widening 121C, and both the outer widening 121B and the inner widening 121C include curved surfaces. In addition, according to the present embodiment, the plan view area of the outer widening portion 121B is larger than the plan view area of the inner widening portion 121C, and each conductive plug 130 overlaps the outer widening portion 121B. In one embodiment, the outer widening 121B directly contacts the inner widening 121C. In addition, the extension portion 121A has a maximum width, i.e., a first width W1. The outer widening 121B has a maximum width, i.e., a second width W2, and the inner widening 121C has a maximum width, i.e., a third width W3. According to an embodiment of the present invention, the second width W2 of the outer widening 121B and the third width W3 of the inner widening 121C are different from each other, and both the second width W2 and the third width W3 are greater than the first width W1 of the extension portion 121A. Further, the second width W2 of the outer widening 121B is greater than the third width W3 of the inner widening 121C.

Similarly, the second pattern 122 includes an extension portion 122A and two end points, which respectively include a third end pattern 122P-1 on the first side 120A and a fourth end pattern 122P-2 on the second side 120B. As shown in fig. 7, the third end pattern 122P-1 of the second pattern 122 overlaps a partial region of the inner widening 121C of the first pattern 121 in a second direction (e.g., the y direction shown in fig. 7), which may also be referred to as an overlapping region, and the second direction is non-parallel to the first direction, e.g., the second direction may be perpendicular to the first direction. In addition, other partial regions of the inner widening 121C of the first pattern 121, i.e., the partial regions that do not overlap with the third end pattern 122P-1 of the second pattern 122 (also referred to as non-overlapping regions), are disposed between the overlapping regions of the inner widening 121C and the outer widening 121B, and the other partial regions (non-overlapping regions) of the inner widening 121C are separated from the third end pattern 122P-1 of the second pattern 122 in the first direction (e.g., the x direction shown in fig. 7).

As shown in fig. 7, in one embodiment, the fourth end pattern 122P-2 of the second pattern 122 on the second side 120B includes an outer widening 122B and an inner widening 122C, the top area of the outer widening 122B is larger than the top area of the inner widening 122C, and the maximum width of the outer widening 122B is larger than the maximum width of the inner widening 122C, in one embodiment, the outer widening 122B directly contacts the inner widening 122C.

Fig. 8 is a schematic partially enlarged plan view of a first pattern according to another embodiment of the utility model. The difference between the first pattern 121 of fig. 8 and the first pattern 121 of fig. 7 is that the partial region 121C-1 of the inner widening 121C directly contacting the outer widening 121B has a constant width, i.e., a fourth width W4, while the partial region 121C-2 of the inner widening 121C directly contacting the extension 121A has a gradually changing width, and the width of the partial region 121C-2 gradually decreases from the fourth width W4 of the partial region 121C-1 to the first width W1 of the extension 121A in the direction from the outer widening 121B to the extension 121A.

Fig. 9 is a schematic partially enlarged plan view of a first pattern according to yet another embodiment of the utility model. The difference between the first pattern 121 of fig. 9 and the first pattern 121 of fig. 7 is that a connection portion 121D is further disposed between the inner widening 121C and the outer widening 121B, the connection portion 121D has a maximum width, i.e., a fifth width W5, and the fifth width W5 of the connection portion 121D is greater than the first width W1 of the extension portion 121A. In an embodiment, the fifth width W5 of the connecting portion 121D may be smaller than the second width W2 of the outer widening 121B and also smaller than the third width W3 of the inner widening 121C. In another embodiment, the fifth width W5 of the connection part 121D may be smaller than the second width W2 of the outer widening 121B and larger than the third width W3 of the inner widening 121C.

The structures illustrated in fig. 6 to 9 described above only show a part of the semiconductor device or the semiconductor memory device, and other components and structures may be included in the semiconductor device or the semiconductor memory device to realize the functions of the semiconductor device or the semiconductor memory device. For example, when the semiconductor device or the semiconductor memory device is a Dynamic Random Access Memory (DRAM), the substrate 101 may further include a plurality of active regions (not shown) surrounded by an insulating structure (not shown), such as a Shallow Trench Isolation (STI), and the active regions are disposed under the bit line patterns (formed by the first patterns 121 and the second patterns 122). Each active region may be electrically connected to a corresponding bit line pattern using a bit line plug (not shown). A plurality of word line patterns (not shown) may be further included in the substrate 101, which may extend along the second direction y and pass through the corresponding active regions. The substrate 101 may further include a plurality of capacitor structures (not shown) above, which may be electrically connected to one end of the active region in the substrate 101, respectively, for storing charges from the bit lines. It is to be noted that the above dram is only one aspect of the present invention, and the semiconductor device or the semiconductor memory device may be any other semiconductor device or semiconductor memory device without departing from the concept of the present invention.

According to an embodiment of the present invention, a patterning process of a material layer may be performed by a self-aligned multiple patterning (SAMP) process and different mask patterns to form a plurality of first patterns 121 and a plurality of second patterns 122 having relatively dense layouts and relatively small sizes, the plurality of first patterns 121 and the plurality of second patterns 122 may be used as conductive lines, such as bit lines of a semiconductor memory device, and asymmetric first end patterns 121P-1 and fourth end patterns 122P-2 may be formed at a first side 120A end of each first pattern 121 and a second side 120B end of each second pattern 122, respectively, each of the first end patterns 121P-1 and the fourth end patterns 122P-2 may include an outer widening and an inner widening and may be used as contact pads of the conductive lines, wherein the outer widening having a large area and a large maximum width in a plan view may be used to carry the conductive plug 130, therefore, the reliability of the electrical connection between the conductive plug and the contact pad is improved, the inner widening can increase the reliability of the interconnection between the outer widening and the extension portion, and the inner widening with a smaller maximum width can prevent or reduce the short circuit problem caused by the contact between the first end pattern 121P-1 of the first pattern 121 and the third end pattern 122P-1 of the adjacent second pattern 122. Therefore, the embodiment of the utility model can form the conducting wire and the contact pad pattern with high electrical connection reliability, dense layout and small size on the premise of simplifying the process, thereby improving the yield of the semiconductor device.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (11)

1. A semiconductor memory device, comprising:

a substrate; and

a first pattern disposed over a substrate and extending in a first direction, the first pattern including an extension portion and two end points including a first end pattern and a second end pattern, respectively, wherein the extension portion has a first width, the first end pattern includes an outer widening and an inner widening, a maximum width of the outer widening and a maximum width of the inner widening are different from each other and are both greater than the first width of the extension portion of the first pattern.

2. The semiconductor memory device according to claim 1, wherein the first end pattern includes an end face perpendicular to the first direction.

3. The semiconductor memory device according to claim 1, wherein a maximum width of the outer widening is larger than a maximum width of the inner widening.

4. The semiconductor memory device according to claim 1, further comprising a plurality of second patterns each extending along the first direction, wherein the plurality of second patterns and the plurality of first patterns are alternately arranged along a second direction, each of the second patterns comprises an end located at a first side, the end of each of the second patterns overlaps with a partial region of the inner widening in the second direction, and the second direction is non-parallel to the first direction.

5. The semiconductor memory device according to claim 4, wherein other partial regions of the inner widening are provided between the partial regions of the inner widening and the outer widening, the other partial regions of the inner widening being separated from the ends of the second pattern in the first direction.

6. The semiconductor memory device according to claim 4, wherein each of the second patterns includes another end disposed at the second side, the other end including an outer widening and an inner widening, the maximum width of the outer widening of the second pattern being greater than the maximum width of the inner widening of the second pattern.

7. The semiconductor memory device according to claim 1, wherein the outer widening directly contacts the inner widening.

8. The semiconductor memory device according to claim 1, wherein the outer widening and the inner widening comprise curved surfaces.

9. The semiconductor memory device according to claim 1, wherein a plan view area of the outer widening is larger than a plan view area of the inner widening.

10. The semiconductor memory device according to claim 1, wherein each of the first patterns and each of the second patterns is a bit line pattern having a conductive layer.

11. The semiconductor memory device according to claim 1, further comprising a plurality of conductive plugs, each of the conductive plugs overlapping the outer widened portion.

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